KR100268804B1 - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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KR100268804B1
KR100268804B1 KR1019970030243A KR19970030243A KR100268804B1 KR 100268804 B1 KR100268804 B1 KR 100268804B1 KR 1019970030243 A KR1019970030243 A KR 1019970030243A KR 19970030243 A KR19970030243 A KR 19970030243A KR 100268804 B1 KR100268804 B1 KR 100268804B1
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gas
thin film
tin
metal wiring
semiconductor device
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KR1019970030243A
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KR19990006021A (en
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채무성
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김영환
현대전자산업주식회사
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Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to form a Ti/TiN metal film as a diffusion barrier by using automatic layer epitaxy chemical vapor deposition method. CONSTITUTION: A diffusion barrier of a stacked structure of Ti/TiN formed on a lower portion of a metal line is formed by an automatic layer epitaxy chemical vapor deposition method. A TiCl4 gas is used as a source gas. An H2 gas and an ammonia gas are used as reaction gases. The stacked structure of Ti/TiN is formed by performing an in-situ process in one reaction furnace. The generated byproducts are purged by using an argon gas when forming the stacked structure of Ti/TiN.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 화학기상증착 방법중에서 ALE CVD(atomic layer epitaxy chemical vapor deposition)방법으로 반도체기판에 확산방지막인 Ti/TiN 금속박막을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a technique of forming a Ti / TiN metal thin film as a diffusion barrier on a semiconductor substrate by ALE CVD (atomic layer epitaxy chemical vapor deposition) method. .

일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.

상기 금속배선은 Ti/TiN 적층구조의 확산장벽층과, 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 물리기상증착(Physical Vapor Deposition, 이하에서 PVD 라 함)방법으로 형성하였다. 물론, 상기 Ti/TiN 적층구조는 화학기상증착(Chemical Vapor Deposition, 이하에서 CVD 라 함)방법으로 형성할 수도 있다.The metal wiring is a physical vapor deposition (Physical) of the diffusion barrier layer of the Ti / TiN laminated structure, and the aluminum alloy containing a small amount of silicon or copper in the aluminum (Al) or both silicon and copper with low resistivity and excellent workability Vapor Deposition, hereinafter referred to as PVD) method. Of course, the Ti / TiN laminated structure may be formed by chemical vapor deposition (hereinafter, referred to as CVD).

그러나, 상기 Ti/TiN 적층구조는 각각 다른 반응기 내에서 형성되어, 생산성이나 쓰루풋(throughput)측면에서 손실이 예상된다. 그리고, 상기 Ti 증착후 TiN형성을 위한 공정 분위기 변화시 Ti 박막의 막질 퇴화가 예상된다.However, the Ti / TiN laminates are formed in different reactors, so losses are expected in terms of productivity and throughput. After the Ti deposition, the film quality of the Ti thin film is expected to change when the process atmosphere for forming TiN is changed.

상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 확산방지막인 Ti/TiN 적층구조의 형성공정시 생산성의 저하, 막질 저하 및 쓰루풋과 같은 특성의 열화가 발생할 수 있어 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 수율 및 생산성을 저하시키는 문제점이 있다.As described above, the metal wiring formation method of the semiconductor device according to the prior art may cause degradation of characteristics such as productivity, film quality and throughput during the formation process of the Ti / TiN laminate structure, which is a diffusion barrier film. And lowering reliability and lowering yield and productivity of the semiconductor device.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, ALE CVD방법을 이용하여 하나의 반응로에서 Ti/TiN 적층구조를 용이하게 형성할 수 있도록 하는 반도체소자의 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, a method for forming metal wirings of a semiconductor device of a semiconductor device, which can easily form a Ti / TiN stacked structure in one reactor using the ALE CVD method. The purpose is to provide.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

반도체소자의 금속배선 형성공정시 금속배선 하부에 형성되는 Ti/TiN 적층 구조의 확산방지막을 ALE CVD 방법으로 형성하는 반도체소자의 금속배선 형성방법 으로서,As a method of forming a metal wiring in a semiconductor device in which a diffusion barrier layer of a Ti / TiN layer structure formed under the metal wiring is formed by the ALE CVD method in the metal wiring formation process of the semiconductor device,

TiCl4가스를 소오스가스로 고정하여 사용하고, 반응기체인 H2와 암모니아 가스를 각각 순차적으로 플로우시키며 하나의 반응로에서 인-시튜 공정으로 Ti/TiN 적층구조를 형성하고,TiCl 4 gas is fixed with a source gas, and H 2 and ammonia gas, respectively, are sequentially flowed and a Ti / TiN lamination structure is formed in an in-situ process in one reactor.

상기 Ti/TiN 적층구조 형성공정시 유발되는 부산물을 아르곤가스로 퍼지하는 공정을 포함하는 것을 특징으로 한다.And purging the by-products generated during the Ti / TiN laminate structure forming process with argon gas.

한편, 이상의 목적을 달성하기 위한 본 발명의 윈리는, Ti/TiN 증착시 전구체(precursor)로서 두 경우 모두 TiCl4을 사용하고, 반응기체는 Ti의 경우 H2가스를, TiN 의 경우는 NH3가스나 N2/H2혼합가스를 사용하고, 퍼지 가스(purge gas)는 아르곤(Ar)가스를 사용하여 ALE CVD 로 Ti/TiN 적층구조를 형성하되, 인-시튜(in-situ)로 하나의 반응기에서 순차적으로 증착함으로써 막질을 향상시키는 것이다.Meanwhile, in order to achieve the above object, the winry of the present invention uses TiCl 4 as a precursor during Ti / TiN deposition, and the reactor is H 2 gas for Ti and NH 3 for TiN. A gas or N 2 / H 2 mixed gas is used, and a purge gas is argon (Ar) gas to form a Ti / TiN laminated structure by ALE CVD, but in-situ By depositing sequentially in the reactor of the to improve the film quality.

참고로, 상기 ALE CVD 는 소오스가스와 퍼지 가스 그리고 반응기체를 사이클릭 펄스(cyclic pulse)로 공급시켜 사이클릭-모노레이어(cyclic-monolayer)를 형성하는 방법이고, 반도체기판 표면에서 흡착(adsorption)과 탈착(desorption)원리를 이용하여 약 10 Å정도의 매우 얇은 박막 두께까지 조절할 수 있으며, 다원계 박막의 조성을 정밀히 제어할 수 있고 박막 결함의 성장과 확산을 억제할 수 있다.For reference, the ALE CVD is a method of forming a cyclic-monolayer by supplying a source gas, a purge gas, and a reactor with a cyclic pulse, and adsorption on the surface of the semiconductor substrate. By using the principle of desorption (desorption) can be adjusted to a very thin film thickness of about 10 Å, it is possible to precisely control the composition of the multi-element thin film and to suppress the growth and diffusion of thin film defects.

이하, 도시되지는 않았으나 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, although not shown, the present invention will be described in detail.

먼저, TiCl4소오스를 0.1 ∼ 60 초간 10 ∼ 1000 sccm 의 유량만큼 한정적으로 공급시켜 TiCl4를 200 ∼ 700℃ 정도의 온도인 기판 상부에 흡착시킨 다음, 연속적으로 아르곤 가스를 10 ∼ 1000 sccm 만큼 흘려주어 소오스 퍼지를 0.1 ∼ 120초간 실시한다.First, TiCl 4 source is supplied at a limited flow rate of 10 to 1000 sccm for 0.1 to 60 seconds, and TiCl 4 is adsorbed onto the substrate having a temperature of about 200 to 700 ° C. Then, argon gas is continuously flowed by 10 to 1000 sccm. A source purge is performed for 0.1 to 120 seconds.

그후, 0.1 ∼ 60 초간 H2반응가스를 10 ∼ 1000 sccm 정도 흘려주어 반도체 기판 상부에 이미 흡착된 TiCl4위에 H2를 흡착시켜 하기 제1식과 같은 반응을 유발시킴으로써 반도체기판 상부에 Ti 모노레이어(monolayer)를 형성한다.Thereafter, the H 2 reaction gas was flowed for 10 to 1000 sccm for 0.1 to 60 seconds to adsorb H 2 onto TiCl 4 already adsorbed on the semiconductor substrate to cause a reaction as shown in the following formula 1 to form a Ti monolayer ( monolayer).

TiCl4(g) + 2H2(g) = Ti(s) + 4HCl(g) --------제1식TiCl 4 (g) + 2H 2 (g) = Ti (s) + 4HCl (g) -------- Formula 1

이때, 상기 반응기 내의 전체압력은 0.1 ∼ 5 Torr 정도를 유지한다. 그 후, 반응기체와 부산물, HCl을 퍼지시키기 위하여 아르곤 가스를 흘려준다.At this time, the total pressure in the reactor maintains about 0.1 to 5 Torr. Thereafter, argon gas is flowed to purge the reactor, by-products and HCl.

상기와 같은 싸이클(cycle)을 5 ∼ 2000 회 정도 반복하여 Ti 두께를 10 ∼ 500Å 정도의 두께로 형성한다.The cycle as described above is repeated 5 to 2000 times to form a Ti thickness of about 10 to 500 kPa.

그 다음에, 이와 같은 방법으로 TiN 박막을 상기 Ti 박막 상부에 증착하되, H2가스 대신 암모니아가스(NH3)로 교체한다. 이 경우는, 이미 형성된 Ti 박막 표면 상부에 다시 TiCl4가 흡착되고, 그 상부에 흡착되는 암모니아 가스는 하기 제2식과 같이 반응하여 TiN 모노레이어를 형성한다. 그리고, 상기 TiN 박막을 10 ∼ 600Å정도의 두께로 형성하기 위하여 상기와 같은 싸이클을 5 ∼ 2000 회 반복한다.Then, a TiN thin film is deposited on the Ti thin film in this manner, but replaced with ammonia gas (NH 3 ) instead of H 2 gas. In this case, TiCl 4 is again adsorbed on the surface of the already formed Ti thin film, and the ammonia gas adsorbed on the upper portion reacts as in the following formula 2 to form a TiN monolayer. The same cycle is repeated 5 to 2000 times in order to form the TiN thin film with a thickness of about 10 to 600 kPa.

6TiCl4(g) + 8NH3(g) = 6TiN(s) + 24HCl(g) + 8N2(g) - 제2식6TiCl 4 (g) + 8NH 3 (g) = 6TiN (s) + 24HCl (g) + 8N 2 (g)-Formula 2

그 다음에, 상기 제1식과 제2식의 반응으로 인하여 유발된 반응물, 즉 부산물들 HCl, N2를 퍼지시킨다.Then, the reactants caused by the reaction of the above formulas 1 and 2, ie by-products HCl, N 2 are purged.

여기서, 상기 TiN 박막 형성공정은 암모니아가스를 흘려주기 위하여 상기 Ti박막 형성공정시 사용된 가스관을 공유할 수도 있고, 별도의 가스관을 사용할 수도 있다.Here, the TiN thin film forming process may share a gas pipe used in the Ti thin film forming process in order to flow ammonia gas, or may use a separate gas pipe.

상기 별도의 가스관을 사용하는 경우는, Ti 박막을 증착시 사용했던 H2가스를 계속 흘려주고 동시에 암모니아 가스 유량을 조절하여 반응가스의 조절을 더 용이하게 할 수도 있다. 이 때의 반응원리는 하기 제3식과 같다.In the case of using the separate gas pipe, the reaction gas may be more easily controlled by continuously flowing the H 2 gas used for depositing the Ti thin film and simultaneously adjusting the ammonia gas flow rate. The reaction principle at this time is as shown in the following third equation.

2TiCl4(g) + 2NH3(g) + H2(g) = 2TiN(s) + 8HCl(g) - 제3식2TiCl 4 (g) + 2NH 3 (g) + H 2 (g) = 2TiN (s) + 8HCl (g)-Formula 3

한편, 소오스와 반응가스들의 반응기 내 주입방법은, 기존의 ALE CVD방법에서와 같이 반도체기판이 놓여있는 방향과 평행하게 흘려준다. 이경우, 빠른 시간내에 기판 상부에 가스들의 흡착을 가능하게 하는 장점이 있지만 기판의 한쪽 방향에서만 가스들이 흘러 나오기 때문에 박막 두께가 균일하게 증착되지 않는 문제가 있으나, 박막 증착 중에 반도체기판을 10 ∼ 500 rpm 정도의 속도로 회전시켜 기판의 모든 방향에서 같은 시간 동안 같은 양의 소오스와 반응가스를 기판 위에 흡착 되게 한다.On the other hand, the injection method of the source and the reaction gases in the reactor, as in the conventional ALE CVD method flows in parallel to the direction in which the semiconductor substrate is placed. In this case, although there is an advantage of allowing adsorption of gases on the substrate in a short time, there is a problem that the thickness of the thin film is not uniformly deposited because the gases flow only in one direction of the substrate, but the semiconductor substrate is 10 to 500 rpm during thin film deposition. It rotates at a speed that allows the same amount of source and reactant gas to be adsorbed onto the substrate for the same amount of time in all directions of the substrate.

이상에서 설명한 바와같이 본 발명에 따른 반도체 소자의 금속배선 형성방법은, 안정된 막질을 갖는 Ti/TiN 적층구조를 용이하게 형성하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the metal wiring forming method of the semiconductor device according to the present invention has an effect of easily forming a Ti / TiN laminated structure having a stable film quality to improve the characteristics and reliability of the semiconductor device.

Claims (7)

반도체소자의 금속배선 형성공정시 금속배선 하부에 형성되는 Ti/TiN적층구조의 확산방지막을 ALE CVD 방법으로 형성하는 반도체소자의 금속배선 형성방법으로서, TiCl4가스를 소오스가스로 고정하여 사용하고, 반응기체인 H2와 암모니아 가스를 각각 순차적으로 플로우시키며 하나의 반응로에서 인-시튜 공정으로 Ti/TiN적 층구조를 형성하고, 상기 Ti/TiN 적층구조 형성공정시 유발되는 부산물을 아르곤 가스로 퍼지하는 공정을 포함하는 반도체소자의 금속배선 형성방법.As a method of forming a metal wiring of a semiconductor device in which a diffusion barrier of a Ti / TiN stacked structure formed under the metal wiring is formed by the ALE CVD method in the process of forming a metal wiring of a semiconductor device, TiCl 4 gas is fixed to a source gas, H 2 and ammonia gas, respectively, are sequentially flowed, forming a Ti / TiN layer structure in an in-situ process in one reactor, and purging the by-products generated during the Ti / TiN layer formation process with argon gas. A metal wiring forming method of a semiconductor device comprising the step of. 청구항 1에 있어서, 상기 Ti 박막 증착공정은 반응기 내의 압력을 0.1~5Torr 유지하고, 0.1~60초간 H2반응가스를 10~1000sccm 흘려주어 반도체기판 상부에 흡착된 TiCl4상부에 H2를 흡착시킨 다음, 반응기체와 부산물을 아르곤가스로 퍼지시키는 싸이클(cycle)을 5~200회 반복하여 10~500Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The Ti thin film deposition process according to claim 1, wherein the Ti thin film deposition process maintains the pressure in the reactor at 0.1 to 5 Torr, and flows the H 2 reaction gas for 10 to 1000 sccm for 0.1 to 60 seconds to adsorb H 2 onto the TiCl 4 adsorbed onto the semiconductor substrate. Next, a cycle for purging the reactor gas and by-products with argon gas (cycle) is repeated 5 to 200 times to form a metal wiring of the semiconductor device, characterized in that to form a thickness of 10 ~ 500Å. 청구항 1에 있어서, 상기 TiN 박막 증착공정은, 상기 Ti 박막 표면에 TiCl4를 흡착하고, 그 상부에 암모니아가스를 흡착시켜 TiN 박막을 형성하는 싸이클을 5 ∼ 2000회 반복하여 10~600Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성 방법.The TiN thin film deposition process according to claim 1, wherein the TiN thin film deposition process is performed by adsorbing TiCl 4 on the surface of the Ti thin film, adsorbing ammonia gas on the top thereof, and repeating the cycle 5 to 2000 times to form a thickness of 10 to 600 μs. A metal wiring forming method of a semiconductor device, characterized in that. 청구항 1, 청구항 2 및 청구항 3 중 어느 한 항에 있어서, 상기 TiCl4가스는 상기 Ti박막과 TiN박막의 전구체로서 상기 Ti박막과 상기 TiN 박막 형성전에 0.1 ∼ 60 초간 10 ∼ 1000 sccm의 유량을 홀려주는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The TiCl 4 gas is a precursor of the Ti thin film and the TiN thin film, and has a flow rate of 10 to 1000 sccm for 0.1 to 60 seconds before forming the Ti thin film and the TiN thin film. Metal wiring forming method of a semiconductor device, characterized in that the giving. 청구항 1에 있어서, 상기 아르곤가스을 이용한 퍼지공정은, 10~1000sccm 유량을 0.1 ∼ 120초간 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the purge step using argon gas is performed at a flow rate of 10 to 1000 sccm for 0.1 to 120 seconds. 청구항 1에 있어서, 상기 ALE CVD 는 반도체기판의 온도를 200~700℃하고, 반응기 내의 압력을 0.5~2Torr하여 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the ALE CVD is performed by using a temperature of a semiconductor substrate at 200 ° C. to 700 ° C. and a pressure in the reactor at 0.5˜2 Torr. 청구항 1 또는 청구항 6 에 있어서, 상기 ALE CVD는 10 ∼ 500 rpm으로 반도체기판을 회전시키며 실시하는것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1 or 6, wherein the ALE CVD is performed by rotating the semiconductor substrate at 10 to 500 rpm.
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KR100474972B1 (en) * 2002-06-07 2005-03-10 주식회사 아이피에스 Method for depositing thin film on wafer using aluminum compound
KR100519376B1 (en) * 2001-06-12 2005-10-07 주식회사 하이닉스반도체 Method for Forming Barrier Layer of Semiconductor Device

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JP3292171B2 (en) * 1999-03-29 2002-06-17 日本電気株式会社 Method for manufacturing semiconductor device
KR100728942B1 (en) * 2001-05-31 2007-06-15 주식회사 하이닉스반도체 method of forming ohmic contact layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100519376B1 (en) * 2001-06-12 2005-10-07 주식회사 하이닉스반도체 Method for Forming Barrier Layer of Semiconductor Device
KR100474972B1 (en) * 2002-06-07 2005-03-10 주식회사 아이피에스 Method for depositing thin film on wafer using aluminum compound

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