CN102593097A - Integrated circuit metal interconnecting structure and manufacture method thereof - Google Patents
Integrated circuit metal interconnecting structure and manufacture method thereof Download PDFInfo
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- CN102593097A CN102593097A CN2012100467202A CN201210046720A CN102593097A CN 102593097 A CN102593097 A CN 102593097A CN 2012100467202 A CN2012100467202 A CN 2012100467202A CN 201210046720 A CN201210046720 A CN 201210046720A CN 102593097 A CN102593097 A CN 102593097A
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Abstract
The invention discloses an integrated circuit metal interconnecting structure and a manufacture method of the integrated circuit metal interconnecting structure. According to the invention, carbon atoms of graphene are elementary substance carbon formed by being orderly arranged according to a hexagonal lattice, and the graphene is used as a diffusion impervious layer in copper interconnection of an integrated circuit, wherein all sp2 hybridized carbon atoms of the graphene have saturated bonds and very stable structure, thus the graphene diffusion impervious layer has excellent heat stability and chemical stability, and can effectively prevent copper atoms from diffusing in silicon and insulation mediums.
Description
Technical field
The present invention relates to nanofabrication technique, specifically is a kind of integrated circuit metal interconnect structure and preparation method thereof.
Background technology
Along with developing rapidly of integrated circuit; Device size constantly dwindles, and device density constantly increases, and the interconnect length and the number of plies that reach between the device between the circuit are more and more; Current 0.18 μ m high-performance ULSI (for example CPU) has had nearly 7 layers copper interconnecting line, and interconnect length reaches 4km approximately.(resistivity of Al is 2.62 μ Ω cm because Cu has the resistivity lower than Al; And Cu is 1.69 μ Ω cm) and higher electromigration resisting property (can increase about two one magnitude), be a kind of preferred material of deep-submicron and nanometer IC multilayer interconnection line so Cu generally believes.But Cu is to Si and SiO
2Adhesiveness relatively poor and diffusion coefficient is very big; In case can become the deep energy level acceptor impurity in the entering silicon chip; Make chip performance degenerate even lose efficacy; Therefore must between the two, increase one deck barrier layer, it rises and stops that the Cu thermal diffusion advances the chip active area and improve Cu and the adhering double action of dielectric material, and this is particularly important in multiple layer of copper interconnects.The material of the diffusion impervious layer of research comprises TiW at present, TiN, and Ta, TaN, Ta-Si-N etc., wherein Ta and TaN are considered to more satisfactory barrier material.But these barrier layers have the resistivity more much higher than copper, and its effect has been equivalent to from interconnecting lead, " tie up " space of part copper lead, have reduced because the effective cross section of copper is long-pending, have therefore increased conductor resistance.Therefore the selection on barrier layer will be taken all factors into consideration many-sided factor, and the barrier layer need be also thin as much as possible outside keeping enough blocking effect.The leading indicator of weighing barrier performance comprises adhesiveness, deelectric transferred ability, diffusion coefficient, sheet resistance, invalid temperature and electrology characteristic etc.Therefore it is better with block and diffusion barrier structure thinner thickness is significant in the Cu interconnection technique to prepare a kind of adhesion.
The material of the diffusion impervious layer of research comprises TiW at present, TiN, and Ta, TaN, Ta-Si-N etc., wherein Ta and TaN are considered to more satisfactory barrier material.Have higher reliability in order to ensure interconnection line, according to the difference of used deposition process, the thickness on required barrier layer is between 1 to 5 nanometer.Supposing that conductor width is 60 nanometers, highly is 120 nanometers, wherein contains the equally distributed 5 nanometer barrier materials of thickness, and the effective resistance of this lead is estimated than pure copper wire high approximately 20% so.
Summary of the invention
The objective of the invention is to propose a kind of Graphene that utilizes and prepare integrated circuit metal interconnect structure and preparation method thereof.
Basic principle of the present invention:
Because Graphene is that carbon atom is the carbon simple substance of neatly arranging and forming by hexagonal lattice, wherein all sp
2The carbon atom of hydridization all is saturated to key; Structure is highly stable; Thereby make Graphene have good thermal stability and chemical stability, therefore Graphene is used as the diffusion impervious layer in the integrated circuit copper interconnecting, can effectively stop copper atom in silicon and dielectric, to spread.
Technical scheme provided by the invention is following:
A kind of integrated circuit metal interconnect structure; It is characterized in that; Comprise upper and lower layer metal connecting line and connect the through hole of upper/lower layer metallic line and the groove of upper strata metal connecting line, in bottom and the side wall deposition diffusion impervious layer and the metal seed layer of said through hole, and the bottom and the sidewall of said upper strata metal connecting line groove also deposit diffusion impervious layer and metal seed layer; Above-mentioned diffusion impervious layer is individual layer, bilayer or multi-layer graphene.
A kind of preparation method of metal interconnected line structure, concrete steps comprise:
(1) metallization medium layer on the structure that has prepared the lower metal line.
The lower metal line can be a tungsten, also can be the alloy wire that coats tectal copper cash or copper.Dielectric layer can be low-K dielectric materials such as silicon dioxide, doping silicon dioxide, organic polymer and porous material.Cover layer can be optionally to be coated on the surperficial cobalt tungsten phosphide (CoWP) of copper interconnecting line, cobalt tungsten boride (CoWB), Graphene etc., also can be the dielectric materials layer that covers above the total, like Si
3N
4Or SiC etc.
(2) in dielectric layer, etch the through hole of connection lower metal line and the groove of upper strata metal interconnecting wires.Connecting the through hole of lower metal line and the groove of upper strata metal interconnecting wires can be (the single mosaic technology) that forms in two steps, also can be (dual-damascene technics) that forms simultaneously.
(3) in bottom and the side wall deposition Graphene diffusion impervious layer and the metal seed layer of through hole and groove.On the bottom and the side wall deposition Graphene barrier layer of through hole and groove, the deposition process of Graphene can be the method for chemical vapour deposition (CVD), also can be other chemically grown method or physics assemble method earlier.Graphene can be an individual layer, and bilayer or multi-layer graphene also can be their amalgams.Then in Graphene barrier layer surface deposited copper seed layer.
(4) plated metal in through hole and groove, and with the method for chemico-mechanical polishing to upper strata metal connecting line and dielectric layer flattening surface.The method of plated metal can be methods such as physical vapour deposition (PVD) or chemical vapour deposition (CVD), plating, chemical plating.
(5) cover layers such as metal connecting line surface selectivity ground deposit cobalt tungsten phosphide (CoWP), cobalt tungsten boride (CoWB), Graphene on the upper strata, perhaps deposition one deck Si on the structure that whole polishing is accomplished
3N
4Or SiC dielectric materials layer.
(6) preparation multilayer interconnect structure: repeat above-mentioned (1～5) process, then can prepare the multiple layer of copper interconnection structure of making diffusion impervious layer of Graphene.
Advantage of the present invention is following:
Thermal stability that Graphene is good and chemical stability have guaranteed the validity of Graphene as diffusion impervious layer; The thickness of single-layer graphene has only 0.34nm, and every increase one deck, thickness only are to have increased 0.34nm, can well satisfy the requirement that the diffusion barrier layer thickness will approach as far as possible; The high conductivity of Graphene has satisfied the requirement of low sheet resistance; The maximum current density that Graphene can bear is 10
9A/cm
2Magnitude has effectively guaranteed the reliability of Graphene as diffusion impervious layer.
Description of drawings
Fig. 1-Fig. 5 is the sketch map in preparation copper interconnecting line structure;
Wherein, 1-lower floor copper interconnecting line; 2-silicon nitride cover layer; 3-silica dioxide medium layer; 4-Graphene diffusion impervious layer; 5-upper copper interconnection line.
Embodiment
Following reference accompanying drawing of the present invention, detailed description goes out most preferred embodiment of the present invention.
The preparation method of integrated circuit metal interconnect structure of the present invention comprises the steps:
(1) at the method grown silicon nitride dielectric materials layer 2 of the body structure surface that has prepared lower floor's copper interconnecting line 1, as shown in Figure 1 with PECVD;
(2) use the method deposit thickness of PECVD to be the silica dioxide medium layer 3 of 1 μ m on the surface of silicon nitride dielectric materials layer 2, as shown in Figure 2.
(3) in silica dioxide medium layer 3 and silicon nitride dielectric materials layer 2, etch the through hole that is connected lower floor's copper interconnecting line 1 and the groove (dual-damascene technics) of upper copper interconnection line 5 with the method for reactive ion etching (RIE), as shown in Figure 3.
(4) with the method for chemical vapour deposition (CVD) bottom and the side wall deposition Graphene diffusion impervious layer 4 at through hole and groove, the structure behind the Graphene diffusion impervious layer of having grown is as shown in Figure 4.Wherein the growth technique process of Graphene is following:
(i) temperature-rise period: at H
2Under Ar atmosphere, in 60 minutes, furnace temperature is risen to 950 ℃ of growth temperatures.H
2Flow control exists: 15sccm, the flow control of Ar exists: 450sccm
(ii) thermostatic process: after furnace temperature rises to growth temperature, continue at H
2With kept ten minutes under the atmosphere of Ar.
(iii) growth course: after the thermostatic process, will contain methane and introduce in the stove, flow control is at 15sccm, and it is constant that temperature continues to keep, and growth time is 60 minutes.
(iv) temperature-fall period: after growth course is accomplished, keep H
2, Ar and CH
4The condition of flow unchanged under begin cooling, cooling rate is 20 ℃/min.
(5) in the method deposition layer of copper seed layer of Graphene diffusion barrier laminar surface with ald; The method of electricity consumption chemical plating then (ECP) deposited copper metal in through hole and groove; And make copper coating 5 and dielectric layer 3 flattening surfaces with the method for chemico-mechanical polishing; Thereby form the through hole and the upper copper interconnection line 5 that connect lower floor's copper interconnecting line 1, as shown in Figure 5.
Above-described embodiment is used to limit the present invention, and any those skilled in the art is not breaking away from the spirit and scope of the present invention, can make various conversion and modification, so protection scope of the present invention is looked the claim scope and defined.
Claims (5)
1. integrated circuit metal interconnect structure; It is characterized in that; Comprise upper and lower layer metal connecting line and connect the through hole of upper/lower layer metallic line and the groove of upper strata metal connecting line; In the bottom of said through hole and bottom and the side wall deposition diffusion impervious layer and the metal seed layer of sidewall and said upper strata metal connecting line groove, wherein said diffusion impervious layer is individual layer, bilayer or multi-layer graphene.
2. the preparation method of a metal interconnected line structure, concrete steps comprise:
1) preparation lower metal connecting line construction, and at lower metal connecting line construction surface deposition dielectric layer;
2) in dielectric layer, etch the through hole of connection lower metal line and the groove of upper strata metal connecting line;
3) at the bottom and the sidewall of through hole, and the bottom of the groove of upper strata metal connecting line and side wall deposition Graphene be as diffusion impervious layer, and in Graphene barrier layer surface plated metal seed layer;
4) plated metal forms through hole and upper strata metal connecting line in the groove of through hole and upper strata metal connecting line, and with the method for chemico-mechanical polishing to upper strata metal connecting line and dielectric layer flattening surface.
3. method as claimed in claim 2 is characterized in that, the deposition process of Graphene adopts the method for chemical vapour deposition (CVD), or other chemically grown method or physics assemble method.
4. method as claimed in claim 2 is characterized in that, the upper strata metal connecting line is the alloy of copper or copper, and the lower metal line is a tungsten, or coats the alloy of tectal copper or copper.
5. method as claimed in claim 2 is characterized in that dielectric layer is low-K dielectric materials such as silicon dioxide, doping silicon dioxide, organic polymer and porous material.
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| CN103515353A (en) * | 2013-10-18 | 2014-01-15 | 上海华力微电子有限公司 | Photoresist fill type metal interconnect structure and manufacturing method thereof |
| CN103943562A (en) * | 2014-05-09 | 2014-07-23 | 浙江大学 | Interconnection line with graphene and preparation method of interconnection line |
| CN103956354A (en) * | 2014-05-09 | 2014-07-30 | 浙江大学 | Interconnecting wire with graphene serving as metallization layer and diffusion barrier layer and manufacturing method of interconnecting wire |
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| CN112514031A (en) * | 2018-08-11 | 2021-03-16 | 应用材料公司 | Graphene diffusion barrier |
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Application publication date: 20120718 |