JPWO2019102296A1 - 撮像装置、および電子機器 - Google Patents
撮像装置、および電子機器 Download PDFInfo
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- JPWO2019102296A1 JPWO2019102296A1 JP2019555089A JP2019555089A JPWO2019102296A1 JP WO2019102296 A1 JPWO2019102296 A1 JP WO2019102296A1 JP 2019555089 A JP2019555089 A JP 2019555089A JP 2019555089 A JP2019555089 A JP 2019555089A JP WO2019102296 A1 JPWO2019102296 A1 JP WO2019102296A1
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Abstract
Description
本実施の形態では、本発明の一形態に係わる撮像装置の構成例について説明する。本発明の一形態に係わる撮像装置は、半導体基板に形成されたトランジスタを有する層と、OSトランジスタを有する層とが積層され、さらに、半導体基板に形成されたトランジスタおよびフォトダイオードを有する層が貼り合わされて積層された構造を有する。
図1(A)は、本発明の一形態に係わる撮像装置10の構成例を示す斜視図である。
信号処理回路110は、記憶装置210およびイメージセンサ310の動作を制御する機能、イメージセンサ310が生成した画像データを処理する機能、撮像装置10を搭載した電子機器との間でデータおよび制御信号等を送受信する機能、等を有する。
記憶装置210は、層100と層200を接続する配線CLを介して、制御回路111と接続されている。配線CLは、層100と層200間のコンタクトホールに形成された導電体によって形成される。そして、記憶装置210と制御回路111間のデータおよび信号の入出力は、配線CLを介して行われる。
イメージセンサ310は、半導体基板SUB2に形成されたトランジスタを用いて構成されている。半導体基板SUB2は、トランジスタのチャネル領域を形成することが可能であれば、特に限定されない。半導体基板SUB2の説明は、半導体基板SUB1と同様のため、省略する。また、本実施の形態では、一例として、半導体基板SUB2に単結晶シリコン基板を用いた場合について説明する。
図2(D)は、画素312の構成例を示す回路図である。図2(D)に示す画素312は、光電変換素子313、トランジスタ314、トランジスタ315、トランジスタ316、トランジスタ317、および容量素子318を有する。
上記のように、撮像装置10は、層100上に層200が、層200上に層300が積層された構造を有し、信号処理回路110、記憶装置210、およびイメージセンサ310を有する。撮像装置10は、イメージセンサ310が生成した画像データに、アナログデジタル変換、ノイズ除去、その他各種画像処理を行ってから、撮像装置10を搭載した電子機器にデータを出力することができる。そのため、撮像装置10を搭載した電子機器を小型化、軽量化することができる。
本実施の形態では、上記実施の形態で説明した撮像装置10の断面構成例について説明する。
図4に示す層100および層200の断面構成例は、トランジスタ400a、トランジスタ400b、トランジスタ500、および容量素子600を含んでいる。図5(A)はトランジスタ500のチャネル長方向の断面図であり、図5(B)はトランジスタ500のチャネル幅方向の断面図であり、図5(C)はトランジスタ400aのチャネル幅方向の断面図である。
図6に、層300の断面構成例を示す。図6に示す層300の断面構成例は、トランジスタ700a、および、pn接合型のフォトダイオード700cを含んでいる。なお、フォトダイオード700cは、実施の形態1における光電変換素子313として機能する。
撮像装置10は、上述した、層100および層200と、層300を貼り合わせて構成される。図7に、撮像装置10の断面構成例を示す。
図4及び図5では、ソース電極またはドレイン電極として機能する導電体542が、酸化物530に接して形成されている構成例について説明したが、OSトランジスタの構成はこれに限られない。例えば、導電体542を設けず、酸化物530を選択的に低抵抗化することで、酸化物530bにソース領域またはドレイン領域が設けられた構成を用いることもできる。このようなトランジスタの構成例を、図8に示す。
図4及び図5では、ゲートとして機能する導電体560が、絶縁体580の開口の内部に形成されている構成例について説明したが、OSトランジスタの構成はこれに限られない。例えば、当該導電体の上方に、当該絶縁体が設けられた構成を用いることもできる。このようなトランジスタの構成例を、図9及び図10に示す。
次に、OSトランジスタの電気特性について説明する。以下では一例として、第1のゲート及び第2のゲートを有するトランジスタについて説明する。第1のゲート及び第2のゲートを有するトランジスタは、第1のゲートと第2のゲートに異なる電位を印加することで、閾値電圧を制御することができる。例えば、第2のゲートに負の電位を印加することにより、トランジスタの閾値電圧を0Vより大きくし、オフ電流を低減することができる。つまり、第2のゲートに負の電位を印加することにより、第1の電極に印加する電位が0Vのときのドレイン電流を小さくすることができる。
図11(A)および図11(C)は、電気特性の評価に用いたトランジスタの断面図である。なお、図11(A)および図11(C)では、図の明瞭化のために一部の要素を省いて図示している。
図11(A)に示すトランジスタ、および図11(C)に示すトランジスタにおいて、Id−Vg特性を計算し、トランジスタの電気特性を評価した。
本実施の形態では、上記の実施の形態で説明したOSトランジスタに用いることができる金属酸化物の構成について説明する。
本明細書等において、CAAC(c−axis aligned crystal)、及びCAC(Cloud−Aligned Composite)と記載する場合がある。なお、CAACは結晶構造の一例を表し、CACは機能、または材料の構成の一例を表す。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本実施の形態では、上記実施の形態で説明した撮像装置10を搭載した電子機器の一例について説明する。
Claims (5)
- 第1の層と、
前記第1の層の上方の第2の層と、
前記第2の層の上方の第3の層と、を有し、
前記第1の層は、信号処理回路を有し、
前記第2の層は、記憶装置を有し、
前記第3の層は、イメージセンサを有し、
前記信号処理回路は、第1の半導体基板に形成されたトランジスタを有し、
前記記憶装置は、チャネル形成領域に金属酸化物を含むトランジスタを有し、
前記イメージセンサは、第2の半導体基板に形成されたトランジスタを有する、撮像装置。 - 第1の層と、
前記第1の層の上方の第2の層と、
前記第2の層の上方の第3の層と、を有し、
前記第1の層は、信号処理回路を有し、
前記第2の層は、記憶装置を有し、
前記第3の層は、イメージセンサを有し、
前記記憶装置は、複数のメモリセルを有し、
前記メモリセルは、トランジスタと、容量素子と、を有し、
前記トランジスタのソースまたはドレインの一方は、前記容量素子の一方の電極と電気的に接続され、
前記トランジスタは、チャネル形成領域に金属酸化物を有し、
前記信号処理回路は、第1の半導体基板に形成されたトランジスタを有し、
前記イメージセンサは、第2の半導体基板に形成されたトランジスタを有する、撮像装置。 - 請求項1または請求項2において、
前記信号処理回路は、前記記憶装置および前記イメージセンサの、動作を制御する機能を有する、撮像装置。 - 請求項1乃至請求項3のいずれか一項において、
前記信号処理回路または前記イメージセンサの少なくとも一方は、アナログデジタル変換回路を有し、
前記アナログデジタル変換回路は、前記イメージセンサが生成した画像データを、デジタル信号に変換する機能を有する、撮像装置。 - 請求項4において、
前記記憶装置は、前記デジタル信号を保持する機能を有する、撮像装置。
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JP2015076502A (ja) * | 2013-10-09 | 2015-04-20 | ソニー株式会社 | 半導体装置およびその製造方法、並びに電子機器 |
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JP2016054478A (ja) * | 2014-07-31 | 2016-04-14 | 株式会社半導体エネルギー研究所 | 撮像装置、監視装置、及び電子機器 |
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