JPWO2018066483A1 - Semiconductor device - Google Patents

Abstract

an n-type Si portion, a first layer disposed on the n-type Si portion, a second layer disposed on the first layer, and a second layer disposed on the second layer The first layer is made of an oxide electride containing calcium atoms and aluminum atoms, and the second layer is made of the following group: (i) zinc (Zn) A metal oxide containing oxygen and oxygen (O) and further containing at least one of silicon (Si) and tin (Sn), (ii) a metal oxide containing titanium (Ti) and oxygen (O), iii) A semiconductor element selected from metal oxides containing tin (Sn) and oxygen (O), and (iv) metal oxides containing zinc (Zn) and oxygen (O).

Description

  The present invention relates to semiconductor devices, for example, semiconductor devices such as solar cells and thin film transistors.

  For example, semiconductor elements such as solar cells and thin film transistors (TFTs) have a configuration in which an electrode layer is disposed on a member made of crystalline or amorphous n-type silicon (see, for example, Patent Document 1).

WO 2015/098225

  In the field of semiconductor devices as described above, there is a demand to further increase the device efficiency. For example, solar cells are required to further improve power generation efficiency, while thin film transistors (TFTs) are required to further improve operation efficiency.

  However, in an ordinary semiconductor device, the interface between the n-type silicon member and the electrode layer does not exhibit ohmic resistance behavior, and as a result, there is a problem that the contact resistance of the interface is high. This is one factor that hinders the improvement of the efficiency of the semiconductor device.

  The present invention has been made in view of such background, and an object of the present invention is to provide a semiconductor device in which the contact resistance between an n-type silicon member and an electrode layer is significantly suppressed.

In the present invention,
n-type Si part,
A first layer disposed on the n-type Si portion,
A second layer disposed on the first layer;
An electrode layer disposed on the second layer;
Have
The first layer is made of electride of oxide containing calcium atom and aluminum atom,
Said second layer comprises the following groups:
(I) A metal oxide containing zinc (Zn) and oxygen (O), and further containing at least one of silicon (Si) and tin (Sn),
(Ii) metal oxides containing titanium (Ti) and oxygen (O),
(Iii) metal oxides containing tin (Sn) and oxygen (O), and (iv) metal oxides containing zinc (Zn) and oxygen (O),
A semiconductor device is provided, which is selected from

  The present invention can provide a semiconductor device in which the contact resistance between the n-type silicon member and the electrode layer is significantly suppressed.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic flow diagram of an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of still another semiconductor device according to an embodiment of the present invention. FIG. 1 is a cross-sectional view schematically showing a configuration example of a solar cell module including a semiconductor device according to an embodiment of the present invention. FIG. 1 is a cross-sectional view schematically showing a configuration example of a TFT provided with a semiconductor device according to an embodiment of the present invention. It is the graph which put together and showed the relationship between the distance between electrodes and resistance value obtained in each sample.

  Hereinafter, the present invention will be described.

In one embodiment of the invention:
n-type Si part,
A first layer disposed on the n-type Si portion,
A second layer disposed on the first layer;
An electrode layer disposed on the second layer;
Have
The first layer is made of electride of oxide containing calcium atom and aluminum atom,
Said second layer comprises the following groups:
(I) A metal oxide containing zinc (Zn) and oxygen (O), and further containing at least one of silicon (Si) and tin (Sn),
(Ii) metal oxides containing titanium (Ti) and oxygen (O),
(Iii) metal oxides containing tin (Sn) and oxygen (O), and (iv) metal oxides containing zinc (Zn) and oxygen (O),
A semiconductor device is provided, which is selected from

  In the present application, the interface between the n-type Si portion and the layer disposed immediately above the n-type Si portion is referred to as “first interface”. In addition, the interface between the electrode layer and the layer disposed immediately below the electrode layer is referred to as “second interface”.

  As described above, in a typical semiconductor device, there is a problem that the contact resistance at the first interface between the n-type silicon member and the electrode layer is high. In order to reduce the contact resistance at the junction of metal and Si, select an appropriate metal material to increase the carrier concentration in Si near the interface or to reduce the Schottky barrier height at the interface between metal and Si. Methods such as to do are known. In the former case, there is a limit to the reduction of contact resistance, both due to physical phenomena such as dopant solubility limit in semiconductor and the latter case Fermi level pinning at the interface between metal and Si.

  However, in the semiconductor device according to the embodiment of the present invention, a plurality of layers are added between the n-type silicon member and the electrode layer.

  According to the findings of the inventors of the present invention, the first layer having the above-mentioned features contained in the present semiconductor device has good electron conductivity. In addition, it has been confirmed that the contact resistance of the interface between the first layer and the n-type Si portion (that is, the “first interface”) is relatively low.

  By arranging the first layer on the n-type Si portion, Fermi level pinning does not occur at the first interface, and the first layer has a high carrier density and a low work function. The barrier height at the interface 1 is small. Therefore, the contact resistance at the first interface can be significantly suppressed while securing the operability as the semiconductor element.

  Here, Fermi level pinning means that, when bonding a semiconductor and a metal, a change in Schottky barrier height is small even if metals of various work functions are used. For example, in the case of bonding Si and Al, the Schottky barrier height is about 1.5 eV, which is higher than the Schottky barrier height expected from the work function of Al (4.2 eV) and the electron affinity of Si (4 eV) Too big. Although Fermi level pinning originates in the interface state or interface state which exists in the band gap of a semiconductor, it is thought that the chemical stability of the interface is greatly concerned in practical use.

  According to the findings of the inventors of the present invention, it is confirmed that the first layer as described above has a relatively high contact resistance with metal. Therefore, when an electrode layer made of metal is disposed immediately above the first layer, the influence of the contact resistance at the second interface becomes remarkable.

  However, as described above, in the present semiconductor device, the first layer and the electrode layer are not in direct contact with each other. That is, the second layer is disposed between the first layer and the electrode layer.

  Here, the second layer has good electron conductivity. Also, it has been confirmed that the contact resistance of the interface between the second layer and the electrode (that is, the "second interface") is relatively low. The contact resistance is also confirmed to be relatively low at the interface between the first layer and the second layer (hereinafter, referred to as "third interface").

  In the present semiconductor device, the Schottky barrier height is significantly suppressed also at the second interface and the third interface for the same reason as the first interface, so the operability as the semiconductor device is secured. As it is, the contact resistance of the second interface (and the third interface) can be significantly suppressed.

  As a result, in the present semiconductor device, the device efficiency can be significantly improved. For example, when the present semiconductor device is applied to a solar cell, power generation efficiency can be significantly improved. In addition, when the present semiconductor device is applied to a TFT, the operation efficiency can be significantly enhanced.

(Semiconductor Device According to One Embodiment of the Present Invention)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a schematic cross section of a semiconductor device according to an embodiment of the present invention (hereinafter, referred to as “first semiconductor device”).

  As shown in FIG. 1, the first semiconductor element 100 includes a support 110, an n-type Si layer 120, a first layer 130, a second layer 140, and an electrode layer 150.

  The support 110 plays a role of supporting each layer disposed thereon and facilitating the formation of the n-type Si layer 120.

  For example, when the first semiconductor element 100 constitutes a part of a solar cell, the support 110 may have a p-type Si layer. Alternatively, the support 110 may be a p-type Si layer. In addition, when the first semiconductor element 100 constitutes a part of a thin film transistor (TFT), the support 110 may have an amorphous Si layer. Alternatively, the support 110 may be an amorphous Si layer.

  However, in a specific case such as when the n-type Si layer 120 is formed thick, the support 110 may be omitted.

  The n-type Si layer 120 is composed of a layer containing n-type silicon Si. The n-type Si layer 120 may be amorphous or crystalline.

  The first layer 130 is made of electride of an oxide containing a calcium atom and an aluminum atom.

  The second layer 140 contains zinc (Zn) and oxygen (O), and is further composed of a metal oxide containing at least one of silicon (Si) and tin (Sn).

  The details of the first layer 130 and the second layer 140 will be described later.

  The electrode layer 150 is made of metal (or alloy, hereinafter the same).

  In the first semiconductor device 100 having such a configuration, the first to third interfaces, that is, the interface between the n-type Si layer 120 and the first layer 130 (first interface), the second layer Contact resistance is significantly suppressed at each of the interface (second interface) between 140 and electrode layer 150 and the interface (third interface) between first layer 130 and second layer 140 Be done.

  For this reason, in the first semiconductor element 100, the efficiency at the time of operation can be significantly improved.

(About each component)
Next, each member constituting the first semiconductor element 100 shown in FIG. 1 will be described in more detail.

  Here, for the sake of clarity, the reference numerals shown in FIG. 1 are used when representing each member.

(Support 110)
As described above, the support 110 plays a role of supporting each layer disposed thereon and facilitating the formation of the n-type Si layer 120.

  The material of the support 110 is not particularly limited.

  For example, when the first semiconductor device 100 is applied to part of a solar cell, the support 110 may be made of p-type Si or non-doped Si. On the other hand, when the first semiconductor element 100 is applied to part of a TFT, the support 110 may have amorphous Si or crystalline Si, or may be composed of amorphous Si or crystalline Si.

  In addition, the support 110 may be a substrate made of glass, alumina, silicon or the like.

  As described above, the support 110 is not an essential component, and may be omitted.

(N-type Si layer 120)
An n-type Si layer 120 is disposed on the support 110.

  The n-type Si layer 120 may be crystalline or amorphous.

  The n-type Si layer 120 may be doped with phosphorus (P) and / or arsenic (As) or the like.

The electron density of the n-type Si layer 120 may be, for example, in the range of 10 ¹⁴ cm ⁻³ to 10 ²¹ cm ⁻³ . The electron density is preferably 10 ¹⁶ cm ³ or more, and more preferably 10 ¹⁸ cm ³ or more. If the electron density is 10 ¹⁴ cm ⁻³ or more, the contact resistance tends to be low. 10 ²⁰ cm ⁻³ or less is preferable, and 10 ¹⁹ cm ⁻³ or less is more preferable.

(First layer 130)
The first layer 130 is made of electride of an oxide containing a calcium atom and an aluminum atom as described above.

  The first layer 130 is conductive, has a significantly high ionization potential, and has a low work function. For example, the work function of the first layer 130 is in the range of 2.4 eV to 4.5 eV (e.g., 2.8 eV to 3.2 eV).

In addition, the first layer 130 has a feature of high electron density. The electron density of the first layer 130 is, for example, in the range of 2.0 × 10 ¹⁷ cm ^{−3 to} 2.3 × 10 ²¹ cm ⁻³ . The electron density is preferably 1.0 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or more, and particularly preferably 1 × 10 ²⁰ cm ⁻³ or more.

  Since the electron density of the first layer 130 is high, the interface (first interface) between the n-type Si layer 120 and the first layer 130 exhibits ohmic properties due to the tunnel effect. Therefore, the contact resistance of the first interface is significantly suppressed. The first layer 130 also exhibits good contact resistance with the second layer 140 (third interface).

  Therefore, in the first semiconductor element 100 having the first layer 130, the contact resistance can be significantly suppressed at any of the first interface and the third interface.

  The thickness of the first layer 130 is preferably in the range of 0.5 nm to 10 nm. If the thickness is 0.5 nm or more, a uniform thin film can be formed, so that the effect of reducing the contact resistance can be stably obtained. The thickness of the first layer 130 is more preferably 2 nm or more, and still more preferably 3 nm or more. On the other hand, if the thickness of the first layer 130 is 10 nm or less, the influence of volume resistance can be ignored. The thickness of the first layer 130 is more preferably 7 nm or less, and further preferably 5 nm or less.

  The thickness of the first layer 130 can be measured by X-ray reflectometry (XRR) or cross-sectional transmission electron microscopy.

  The first layer 130 may be amorphous or crystalline. Each case will be described below.

(Amorphous first layer 130)
The first layer 130 may be composed of electride of an amorphous oxide containing calcium atoms and aluminum atoms.

Amorphous means a substance that does not give sharp peaks in X-ray diffraction measurement. Specifically, when the X-ray wavelength λ is 0.154 nm and the Scherrer constant K is 0.9, the crystallite diameter (Sheller diameter) determined by the Scheller equation expressed by the following equation (1) is 5 .2 nm or less. The Scheller diameter L is K, the X-ray wavelength is λ, the half width is β, and the peak position is θ, where

L = Kλ / (β cos θ) (1)

Is represented by It is preferable that the first layer 130 be amorphous because the smoothness of the film surface is high and the short circuit of the element can be prevented.

  Also, “electride of amorphous oxide containing calcium atom and aluminum atom” means solvation in which an amorphous composed of a calcium atom, an aluminum atom and an oxygen atom is used as a solvent and an electron is used as a solute. By amorphous solid material is meant.

  Electrons in electride can act as anions. The electrons may exist as bipolarons. A bipolaron is composed of calcium atoms, aluminum atoms, and oxygen atoms, and is adjacent to two cages which are three-dimensionally connected voids having an inner diameter of about 0.4 nm, and electrons (solutes) in each cage. Is included. However, the state of electride of the amorphous oxide is not limited to the above, and two electrons (solutes) may be included in one cage. In addition, a plurality of these cages may be in a state of aggregation, and since the aggregated cage can be regarded as a microcrystal, a state in which the microcrystals are included in the amorphous state is also regarded as an amorphous state.

  The molar ratio of aluminum atoms to calcium atoms (Ca / Al) in “amorphous oxide electride” is preferably in the range of 0.3 to 5.0, and more preferably in the range of 0.55 to 1.00. The range of 0.8 to 0.9 is more preferable, and the range of 0.84 to 0.86 is particularly preferable.

The composition of “amorphous oxide electride” is preferably 12CaO · 7Al ₂ O _3, but is not limited thereto. For example, the following compounds (1) to (5) are exemplified.
(1) Isomorphic compounds in which part or all of Ca atoms are substituted by metal atoms such as Sr, Mg and / or Ba. For example, as a compound in which part or all of the Ca atom is substituted with Sr, there is strontium aluminate Sr ₁₂ Al ₁₄ O ₃₃ , and calcium strontium aluminum as a mixed crystal in which the mixing ratio of Ca and Sr is arbitrarily changed. And the like, for example, in the form of a salt, Ca _12-x Sr _x Al ₁₄ O ₃₃ (x is an integer of 1 to 11; in the case of an average value, a number greater than 0 and less than 12).
(2) A homomorphic compound in which part or all of Al atoms are substituted with one or more atoms selected from the group consisting of Si, Ge, Ga, In, and B. For _example, like _{Ca 12 Al 10 Si 4 O 35} .
(3) A part of metal atoms and / or nonmetal atoms (but excluding oxygen atoms) in 12CaO · 7Al ₂ O ₃ (including the compounds of the above (1) and (2)) is Ti, V, One or more transition metal atoms or typical metal atoms selected from the group consisting of Cr, Mn, Fe, Co, Ni and Cu, and one or more alkali metal atoms selected from the group consisting of Li, Na and K, Or an isomorphic compound substituted with one or more rare earth atoms selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb.
(4) A compound in which part or all of the free oxygen ions contained in the cage are replaced by other anions. As other anions, for example, anions such as H ⁻ , H ₂ ⁻ , H ^{2 −} , O ₂ ⁻ , O ₂ ⁻ , O ₂ ⁻ , OH ⁻ , F ⁻ , Cl ⁻ , and S ²⁻ , and nitrogen (N) There are anions of
(5) A compound in which a part of oxygen in the cage skeleton is substituted with nitrogen (N) or the like.

  The bipolaron has little light absorption in the visible light range of photon energy of 1.55 eV to 3.10 eV, and shows light absorption at around 4.6 eV. Thus, the first layer 130 is transparent to visible light. Also, by measuring the light absorption characteristics of the first layer 130 and measuring the light absorption coefficient around 4.6 eV, whether or not a bipolaron is present in the first layer 130, ie, the first layer 130 It can be confirmed whether or not it has an amorphous oxide electride.

  Composition analysis of the first layer 130 can be performed by an XPS method, an EPMA method, an EDX method, or the like. When the film thickness is 100 nm or less, analysis is possible by the XPS method, when it is 50 nm or more, analysis by the EPMA method, and when it is 3 μm or more, analysis by the EDX method is possible.

  When the first layer 130 is composed of amorphous oxide electride, no peak is observed in the measurement of X-ray diffraction, and only the halo is observed.

The first layer 130 may contain microcrystals. Whether or not microcrystals are contained in the first layer 130 is determined from, for example, a cross-sectional TEM (transmission electron microscope) photograph of the first layer 130 or the like. The composition in the crystalline state is represented by 12CaO · 7Al ₂ O ₃ , CaO · Al ₂ O ₃ , 3CaO · Al ₂ O ₃ or the like. The microcrystal is a crystal having a Scherrer diameter of greater than 5.2 nm and less than 100 nm. If the first layer 130 is microcrystalline, the conductivity is improved.

In the first layer 130, the light absorption value at the position of 4.6eV may also be 100 cm ^-1 or more, may be 200 cm ^-1 or more. If the light absorption value at the position of 4.6 eV is 100 cm ⁻¹ or more, the electron density increases and the work function decreases, so the contact resistance can be sufficiently reduced.

  Note that the electron density of the first layer 130 can be measured by an iodine titration method. Incidentally, the density of the bipolaron in the thin film of electride can be calculated by halving the measured electron density.

In this iodine titration method, a sample of the first layer 130 is immersed in a 5 mol / l aqueous iodine solution, and after adding and dissolving hydrochloric acid, the amount of unreacted iodine contained in the solution is Is a method of titration detection. In this case, due to the dissolution of the sample, the iodine in the aqueous iodine solution is ionized by the following reaction:

I ₂ + e ⁻ → 2 I ⁻ (2)

In addition, when an aqueous iodine solution is titrated with sodium thiosulfate,

2Na ₂ S ₂ O ₃ + I ₂ → ₂ NaI + Na ₂ S ₄ O ₆ (3)

The reaction of (4) converts unreacted iodine to sodium iodide. The amount of iodine consumed in the reaction of the equation (2) is calculated by subtracting the amount of iodine titrated and detected in the equation (3) from the amount of iodine present in the first solution. Thereby, the electron density in the sample of the first layer 130 can be measured.

The method of forming the amorphous first layer 130 is not particularly limited. The amorphous first layer 130 may be deposited, for example, by vapor deposition. The amorphous first layer 130 may be deposited, for example, by heating the raw material in a vacuum of 10 ^-7 Pa to 10 ^-3 Pa. Alternatively, the amorphous first layer 130 may be deposited by sputtering or the like.

(Crystalline first layer 130)
The first layer 130 may be composed of an electride of a crystalline oxide containing calcium and aluminum atoms.

  In crystalline oxide electrides, respective cages share a plane to be three-dimensionally stacked to form a crystal lattice, and electrons are included in a part of the cages. In crystalline C12A7 electride, the electrons contained in the cage are loosely bound to the cage and can move freely in the crystal. For this reason, crystalline C12A7 electride exhibits higher conductivity than amorphous C12A7 electride. The composition of “crystalline oxide electride” is the same as the composition of “amorphous oxide electride” described above.

  The crystalline oxide electride can be produced by heat treatment of amorphous oxide electride at 900 ° C. or higher. The heat treatment can be performed by heating using a common electric furnace, infrared heating, laser heating, induction heating, or the like.

(Second layer 140)
The second layer 140 contains zinc (Zn) and oxygen (O), and is further composed of a metal oxide containing at least one of silicon (Si) and tin (Sn).

  For example, the second layer 140 may include zinc (Zn), silicon (Si) and oxygen (O). Hereinafter, such a second layer is particularly referred to as a "ZSO layer". The second layer may also contain zinc (Zn), tin (Sn) and oxygen (O). Hereinafter, such a second layer is particularly referred to as a "ZTO layer". Furthermore, the second layer may contain zinc (Zn), silicon (Si), tin (Sn) and oxygen (O). Hereinafter, such a second layer is particularly referred to as a "ZSTO layer".

  Each of the ZSO layer, the ZTO layer, and the ZSTO layer will be described below.

(ZSO layer)
The ZSO layer contains zinc (Zn), silicon (Si) and oxygen (O). In the case where the second layer 140 is formed of a ZSO layer, since the second layer 140 does not have a grain boundary, the planarity and the homogeneity are excellent as compared with a commonly used oxide semiconductor such as ZnO.

  The value of Zn / (Zn + Si) is, for example, preferably in the range of 0.30 to 0.95 in molar ratio. If it is 0.30 or more, a sufficiently large electron mobility can be obtained and it can be used after being thickened, so that the Si substrate can be sufficiently chemically protected. If it is 0.95 or less, since a smooth surface is obtained, a short circuit can be suppressed. The value of Zn / (Zn + Si) may be 0.70 or more, 0.80 or more, or 0.85 or more in molar ratio. The value of Zn / (Zn + Si) may be 0.94 or less, 0.92 or less, or 0.90 or less in molar ratio.

ZSO layer is preferably chemical composition is represented by _{xZnO- (1-x) SiO 2} (x = 0.30~0.95). Here, if x is 0.30 or more, a sufficiently large electron mobility can be obtained and a thick film can be used, so that the Si substrate can be sufficiently protected. If x is 0.95 or less, a smooth surface can be obtained, so that a short circuit can be suppressed. x may be 0.70 or more, may be 0.80 or more, and may be 0.85 or more. x may be 0.94 or less, 0.92 or less, or 0.90 or less.

ZSO layer is excellent in transparency, for example, shows a high electron mobility ^{0.1cm 2 V -1 s -1 ~5.0cm 2} V -1 s -1. In addition, since the ZSO layer is homogeneous and has low gas permeability because it does not have grain boundaries, it can be used as a protective layer for the Si substrate and various functional layers formed on the substrate. It is known that the characteristics of the Si substrate and various functional layers formed on the substrate deteriorate mainly by the influence of oxygen and moisture when exposed to the outside air, and usually a protective layer is required.

  The thickness of the ZSO layer is preferably in the range of 10 nm to 1000 nm. When the thickness of the ZSO layer is 10 nm or more, it sufficiently functions as a protective layer. In addition, if the thickness of the ZSO layer is 1000 nm or less, the manufacturing process is short. When the thickness of the ZSO layer exceeds 1000 nm, in order to improve the deposition rate (film deposition thickness per unit time), for example, in the case of using a sputtering method, a plurality of sputtering targets may be prepared or high output Film deposition equipment is required. The thickness of the ZSO layer is more preferably 20 nm or more, further preferably 30 nm or more, and particularly preferably 50 nm or more. On the other hand, the thickness of the ZSO layer is more preferably 700 nm or less, still more preferably 500 nm or less, and particularly preferably 300 nm or less.

(ZTO layer)
The ZTO layer contains zinc (Zn), tin (Sn) and oxygen (O). When the second layer 140 is formed of a ZTO layer, the etching rate is appropriate, and a desired shape can be formed without excessive etching, so that semiconductor devices can be stably manufactured.

In the ZTO layer, SnO ₂ is preferably 15 mol% or more and 95 mol% or less with respect to a total of 100 mol% of ZnO and SnO _{2 in} terms of oxide. If the SnO ₂ content is 15 mol% or more, the crystallization temperature is high, and it is difficult to crystallize in the heat treatment process applied in various processes. When the SnO ₂ content is 95 mol% or less, sintering is easy, a good oxide target is obtained, and a thin film is easily formed. SnO ₂ may be 20 mol% or more, 30 mol% or more, 35 mol% or more, or 40 mol% or more. On the other hand, SnO ₂ may be 70 mol% or less, 60 mol% or less, or 50 mol% or less.

ZTO layer is excellent in transparency, for ^example, shows a high electron mobility ^{1cm 2 V -1 s -1 ~10cm 2} V -1 s -1. In addition, since the ZSTO layer is homogeneous and has low gas permeability because it does not have grain boundaries, it can be used as a protective layer for the Si substrate and various functional layers formed on the substrate.

  The thickness of the ZTO layer is preferably in the range of 10 nm to 1000 nm. If the thickness of the ZTO layer is 10 nm or more, it sufficiently functions as a protective layer. If the thickness of the ZTO layer is 1000 nm or less, the manufacturing process is short. The thickness of the ZTO layer is more preferably 20 nm or more, further preferably 30 nm or more, and particularly preferably 50 nm or more. On the other hand, the thickness of the ZSO layer is more preferably 700 nm or less, still more preferably 500 nm or less, and particularly preferably 300 nm or less.

(ZSTO layer)
The ZSTO layer contains zinc (Zn), tin (Sn), silicon (Si) and oxygen (O). When the second layer 140 is formed of a ZSTO layer, the semiconductor device characteristics are improved because the work function is low, the etching rate is appropriate, and high transparency is obtained.

In the ZSTO layer, SnO ₂ is preferably 15 mol% or more and 95 mol% or less based on the total of 100 mol% of ZnO, SnO ₂ , and SiO _{2 in} terms of oxide. If the SnO ₂ content is 15 mol% or more, the crystallization temperature is high, and it is difficult to crystallize in the heat treatment process applied in various processes. If it is 95 mol% or less, it will be easy to sinter, a favorable oxide target will be obtained, and it will be easy to form a thin film. SnO ₂ may be 30 mol% or more, 35 mol% or more, or 40 mol% or more. On the other hand, SnO ₂ may be 70 mol% or less, 60 mol% or less, or 50 mol% or less.

In the ZSTO layer, SiO ₂ is preferably 7 mol% or more and 30 mol% or less with respect to a total of 100 mol% of ZnO, SnO ₂ , and SiO _{2 in} terms of oxide. If SiO ₂ is 7 mol% or more and 30 mol% or less, the electron affinity is not too large and the volume resistivity is not too high. SiO ₂ may be 8 mol% or more, or 10 mol% or more. On the other hand, SiO ₂ may be 20 mol% or less or 15 mol% or less.

ZSTO layer is excellent in transparency, for example, shows a high electron mobility ^{0.1cm 2 V -1 s -1 ~3cm 2} V -1 s -1. In addition, since the ZSTO layer is homogeneous and has low gas permeability because it does not have grain boundaries, it can be used as a protective layer for the Si substrate and various functional layers formed on the substrate.

  The thickness of the ZSTO layer is preferably in the range of 10 nm to 1000 nm. If the thickness of the ZSTO layer is 10 nm or more, it sufficiently functions as a protective layer for the Si substrate and various functional layers formed on the substrate. If the thickness of the ZSTO layer is 1000 nm or less, the manufacturing process is short. The thickness of the ZSTO layer is more preferably 20 nm or more, further preferably 30 nm or more, and particularly preferably 50 nm or more. On the other hand, the thickness of the ZSTO layer is more preferably 700 nm or less, still more preferably 500 nm or less, and particularly preferably 300 nm or less.

The second layer 140 may further include one or more metal components selected from the group consisting of titanium (Ti), indium (In), gallium (Ga), niobium (Nb), and aluminum (Al). . By including these metal components, the chemical durability is excellent. The content of these metal components is preferably 15 mol% or less, more preferably 10 mol or less, based on the total of 100 mol% of oxides of ZnO, SiO ₂ , SnO ₂ and other metal components in terms of oxide. % Or less, more preferably 5 mol% or less. Note that, in terms of oxide, these metals are calculated as a form of TiO ₂ , In ₂ O ₃ , Ga ₂ O ₃ , Nb ₂ O ₅ , or Al ₂ O ₃ .

The composition of the second layer 140 can be analyzed using EPMA when the thickness is 200 nm or more. Moreover, when thickness is 700 nm or more, it can analyze using SEM-EDX of the acceleration voltage of 10 kV, for example. It can also be analyzed by performing substrate correction using XRF. Also, when using ICP, the second layer 140 can be analyzed by using a volume of 1 mm ³ or more.

  The second layer 140 is preferably in an amorphous state or in an amorphous state. Here, “amorphous” means, like the first layer 130, a substance that does not give a sharp peak in X-ray diffraction measurement. In addition, the amorphous state is dominant when amorphous is present in a volume ratio of more than 50%. If the second layer 140 is in an amorphous state or in an amorphous state, this is preferable because the smoothness of the film surface is high and the short circuit of the element can be prevented.

  The second layer 140 may be microcrystalline or may be in the form of a mixture of amorphous and microcrystalline. Here, a microcrystalline is a crystal having a Scherrer diameter of greater than 5.2 nm and less than 100 nm. If the second layer 140 is microcrystalline, it is preferable because the conductivity is improved. It is preferable that the second layer 140 be in a form in which amorphous and microcrystals are mixed, because both the smoothness and the conductivity are improved.

The electron mobility of the second layer 140 is preferably 10 ⁻⁴ cm ² · V ⁻¹ s ⁻¹ to 10 ² cm ² · V ⁻¹ s ⁻¹ . If it is 10 ^-4 cm ² · V ^-1 s ^-1 or more, the thickness of the second layer 140 can be 10 nm or more, and as a protective layer for the Si substrate and various functional layers formed on the substrate Works well. If it is 10 ² cm ² · V ⁻¹ s ⁻¹ or less, the amorphous state becomes dominant, the smoothness of the film surface is high, and short circuiting of the element can be prevented. The electron mobility of the second layer 140 may be 10 ⁻⁴ cm ² · V ⁻¹ s ⁻¹ or higher, and may be 10 ⁻³ cm ² · V ⁻¹ s ⁻¹ or higher. ^It may be ⁻² cm ² · V ⁻¹ s ⁻¹ or more. The electron mobility of the second layer 140 may be 10 ² cm ² · V ⁻¹ s ⁻¹ or less, or 10 cm ² · V ⁻¹ s ⁻¹ or less, 10 ⁻¹ cm ^{2 ···} It may be less than or equal to V ⁻¹ s ⁻¹ .

The electron density of the second layer 140 is preferably 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . If it is 1 × 10 ¹⁴ cm ⁻³ or more, the thickness of the second layer 140 can be 10 nm or more, and functions sufficiently as a protective layer for the Si substrate and various functional layers formed on the substrate. If it is 1 × 10 ²¹ cm ⁻³ or less, the amorphous state becomes dominant, the smoothness of the film surface is high, and short circuiting of the element can be prevented. The electron density of the second layer 140 may be 1 × 10 ¹⁴ cm ⁻³ or more, 5 × 10 ¹⁶ cm ⁻³ or more, or 1 × 10 ¹⁸ cm ⁻³ or more. Good. The electron density of the second layer 140 may be 1 × 10 ²¹ cm ⁻³ or less, 5 × 10 ²⁰ cm ⁻³ or less, or 1 × 10 ²⁰ cm ⁻³ or less Good.

  The electron mobility of the second layer 140 can be determined by Hall measurement or Time-of-Flight (TOF) method or the like. The electron density of the second layer 140 can be determined by an iodine titration method, a hole measurement method, or the like.

  The electron affinity of the second layer 140 is preferably 2.0 eV to 4.0 eV. If it is 2.0 eV or more, the contact resistance can be sufficiently reduced. If it is 4.0 eV or less, the effect of reduction of the contact resistance can not be obtained sufficiently. The electron affinity of the second layer 140 may be 2.0 eV or more, 2.2 eV or more, or 2.5 eV or more. On the other hand, the electron affinity of the second layer 140 may be 4.0 eV or less, 3.5 eV or less, or 3.0 eV or less.

  The ionization potential of the second layer 140 is preferably 5.5 eV to 8.5 eV. The second layer 140 having such a large ionization potential has a high hole blocking effect, and can selectively transport only electrons. The ionization potential of the second layer 140 may be 5.7 eV or more, and may be 5.9 eV or more. On the other hand, the ionization potential of the second layer 140 may be 7.5 eV or less, or 7.0 eV or less.

  As described above, normally, the interface between the n-type Si layer and the metal electrode layer does not exhibit ohmic resistance behavior, and there is a problem that the contact resistance of the interface is high.

  On the other hand, the second layer 140 forms an ohmic junction with the metal electrode layer 150, and the contact resistance of the interface between the two is relatively small. Also, as mentioned above, the contact resistance at the interface between the second layer 140 and the first layer 130 is significantly smaller. Therefore, even if the second layer 140 is provided on the first layer 130, the influence of the increase in the number of interfaces on the increase in the contact resistance is small.

  As a result, by disposing the second layer 140 immediately below the electrode layer 150, it is possible to suppress the overall resistance loss in the first semiconductor element 100. Further, this makes it possible to increase the device efficiency in the first semiconductor device 100.

(Electrode layer 150)
The electrode layer 150 is made of metal. The electrode layer 150 may be made of, for example, aluminum, an aluminum alloy, copper, and a copper alloy.

  The thickness of the electrode layer 150 is, for example, in the range of 50 nm to 100 nm. If the thickness of the electrode layer 150 is 50 nm or more, a low resistance electrode is preferably formed. If the thickness of the electrode layer 150 is 100 nm or less, it is preferable because the difference in level at the edge of the electrode is small and the coverage of a film to be formed later is good. The thickness of the electrode layer 150 may be 60 nm or more, and may be 70 nm or more. On the other hand, the thickness of the electrode layer 150 may be 90 nm or less, or 80 nm or less.

  The electrode layer 150 may be configured, for example, in a mesh shape.

(Method of Manufacturing First Semiconductor Device 100)
Next, with reference to FIG. 2, an example of a method of manufacturing the first semiconductor element 100 having the configuration as shown in FIG. 1 will be described.

  FIG. 2 shows a schematic flow diagram of an example of a method of manufacturing the first semiconductor device 100.

As shown in FIG. 2, this manufacturing method (hereinafter referred to as “first manufacturing method”) is
Placing an n-type Si layer on a support (step S110);
placing a first layer on the n-type Si layer (step S120);
Placing a second layer on the first layer (step S130);
Placing an electrode layer on the second layer (step S140);
Have.

  Each step will be described below. Here, for the sake of clarity, the reference numerals shown in FIG. 1 are used when representing each member.

(Step S110)
First, the support 110 is prepared.

  As mentioned above, the material of the support 110 is not particularly limited. Here, as an example, the case where the support 110 is a Si substrate will be described below as an example.

  The surface of support 110 is thoroughly cleaned prior to the subsequent steps.

  Next, an n-type Si layer 120 is formed on the support 110.

  The n-type Si layer 120 may be formed, for example, by doping the surface of the support 110, ie, the Si substrate, with an n-type dopant such as phosphorus and / or arsenic.

(Step S120)
Next, the first layer 130 is disposed on the n-type Si layer 120.

  The method of forming the first layer 130 is not particularly limited. The first layer 130 can be formed by, for example, a “vapor deposition method” using a target containing aluminum (Al) and calcium (Ca).

  Here, in the present application, the “vapor deposition method” refers to physical vapor deposition (PVD) method, PLD method, sputtering method, and vacuum deposition method. It is a generic term of the film forming method to be deposited on the film member.

For example, the first layer 130 may be deposited by evaporation. The first layer 130 may be deposited by heating the raw material in a vacuum of 10 ⁻⁷ Pa to 10 ⁻³ Pa, for example. If it is 10 ^-7 Pa or more, sufficient electron density can be obtained. It may be 10 ⁻⁶ Pa or more, or 10 ⁻⁵ Pa or more. If it is 10 < ^-3 > Pa or less, a thin film can be formed at low cost using a simple apparatus. 10 ^-4 Pa or less may be sufficient and 10 ^-5 Pa or less may be sufficient. Alternatively, the first layer 130 may be formed by a sputtering method or the like.

  The first layer 130 deposited by a vapor deposition method usually has an amorphous structure. Thereafter, the first layer 130 may be heat-treated, if necessary. In this case, for example, the crystalline first layer 130 can be obtained by heat treatment of the first layer 130 to 900 ° C. or higher.

(Step S130)
Next, the second layer 140 is disposed on the first layer 130.

  The second layer 140 can be formed by, for example, a “vapor phase deposition method” including a sputtering method using a target containing zinc (Zn) and silicon (Si).

  The sputtering method includes DC (direct current) sputtering method, high frequency sputtering method, helicon wave sputtering method, ion beam sputtering method, magnetron sputtering method and the like. In the sputtering method, the second layer 140 can be deposited relatively uniformly in a large area region.

  The target may be any one containing Zn and Si. Zn and Si may be contained in a single target, or may be separately contained in a plurality of targets. In the target, Zn and Si may be present as metal or metal oxide, respectively, and may be present as alloy or mixed metal oxide. The metal oxide or mixed metal oxide may be crystalline or amorphous.

  The target may include, in addition to Zn and Si, one or more metal components selected from the group consisting of Sn, Ti, In, Ga, Nb, and Al. Zn, Si and other metal components may be contained in a single target, or may be separately contained in a plurality of targets. In the target, Zn, Si and other metal components may be present as metals or metal oxides, respectively, or as alloys or complex metal oxides of two or more metals. The metal oxide or mixed metal oxide may be crystalline or amorphous.

When a single target is used, the value of Zn / (Zn + Si) in the target may be 0.30 to 0.95 or 0.70 to 0.94 in molar ratio, 0.80 It may be up to 0.92, or it may be up to 0.85 to 0.90. When a single target contains, in addition to Zn and Si, one or more metal components selected from the group consisting of Sn, Ti, In, Ga, Nb, and Al, the content of these metal components is an oxide Preferably, it is 15 mol% or less, more preferably 10 mol% or less, still more preferably 5 mol% or less, based on a total of 100 mol% of the oxides of ZnO, SiO ₂ and other metal components. Note that, in terms of oxide, the metal component is calculated as SnO ₂ , TiO ₂ , In ₂ O ₃ , Ga ₂ O ₃ , Nb ₂ O ₅ , or Al ₂ O ₃ . Composition analysis of the target can be performed by the XRF method or the like. Note that the composition of the second layer 140 may be different from the composition ratio of the target used.

When a plurality of targets are used, for example, the second layer 140 can be obtained by simultaneously sputtering a target of metal Si and a target of ZnO. Other combinations of targets include a combination of a ZnO target and an SiO ₂ target, a combination of a plurality of targets including ZnO and SiO ₂ and different ZnO ratios, a combination of a metal Zn target and a metal Si target, A combination of a target of metal Zn and a target of SiO ₂ , a combination of a target containing metal Zn or metal Si and a target containing ZnO and SiO ₂ , and the like can be mentioned.

  When a plurality of targets are used simultaneously, the second layer 140 having a desired composition can be obtained by adjusting the power applied to each target.

  When depositing the second layer 140, if the second layer 140 is in an amorphous or amorphous state, the support 110 may not be “actively” heated. preferable. This is because when the temperature of the support 110 rises, the second layer 140 may not easily become amorphous.

  However, the support 110 may be heated "accidentally" by the sputtering process itself by ion bombardment or the like. In this case, how much the temperature of the support 110 rises depends on the sputtering conditions. In order to avoid the temperature rise of the support 110, the support 110 may be "actively" cooled. The first layer 130 is preferably formed at a temperature of 70 ° C. or less for the support 110. The temperature of the support 110 may be 60 ° C. or less, or 50 ° C. or less.

  The pressure of the sputtering gas (pressure in the chamber of the sputtering apparatus) is preferably in the range of 0.05 Pa to 10 Pa, more preferably 0.1 Pa to 5 Pa, and still more preferably 0.2 Pa to 3 Pa. Within this range, the pressure of the sputtering gas is not too low, and the plasma becomes stable. Further, since the pressure of the sputtering gas is not too high, it is possible to suppress the temperature rise of the support 110 due to the increase of the ion bombardment.

The sputtering gas used is not particularly limited. The sputtering gas may be an inert gas or a noble gas. It may contain oxygen. Examples of the inert gas include N ₂ gas. Further, as the noble gas, He (helium), Ne (neon), Ar (argon), Kr (krypton), and Xe (xenon) can be mentioned. These may be used alone or in combination with other gases. Alternatively, the sputtering gas may be a reducing gas such as NO (nitrogen monoxide) or CO (carbon monoxide).

  By the above method, the second layer 140 can be formed on the first layer 130.

(Step S140)
Next, the electrode layer 150 is disposed on the second layer 140.

  The method for forming the electrode layer 150 is not particularly limited. For example, the electrode layer 150 may be formed by a known film formation technique such as a vapor deposition method, a sputtering method, or a coating method.

  The first semiconductor element 100 can be manufactured by the above steps.

  Further, other members may be installed on the first semiconductor element 100 as necessary.

(Another semiconductor device according to one embodiment of the present invention)
Next, another semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 3 shows a schematic cross section of another semiconductor device according to an embodiment of the present invention (hereinafter, referred to as “second semiconductor device”).

  As shown in FIG. 3, the second semiconductor element 200 includes a support 210, an n-type Si layer 220, a first layer 230, a second layer 240, and an electrode layer 250 in this order.

  Here, the configuration of the second semiconductor element 200 is substantially the same as that of the first semiconductor element 100 shown in FIG. For example, in the second semiconductor element 200, the support 210 to the first layer 230 and the electrode layer 250 are respectively the support 110 to the first layer 130 in the first semiconductor element 100 and the electrode layer It has the same configuration as 150.

  However, the second layer 240 in the second semiconductor element 200 is formed of a layer different from the second layer 140 in the first semiconductor element 100.

  Therefore, the second layer 240 will be described in detail below.

(Second layer 240)
The second layer 240 is
(A) Metal oxides containing titanium (Ti) and oxygen (O),
(B) metal oxides containing tin (Sn) and oxygen (O), and (c) metal oxides containing zinc (Zn) and oxygen (O),
It consists of either.

  In the case of (a), the second layer 240 has high chemical durability, and in particular, excellent protection with respect to the Si substrate and various functional layers formed on the substrate. The second layer 240 may be made of titanium oxide doped with Nb (niobium). The second layer 240 is made of titanium oxide doped with Nb (niobium) to exhibit high conductivity, and in particular, the film thickness can be increased. Therefore, various kinds of layers formed on the Si substrate and the substrate can be obtained. Excellent protection to the functional layer. The value of Nb / (Ti + Nb) is, for example, in the range of 0.01 to 0.15 in molar ratio. If it is 0.01 or more, high conductivity is exhibited, and the film thickness can be increased. Therefore, the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. If it is 0.15 or less, Nb (niobium) will form a solid solution, so a homogeneous thin film can be produced. The value of Nb / (Ti + Nb) may be 0.02 or more, 0.03 or more, or 0.05 or more in molar ratio. The value of Nb / (Ti + Nb) may be 0.10 or less, 0.08 or less, or 0.07 or less in molar ratio.

  Further, in the case of (b), the second layer 240 has high chemical durability, and in particular, has excellent protection with respect to the Si substrate and various functional layers formed on the substrate. The second layer 240 may be made of tin oxide, ITO (indium tin oxide), or tin oxide doped with fluorine.

  The second layer 240 is made of tin oxide, so that the second layer 240 has high chemical durability, and in particular, excellent protection with respect to the Si substrate and various functional layers formed on the substrate.

  Since the second layer 240 is made of ITO, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the second layer 240 is excellent in the protection with respect to the Si substrate and various functional layers formed on the substrate. The value of In / (Sn + In) is, for example, in the range of 0.03 to 0.2 in molar ratio. If it is 0.03 or more, high conductivity is exhibited, and the film thickness can be increased. Therefore, the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. If it is 0.20 or less, since Sn (tin) forms a solid solution, a homogeneous thin film can be produced. The value of In / (Sn + In) may be 0.5 or more, 0.07 or more, or 0.09 or more in molar ratio. The value of In / (Sn + In) may be 0.15 or less, 0.13 or less, or 0.11 or less in molar ratio.

  The second layer 240 is made of fluorine-doped tin oxide, so that the second layer 240 has high chemical durability, and in particular, excellent protection with respect to a Si substrate and various functional layers formed on the substrate. The value of F / (Sn + F) is, for example, in the range of 0.01 to 0.2 in molar ratio. If it is 0.01 or more, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. If it is 0.2 or less, since F (fluorine) is solid-solved, a homogeneous thin film can be produced. The value of F / (Sn + F) may be 0.03 or more, 0.05 or more, or 0.08 or more in molar ratio. The value of F / (Sn + F) may be 0.15 or less, 0.12 or less, or 0.1 or less in molar ratio.

  Furthermore, in the case of (c), the second layer 240 may be made of zinc oxide, IZO (indium zinc oxide), zinc oxide doped with aluminum, zinc oxide doped with gallium, or the like.

  Since the second layer 240 is made of zinc oxide, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the second layer 240 is excellent in protection with respect to the Si substrate and various functional layers formed on the substrate. .

  Since the second layer 240 is made of IZO, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the second layer 240 is excellent in the protection with respect to the Si substrate and various functional layers formed on the substrate. The value of Zn / (Zn + In) is, for example, in the range of 0.01 to 0.2 in molar ratio. If it is 0.01 or more, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. Since Zn (zinc) is solid-solved, a homogeneous thin film can be produced. The value of Zn / (Zn + In) may be 0.05 or more, 0.08 or more, or 0.1 or more in molar ratio. The value of Zn / (Zn + In) may be 0.15 or less, 0.13 or less, or 0.11 or less in molar ratio.

  Since the second layer 240 is made of zinc oxide doped with aluminum, high conductivity can be obtained, and in particular, since the film thickness can be increased, various functional layers formed on the Si substrate and the substrate can be obtained. Excellent protection against The value of Al / (Zn + Al) is, for example, in the range of 0.01 to 0.2 in molar ratio. If it is 0.01 or more, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. If it is 0.2 or less, Al (aluminum) forms a solid solution, so that a homogeneous thin film can be produced. The value of Al / (Zn + Al) may be 0.05 or more, 0.08 or more, or 0.1 or more in molar ratio. The value of Al / (Zn + Al) may be 0.15 or less, 0.13 or less, or 0.11 or less in molar ratio.

  The second layer 240 is made of zinc oxide doped with gallium, whereby high conductivity can be obtained, and in particular, since the film thickness can be increased, various functional layers formed on the Si substrate and the substrate can be obtained. Excellent protection against The value of Ga / (Zn + Ga) is, for example, in the range of 0.01 to 0.2 in molar ratio. If it is 0.01 or more, high conductivity can be obtained, and in particular, the film thickness can be increased, so that the protective properties to the Si substrate and various functional layers formed on the substrate are excellent. If it is 0.2 or less, Ga (gallium) will form a solid solution, so a homogeneous thin film can be produced. The value of Ga / (Zn + Ga) may be 0.05 or more, 0.08 or more, or 0.1 or more in molar ratio. The value of Ga / (Zn + Ga) may be 0.15 or less, 0.13 or less, or 0.11 or less in molar ratio.

  The second layer 240 may be crystalline or amorphous.

  The second layer 240 forms an ohmic junction at the interface (second interface) with the metal electrode layer 250, and the contact resistance of the second interface is relatively small. The contact resistance at the interface (third interface) between the second layer 240 and the first layer 230 is also significantly smaller. For this reason, even if the second layer 240 is provided on the first layer 230, the influence of the increase in the contact resistance due to the increase in the number of interfaces is small.

  Also, as described above, the contact resistance is also significantly suppressed at the interface (first interface) between the n-type Si layer 220 and the first layer 230.

  Therefore, also in the second semiconductor element 200, the same effect as in the case of the first semiconductor element 100 can be obtained. That is, in the second semiconductor element 200, the first to third interfaces, that is, the interface (first interface) between the n-type Si layer 220 and the first layer 230, the second layer 240, and the electrode layer The contact resistance is significantly suppressed at each of the interfaces between 250 and 250 (second interface) and the interface between the first layer 230 and the second layer 240 (third interface). As a result, in the second semiconductor element 200, the efficiency at the time of operation can be significantly improved.

(Method of Manufacturing Second Semiconductor Device 200)
As a method of manufacturing the second semiconductor element 200 (hereinafter, referred to as “second manufacturing method”), the flowchart of the first manufacturing method shown in FIG. 2 described above can be referred to. In particular, steps S110 to S120 and step S140 in the first manufacturing method described above can be applied to the second manufacturing method as it is.

  Therefore, here, step S130 shown in FIG. 2 in particular, that is, an example of the method of installing the second layer will be described.

(How to install the second layer 240)
The second layer 240, as described above,
(A) Metal oxides containing titanium (Ti) and oxygen (O),
(B) metal oxides containing tin (Sn) and oxygen (O), or (c) metal oxides containing zinc (Zn) and oxygen (O),
It consists of either.

  The second layer 240 can be formed by, for example, a "vapor phase deposition method" including a sputtering method.

  The sputtering method includes DC (direct current) sputtering method, high frequency sputtering method, helicon wave sputtering method, ion beam sputtering method, magnetron sputtering method and the like. In the sputtering method, the second layer 240 can be deposited relatively uniformly in a large area region.

  The target may be any one containing a predetermined material. For example, in the case of the above (a), a target containing Ti is used. Moreover, in the case of the above-mentioned (b), the target containing Sn is used. Furthermore, in the case of (c) above, a target containing Zn is used. These targets may be metals or metal oxides. The target may be crystalline or amorphous.

  In the case where the second layer 240 is a layer which is in the amorphous state or in the amorphous state, the support 210 in forming the second layer 240 may not be “actively” heated. preferable.

  In addition, the installation method of the 2nd layer 240 shown here is only an example, and the 2nd layer 240 may be installed by other methods.

(Still another semiconductor device according to one embodiment of the present invention)
Next, another semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 4 shows a schematic cross section of still another semiconductor device according to an embodiment of the present invention (hereinafter, referred to as “third semiconductor device”).

  As shown in FIG. 4, the third semiconductor device 300 includes a support 310, an n-type Si layer 320, a first layer 330, a third layer 342, a fourth layer 344, and an electrode layer. And 350.

  Here, the third semiconductor element 300 has a configuration similar to the first semiconductor element 100 shown in FIG. For example, in the third semiconductor element 300, the support 310 to the third layer 342 and the electrode layer 350 are respectively the support 110 to the second layer 140 in the first semiconductor element 100 and the electrode layer It has the same configuration as 150. That is, the third layer 342 in the third semiconductor element 300 corresponds to the second layer 140 in the first semiconductor element 100.

  However, the third semiconductor element 300 is different from the first semiconductor element 100 in that a fourth layer 344 is provided between the third layer 342 and the electrode layer 350. In other words, the third semiconductor element 300 has a configuration in which two layers of the third layer 342 and the fourth layer 344 are disposed instead of the second layer 140 in the first semiconductor element 100. I can say that.

Here, the fourth layer 344 corresponds to the second layer 240 in the second semiconductor element 200. That is, the fourth layer 344
(A) Metal oxides containing titanium (Ti) and oxygen (O),
(B) metal oxides containing tin (Sn) and oxygen (O), or (c) metal oxides containing zinc (Zn) and oxygen (O),
It consists of either.

  As described above, in the case of (a), the fourth layer 344 may be made of titanium oxide doped with Nb (niobium). In the case of (b), the fourth layer 344 may be made of tin oxide, ITO (indium tin oxide), or tin oxide doped with fluorine or the like. Further, in the case of (c), the fourth layer 344 may be made of zinc oxide, IZO (indium zinc oxide), zinc oxide doped with aluminum, zinc oxide doped with gallium, or the like.

  The fourth layer 344 may be crystalline or amorphous.

  Here, in the third semiconductor element 300, the number of layers is increased by one as compared with the first semiconductor element 100 and the second semiconductor element 200 described above, and as a result, the interface is also increased by one.

  However, according to the findings of the inventors of the present invention, it is confirmed that the contact resistance of the interface between the third layer 342 and the fourth layer 344 (hereinafter, referred to as “fourth interface”) is relatively low. . Therefore, although the number of layers and the number of interfaces increase in the third semiconductor element 300 as compared with the first semiconductor element 100 and the second semiconductor element 200, the influence thereof hardly occurs.

  Therefore, also in the third semiconductor device 300 having such a configuration, the same effect as in the case of the first semiconductor device 100 and the second semiconductor device 200 can be obtained. That is, in the third semiconductor element 300, the interface (first interface) between the n-type Si layer 320 and the first layer 330, the interface (fourth) between the fourth layer 344 and the electrode layer 350 Contact resistance is significantly suppressed at each of the interfaces of the first layer 330 and the third layer 342 (third interface).

  Therefore, in the third semiconductor element 300, the contact resistance can be reduced as compared with the first semiconductor element 100 and the second semiconductor element 200, so that the element efficiency can be significantly improved. In addition, when the third layer 342 and the fourth layer 344 have different refractive indexes, the degree of freedom in optical design can be increased.

A person skilled in the art can easily understand the method of manufacturing the third semiconductor device 300 from the description of the method of manufacturing the first semiconductor device 100 and the second semiconductor device 200 described above.
In the above, one embodiment of the present invention has been described by taking the first to third semiconductor elements 100, 200, and 300 as examples. However, the present invention is not limited to these configurations. For example, in the first to third semiconductor elements 100, 200, and 300, the n-type Si layers 120, 220, and 320 may be made of another n-type semiconductor material other than Si.

(Example of application of semiconductor device according to one embodiment of the present invention)
Next, application examples of the semiconductor device according to the embodiment of the present invention will be described. Here, the application example will be described by taking the configuration of the first semiconductor element 100 described above as an example. However, it will be apparent to those skilled in the art that the same application is possible in the configuration of the second or third semiconductor device 200, 300 described above.

(Solar cell module)
The semiconductor device according to one embodiment of the present invention can be applied to, for example, a solar cell module.

  One structural example of such a solar cell module is typically shown in FIG.

  As shown in FIG. 5, the solar cell module 500 is configured by electrically connecting a plurality of solar cells 502 in series.

  Each solar cell 502 has a first electrode 560A and a second electrode 560B made of metal, and a first portion 580 and a second portion 590 are disposed between the electrodes 560A and 560B. . In other words, the solar battery cell 502 is configured by arranging the second electrode 560B, the second portion 590, the first portion 580, and the first electrode 560A in order from the bottom.

  The first electrode 560A is electrically connected to the second electrode 560B of the adjacent right solar cell 502. The second electrode 560B is electrically connected to the first electrode 560A of the adjacent left solar cell 502. Thereby, each photovoltaic cell 502 is mutually connected in series.

  The first portion 580 has an n-type Si layer, and the second portion 590 has a p-type Si layer. The n-type Si layer of the first portion 580 forms a pn junction with the p-type Si layer of the second portion 590.

  Here, the second portion 590 to the first electrode 560A are formed of the above-described first semiconductor element 100. That is, the second portion 590 of the solar cell 502 corresponds to the support 110 of the first semiconductor element 100, and the first portion 580 of the solar cell 502 is the n-type Si of the first semiconductor element 100. The first electrode 560A in the solar battery cell 502 corresponds to the electrode layer 150 of the first semiconductor element 100, which corresponds to the layer 120, the first layer 130, and the second layer 140.

  As described above, in the conventional solar cell module, the contact resistance between the first electrode and the n-type Si layer in the first portion 580 is relatively high, and thus there is a limit to the improvement of the power generation efficiency. The

  However, in the solar cell module 500 shown in FIG. 5, the first semiconductor element 100 having the above-described features is applied. For this reason, in the solar cell module 500, the power generation efficiency can be significantly improved.

(TFT)
The semiconductor device according to an embodiment of the present invention can be applied to, for example, a TFT.

  FIG. 6 schematically shows one configuration example of such a TFT.

  As shown in FIG. 6, the TFT 600 includes a gate electrode 601, a gate insulating film 603, an amorphous Si layer 690, an n-type Si layer 680, a first electrode 660A (for example, a source), and a second electrode 660B (for example, a drain) A channel protective layer 670 and a protective film 675 are provided.

  In addition, since the role of these members is clear to those skilled in the art, the detailed description is omitted here.

  Here, the portion of the amorphous Si layer 690 to the first electrode 660A or the portion of the amorphous Si layer 690 to the second electrode 660B is formed of the first semiconductor element 100 described above. That is, the amorphous Si layer 690 in the TFT 600 corresponds to the support 110 of the first semiconductor element 100, and the n-type Si layer 680 in the TFT 600 corresponds to the n-type Si layer 120 of the first semiconductor element 100. The first electrode 660 A or the second electrode 660 B in the TFT 600 corresponds to the electrode layer 150 of the first semiconductor element 100.

  As described above, in the conventional TFT, the contact resistance between the first or second electrode and the n-type Si layer is relatively high, which limits the improvement of the operation efficiency.

  However, the first semiconductor element 100 having the above-mentioned features is applied to the TFT 600 shown in FIG. Therefore, the TFT 600 can significantly improve the operation efficiency.

  Hereinabove, the application example of the semiconductor device according to the embodiment of the present invention has been described by taking the solar cell module and the TFT as an example. However, these applications are merely examples, and the semiconductor device according to one embodiment of the present invention may be applied to other devices.

  Next, examples of the present invention will be described.

(Example 1)
The semiconductor device as shown in FIG. 1 was manufactured by the following method.

First, an n-type Si substrate was prepared. The n-type Si substrate had dimensions of 30 mm long × 30 mm wide × 0.5 mm thick, and the electron density was 10 ¹⁵ cm ⁻³ .

  The n-type Si substrate (hereinafter simply referred to as "substrate") was cleaned with hydrofluoric acid and pure water before use to remove the natural oxide film on the surface.

Next, the substrate was introduced into a sputtering apparatus. After the inside of the sputtering apparatus was evacuated to 3 × 10 ⁻⁷ Pa, amorphous C 12 A 7 electride was formed as a first layer on the substrate by a sputtering method.

  At the time of film formation, a metal mask was used to form four rectangular first layers (2 nm in thickness) each having a width of 200 μm × a length of 800 μm × a thickness of 2 nm on the substrate. The intervals between adjacent rectangles were 400 μm, 600 μm, and 800 μm, respectively.

  At the time of film formation, the RF power was 100 W, Ar was used as a film forming gas, and the total pressure was 0.15 Pa. Moreover, the distance between the substrate and the target was 100 mm.

The electron density of the obtained first layer was 10 ²¹ cm ⁻³ .

  Next, while the substrate was introduced into the sputtering apparatus, a second layer was formed by sputtering on each rectangular first layer. The second layer was a ZSO layer.

  As a target, one having a composition of Zn: Si = 80: 20 in molar ratio was used.

The distance between the target and the substrate at the time of film formation was 100 mm. The sputtering gas at the time of film formation was a mixed gas of Ar and O ₂ , and the pressure of the sputtering gas was 0.4 Pa. The flow rate of Ar was 39.9 sccm, and the flow rate of O ₂ was 0.1 sccm. The RF plasma power was 100 W. Thereby, the 10-nm-thick second layer was formed only on the first layer.
The electron density of the obtained second layer was 10 ¹⁵ cm ⁻³ .

  Thereafter, the substrate on which each layer was formed was taken out to the atmosphere and left to stand for 1.5 hours.

  Next, the substrate was returned to the same sputtering apparatus, and an Al alloy layer (hereinafter referred to as "Al electrode") was formed only on the second layer. The Al electrode was deposited by sputtering using an Al: 2% Nd target.

  The thickness of the Al electrode was 200 nm in any portion of the four rectangles.

  A semiconductor element (hereinafter, referred to as “sample A”) was formed by such a method.

(Example 2)
A semiconductor device was manufactured in the same manner as in Example 1.

However, in this example 3, titanium oxide doped with Nb (niobium) was formed as a second layer on the first layer. As a target, one having a composition of Ti: Nb = 94: 6 in molar ratio was used. The distance between the target and the substrate at the time of film formation was 100 mm. The sputtering gas at the time of film formation was a mixed gas of Ar and O ₂ , and the pressure of the sputtering gas was 0.4 Pa. The flow rate of Ar was 40 sccm. The RF plasma power was 100 W. Thereby, the 10-nm-thick second layer was formed only on the first layer. At this time, the second layer was amorphous.

  Thereafter, the substrate on which each layer was formed was taken out to the atmosphere and left for 48 hours.

  Next, the substrate was returned to the same sputtering apparatus, and an Al electrode was formed only on the second layer.

  The obtained semiconductor device is hereinafter referred to as “sample B”.

(Example 3)
A semiconductor device was manufactured in the same manner as in Example 1.

  However, in this example 3, the second layer was not formed on the first layer. That is, an Al electrode was formed directly on the amorphous C12A7 electride layer. The film forming conditions and the like of each layer are the same as in the case of Example 1.

  The obtained semiconductor device is hereinafter referred to as “sample C”.

(Evaluation)
Resistance measurements were made using sample A, sample B and sample C described above. The TLM method (Transmission Line Model) was used for resistance measurement.

  In this method, by measuring the current and voltage between each two Al electrodes, it is possible to measure the resistance of the sample as a function of the distance between the two Al electrodes. Keithley 2635B was used for the current voltmeter.

  As a result of the measurement, it was confirmed that the resistance change was ohmic in sample A and sample B. On the other hand, in sample C, it was confirmed that the resistance change was not ohmic.

  FIG. 7 summarizes the measurement results obtained for Sample A, Sample B, and Sample C.

  In FIG. 7, the horizontal axis is the distance between the Al electrodes, and the vertical axis is the resistance value.

It can be seen from FIG. 7 that sample A and sample B show significantly lower resistance values as compared to sample C. Although not shown, four rectangular Al electrodes were formed directly on the substrate, and the same measurement was performed. As a result, it was confirmed that the resistance change was not ohmic in such a sample. Moreover, it turned out that the absolute value of resistance is significantly high irrespective of the distance between Al electrodes.
As a cause of this, it is conceivable that the interface of the amorphous C12A7 electride layer, which is an oxide, is altered. Amorphous C12A7 elect from the electrical conduction cage Ride layer instead O ^2- is missing e ^- contain e ^- but are considered to be obtained by moving the interface of the amorphous C12A7 electride layer It is inferred that oxygen atoms enter the cage to reduce the electrical properties, which is considered to be a phenomenon unique to the amorphous C12A7 electride layer.

  Thus, while arranging the above-mentioned first layer (C12A7 electride layer) right above the n-type layer, and arranging the above-mentioned second layer (ZSO layer or titanium oxide layer) directly below the Al electrode. Thus, it was confirmed that the contact resistances of the first interface and the second interface were both suppressed, and the overall resistance value of the semiconductor element could be reduced.

  The semiconductor device of the present invention can be applied to, for example, a solar cell module and a thin film transistor (TFT). Further, the present invention can be applied to semiconductor devices and the like used for various electronic devices and the like such as electro-optical devices. For example, it can be used for displays such as TVs, electric appliances such as washing machines and refrigerators, and electronic devices such as information processing devices such as mobile phones and computers. The semiconductor element of the present invention can also be used in electronic devices such as automobiles and various industrial devices.

  The present application claims priority based on Japanese Patent Application No. 2016-195785 filed on October 3, 2016, the entire contents of which are incorporated herein by reference.

DESCRIPTION OF SYMBOLS 100 1st semiconductor element 110 support body 120 n-type Si layer 130 1st layer 140 2nd layer 150 electrode layer 200 2nd semiconductor element 210 support body 220 n-type Si layer 230 1st layer 240 2nd Layer 250 electrode layer 300 third semiconductor element 310 support 320 n-type Si layer 330 first layer 342 third layer 344 fourth layer 350 electrode layer 500 solar cell module 502 each solar cell 560A first electrode 560 B Second electrode 580 First portion 590 Second portion 600 TFT
601 gate electrode 603 gate insulating film 660A first electrode 660B second electrode 670 channel protective layer 675 protective film 680 n-type Si layer 690 amorphous Si layer

Claims (9)

n-type Si part,
A first layer disposed on the n-type Si portion,
A second layer disposed on the first layer;
An electrode layer disposed on the second layer;
Have
The first layer is made of electride of oxide containing calcium atom and aluminum atom,
Said second layer comprises the following groups:
(I) A metal oxide containing zinc (Zn) and oxygen (O), and further containing at least one of silicon (Si) and tin (Sn),
(Ii) metal oxides containing titanium (Ti) and oxygen (O),
(Iii) metal oxides containing tin (Sn) and oxygen (O), and (iv) metal oxides containing zinc (Zn) and oxygen (O),
Semiconductor devices selected from   The semiconductor device according to claim 1, wherein the first layer is amorphous.   The semiconductor device according to claim 1, wherein the metal oxide of (i) is amorphous.   The semiconductor device according to any one of claims 1 to 3, wherein the metal oxide of (ii) is titanium oxide doped with Nb (niobium).   The semiconductor device according to any one of claims 1 to 4, wherein the metal oxide of (iii) is indium tin oxide (ITO) or fluorine-doped tin oxide.   The semiconductor device according to any one of claims 1 to 5, wherein the metal oxide of (iv) is zinc oxide doped with aluminum and / or gallium. The second layer is composed of at least two layers including a third layer and a fourth layer from the side close to the first layer,
The third layer is selected from (i),
The semiconductor device according to any one of claims 1 to 6, wherein the fourth layer is selected from one of the (ii) to (iv).   A solar cell module comprising the semiconductor device according to any one of claims 1 to 7.   A TFT comprising the semiconductor element according to any one of claims 1 to 7.

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