JPWO2017209883A5 - - Google Patents

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Publication number
JPWO2017209883A5
JPWO2017209883A5 JP2018555617A JP2018555617A JPWO2017209883A5 JP WO2017209883 A5 JPWO2017209883 A5 JP WO2017209883A5 JP 2018555617 A JP2018555617 A JP 2018555617A JP 2018555617 A JP2018555617 A JP 2018555617A JP WO2017209883 A5 JPWO2017209883 A5 JP WO2017209883A5
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Japan
Prior art keywords
memory
host
processor
coherence
cache
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JP2018555617A
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English (en)
Japanese (ja)
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JP2019517687A (ja
JP7160682B2 (ja
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Priority claimed from US15/169,118 external-priority patent/US10503641B2/en
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JP2018555617A 2016-05-31 2017-05-02 メモリにおける処理のためのキャッシュコヒーレンス Active JP7160682B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/169,118 2016-05-31
US15/169,118 US10503641B2 (en) 2016-05-31 2016-05-31 Cache coherence for processing in memory
PCT/US2017/030586 WO2017209883A1 (en) 2016-05-31 2017-05-02 Cache coherence for processing in memory

Publications (3)

Publication Number Publication Date
JP2019517687A JP2019517687A (ja) 2019-06-24
JPWO2017209883A5 true JPWO2017209883A5 (ru) 2022-07-15
JP7160682B2 JP7160682B2 (ja) 2022-10-25

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JP2018555617A Active JP7160682B2 (ja) 2016-05-31 2017-05-02 メモリにおける処理のためのキャッシュコヒーレンス

Country Status (6)

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US (1) US10503641B2 (ru)
EP (1) EP3465445B1 (ru)
JP (1) JP7160682B2 (ru)
KR (1) KR102442079B1 (ru)
CN (1) CN109154910B (ru)
WO (1) WO2017209883A1 (ru)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10866900B2 (en) * 2017-10-17 2020-12-15 Samsung Electronics Co., Ltd. ISA extension for high-bandwidth memory
US10365980B1 (en) * 2017-10-31 2019-07-30 EMC IP Holding Company LLC Storage system with selectable cached and cacheless modes of operation for distributed storage virtualization
US10474545B1 (en) 2017-10-31 2019-11-12 EMC IP Holding Company LLC Storage system with distributed input-output sequencing
KR20190075363A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 모듈
US11288195B2 (en) * 2019-03-22 2022-03-29 Arm Limited Data processing
US10922236B2 (en) 2019-04-04 2021-02-16 Advanced New Technologies Co., Ltd. Cascade cache refreshing
CN110059023B (zh) * 2019-04-04 2020-11-10 创新先进技术有限公司 一种刷新级联缓存的方法、系统及设备
US11126537B2 (en) 2019-05-02 2021-09-21 Microsoft Technology Licensing, Llc Coprocessor-based logging for time travel debugging
CN111176582A (zh) * 2019-12-31 2020-05-19 北京百度网讯科技有限公司 矩阵存储方法、矩阵访问方法、装置和电子设备
US11023375B1 (en) * 2020-02-21 2021-06-01 SiFive, Inc. Data cache with hybrid writeback and writethrough
US11467834B2 (en) * 2020-04-01 2022-10-11 Samsung Electronics Co., Ltd. In-memory computing with cache coherent protocol
KR20210154277A (ko) 2020-06-11 2021-12-21 삼성전자주식회사 메모리 모듈 및 그의 동작 방법
US11360906B2 (en) 2020-08-14 2022-06-14 Alibaba Group Holding Limited Inter-device processing system with cache coherency
KR20220032366A (ko) 2020-09-07 2022-03-15 삼성전자주식회사 가변적인 모드 설정을 수행하는 메모리 장치 및 그 동작방법
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
JP2023007601A (ja) * 2021-07-02 2023-01-19 株式会社日立製作所 ストレージシステム制御方法及びストレージシステム
US11989142B2 (en) 2021-12-10 2024-05-21 Samsung Electronics Co., Ltd. Efficient and concurrent model execution
US20230281128A1 (en) * 2022-03-03 2023-09-07 Samsung Electronics Co., Ltd. Cache-coherent interconnect based near-data-processing accelerator
US11809323B1 (en) * 2022-06-22 2023-11-07 Seagate Technology Llc Maintaining real-time cache coherency during distributed computational functions

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816474A (ja) * 1994-06-29 1996-01-19 Hitachi Ltd マルチプロセッサシステム
US5829034A (en) * 1996-07-01 1998-10-27 Sun Microsystems, Inc. Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains
US6269428B1 (en) * 1999-02-26 2001-07-31 International Business Machines Corporation Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system
US6338123B2 (en) * 1999-03-31 2002-01-08 International Business Machines Corporation Complete and concise remote (CCR) directory
US6751705B1 (en) * 2000-08-25 2004-06-15 Silicon Graphics, Inc. Cache line converter
US6470429B1 (en) * 2000-12-29 2002-10-22 Compaq Information Technologies Group, L.P. System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops
US6463510B1 (en) * 2000-12-29 2002-10-08 Compaq Information Technologies Group, L.P. Apparatus for identifying memory requests originating on remote I/O devices as noncacheable
US7177987B2 (en) 2004-01-20 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for responses between different cache coherency protocols
US20050216637A1 (en) * 2004-03-23 2005-09-29 Smith Zachary S Detecting coherency protocol mode in a virtual bus interface
US7167956B1 (en) * 2004-05-03 2007-01-23 Sun Microsystems, Inc. Avoiding inconsistencies between multiple translators in an object-addressed memory hierarchy
US7552236B2 (en) 2005-07-14 2009-06-23 International Business Machines Corporation Routing interrupts in a multi-node system
US7395376B2 (en) 2005-07-19 2008-07-01 International Business Machines Corporation Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks
US7376799B2 (en) * 2005-07-21 2008-05-20 Hewlett-Packard Development Company, L.P. System for reducing the latency of exclusive read requests in a symmetric multi-processing system
US7748037B2 (en) 2005-09-22 2010-06-29 Intel Corporation Validating a memory type modification attempt
US8539164B2 (en) * 2007-04-30 2013-09-17 Hewlett-Packard Development Company, L.P. Cache coherency within multiprocessor computer system
US7941613B2 (en) 2007-05-31 2011-05-10 Broadcom Corporation Shared memory architecture
US8082400B1 (en) 2008-02-26 2011-12-20 Hewlett-Packard Development Company, L.P. Partitioning a memory pool among plural computing nodes
US8473644B2 (en) * 2009-03-04 2013-06-25 Freescale Semiconductor, Inc. Access management technique with operation translation capability
US8176220B2 (en) 2009-10-01 2012-05-08 Oracle America, Inc. Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors
US8543770B2 (en) * 2010-05-26 2013-09-24 International Business Machines Corporation Assigning memory to on-chip coherence domains
US20120124297A1 (en) 2010-11-12 2012-05-17 Jaewoong Chung Coherence domain support for multi-tenant environment
CN103229152B (zh) * 2010-11-26 2016-10-19 国际商业机器公司 高速缓存一致性控制方法、系统和程序
US9753858B2 (en) * 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
CN104145251B (zh) 2012-03-02 2017-06-09 Arm 有限公司 具有第一协议域和第二协议域的数据处理装置及其方法
US20140018141A1 (en) * 2012-07-11 2014-01-16 Sergey Anikin Method for expanding sales through computer game
US8922243B2 (en) 2012-12-23 2014-12-30 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
WO2014065880A1 (en) * 2012-10-22 2014-05-01 Robert Beers Coherence protocol tables
US9442852B2 (en) * 2012-11-27 2016-09-13 International Business Machines Corporation Programmable coherent proxy for attached processor
US9069674B2 (en) * 2012-11-27 2015-06-30 International Business Machines Corporation Coherent proxy for attached processor
US9251069B2 (en) 2012-12-21 2016-02-02 Advanced Micro Devices, Inc. Mechanisms to bound the presence of cache blocks with specific properties in caches
US9235528B2 (en) 2012-12-21 2016-01-12 Advanced Micro Devices, Inc. Write endurance management techniques in the logic layer of a stacked memory
US9170948B2 (en) 2012-12-23 2015-10-27 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die
US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
US9244629B2 (en) 2013-06-25 2016-01-26 Advanced Micro Devices, Inc. Method and system for asymmetrical processing with managed data affinity
JP6637906B2 (ja) * 2014-05-08 2020-01-29 マイクロン テクノロジー，インク． ハイブリッドメモリキューブシステム相互接続ディレクトリベースキャッシュコヒーレンス方法
CN106415522B (zh) 2014-05-08 2020-07-21 美光科技公司 存储器内轻量一致性
US9542316B1 (en) * 2015-07-23 2017-01-10 Arteris, Inc. System and method for adaptation of coherence models between agents

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