JP5714733B2 - キャッシュ競合の解決 - Google Patents
キャッシュ競合の解決 Download PDFInfo
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- JP5714733B2 JP5714733B2 JP2014006733A JP2014006733A JP5714733B2 JP 5714733 B2 JP5714733 B2 JP 5714733B2 JP 2014006733 A JP2014006733 A JP 2014006733A JP 2014006733 A JP2014006733 A JP 2014006733A JP 5714733 B2 JP5714733 B2 JP 5714733B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
Claims (7)
- プロセッサであって、
複数の処理コアと、
前記複数の処理コアの包含的なキャッシュとして作用するための最終レベル・キャッシュと、
前記最終レベル・キャッシュと前記複数の処理コアとの間のオーダリング・ロジックであって、前記オーダリング・ロジックは、前記複数の処理コアによって行われる、キャッシュ線に対するアクセスを管理し、前記オーダリング・ロジックは、前記キャッシュ線の所有権及びコヒーレンス状態情報を管理するためのデータ記憶装置を有し、前記処理コアの1つによって行われるが、前記処理コアの別の1つによって所有される排他的状態におけるキャッシュ線に対する読み出し要求により、前記オーダリング・ロジックは、前記キャッシュ線が前記排他的状態にある旨を示す、前記キャッシュ線の情報を保存し、前記キャッシュ線のデータが前記処理コアの前記1つによって受け取られ、それにより、前記情報が前記データ記憶装置から取り出され、前記キャッシュ線が前記排他的状態に戻されるまで前記キャッシュ線を無効状態におくプロセッサ。 - 請求項1記載のプロセッサであって、前記コヒーレンス状態情報は、第2のキャッシュ線を前記処理コアが共有することを可能にする状態を含み、しかし、前記第2のキャッシュ線は、前記プロセッサによって排他的に保有されていると前記プロセッサの外部の要求エージェントにみなされるプロセッサ。
- 請求項1記載のプロセッサであって、前記コヒーレンス状態情報は、第2のキャッシュ線を前記処理コアが共有することを可能にする状態を含み、しかし、前記第2のキャッシュ線は、修正されていると前記プロセッサの外部の要求エージェントにみなされるプロセッサ。
- 請求項1記載のプロセッサであって、前記処理コアはそれぞれ、それら自身のそれぞれのキャッシュを前記最終レベルのキャッシュの上に有するプロセッサ。
- 請求項1記載のプロセッサであって、前記処理コアはポイントツーポイント相互接続を介して結合されるプロセッサ。
- 第1の処理コア及び第2の処理コアの包含的なキャッシュの前の点で行われる方法であって、
キャッシュ線に対する読み出しを前記第1の処理コアから受け取る工程と、
前記キャッシュ線が排他的状態にあり、前記第2の処理コアによって所有されていると認識する工程と、
前記キャッシュ線を無効状態にし、前記キャッシュ線が排他的状態を有している旨を示す、前記キャッシュ線の情報を保存する工程と、
前記キャッシュ線の前記第1の処理コアと前記第2の処理コアとの間のクロス・スヌープの完了により、前記情報を読み出し、前記キャッシュ線をその排他的状態に戻す方法。 - 請求項6記載の方法であって、前記包含的なキャッシュは、前記第1の処理コア及び前記第2の処理コアによって共有された最終レベル・キャッシュである方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US93797304A | 2004-09-09 | 2004-09-09 | |
US10/937,973 | 2004-09-09 |
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JP2011145496A Division JP5535991B2 (ja) | 2004-09-09 | 2011-06-30 | キャッシュ競合の解決 |
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JP2014089760A JP2014089760A (ja) | 2014-05-15 |
JP5714733B2 true JP5714733B2 (ja) | 2015-05-07 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007531199A Pending JP2008512772A (ja) | 2004-09-09 | 2005-08-26 | キャッシュ競合の解決 |
JP2011145496A Expired - Fee Related JP5535991B2 (ja) | 2004-09-09 | 2011-06-30 | キャッシュ競合の解決 |
JP2014006733A Expired - Fee Related JP5714733B2 (ja) | 2004-09-09 | 2014-01-17 | キャッシュ競合の解決 |
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JP2007531199A Pending JP2008512772A (ja) | 2004-09-09 | 2005-08-26 | キャッシュ競合の解決 |
JP2011145496A Expired - Fee Related JP5535991B2 (ja) | 2004-09-09 | 2011-06-30 | キャッシュ競合の解決 |
Country Status (5)
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US (2) | US9727468B2 (ja) |
JP (3) | JP2008512772A (ja) |
CN (3) | CN100498739C (ja) |
DE (1) | DE112005002180T5 (ja) |
WO (1) | WO2006031414A2 (ja) |
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US8015365B2 (en) * | 2008-05-30 | 2011-09-06 | Intel Corporation | Reducing back invalidation transactions from a snoop filter |
US20090300291A1 (en) * | 2008-06-03 | 2009-12-03 | Gerald Keith Bartley | Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System |
US8250311B2 (en) * | 2008-07-07 | 2012-08-21 | Intel Corporation | Satisfying memory ordering requirements between partial reads and non-snoop accesses |
CN101739298B (zh) * | 2008-11-27 | 2013-07-31 | 国际商业机器公司 | 共享缓存管理方法和系统 |
DE112013004105T5 (de) * | 2012-10-22 | 2015-04-30 | Intel Corp. | Kohärenzprotokolltabellen |
US10268583B2 (en) | 2012-10-22 | 2019-04-23 | Intel Corporation | High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier |
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CN109240945B (zh) * | 2014-03-26 | 2023-06-06 | 阿里巴巴集团控股有限公司 | 一种数据处理方法及处理器 |
CN104035888B (zh) * | 2014-06-11 | 2017-08-04 | 华为技术有限公司 | 一种缓存数据的方法及存储设备 |
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2005
- 2005-01-28 US US11/045,525 patent/US9727468B2/en active Active
- 2005-08-26 WO PCT/US2005/030444 patent/WO2006031414A2/en active Application Filing
- 2005-08-26 CN CNB2005800297873A patent/CN100498739C/zh not_active Expired - Fee Related
- 2005-08-26 DE DE112005002180T patent/DE112005002180T5/de not_active Ceased
- 2005-08-26 JP JP2007531199A patent/JP2008512772A/ja active Pending
- 2005-08-26 CN CN2008101761362A patent/CN101425043B/zh not_active Expired - Fee Related
- 2005-08-26 CN CN2008101761358A patent/CN101425042B/zh not_active Expired - Fee Related
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2011
- 2011-06-30 JP JP2011145496A patent/JP5535991B2/ja not_active Expired - Fee Related
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2014
- 2014-01-17 JP JP2014006733A patent/JP5714733B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN101425042B (zh) | 2011-07-06 |
JP2008512772A (ja) | 2008-04-24 |
CN101425043A (zh) | 2009-05-06 |
US20060053257A1 (en) | 2006-03-09 |
US20170337131A1 (en) | 2017-11-23 |
CN101010670A (zh) | 2007-08-01 |
US10078592B2 (en) | 2018-09-18 |
WO2006031414A2 (en) | 2006-03-23 |
WO2006031414A3 (en) | 2007-01-25 |
CN100498739C (zh) | 2009-06-10 |
CN101425043B (zh) | 2012-06-20 |
DE112005002180T5 (de) | 2007-07-05 |
US9727468B2 (en) | 2017-08-08 |
CN101425042A (zh) | 2009-05-06 |
JP5535991B2 (ja) | 2014-07-02 |
JP2011227921A (ja) | 2011-11-10 |
JP2014089760A (ja) | 2014-05-15 |
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