JPWO2016047534A1 - Semiconductor device provided with SiC layer - Google Patents

Semiconductor device provided with SiC layer Download PDF

Info

Publication number
JPWO2016047534A1
JPWO2016047534A1 JP2016550139A JP2016550139A JPWO2016047534A1 JP WO2016047534 A1 JPWO2016047534 A1 JP WO2016047534A1 JP 2016550139 A JP2016550139 A JP 2016550139A JP 2016550139 A JP2016550139 A JP 2016550139A JP WO2016047534 A1 JPWO2016047534 A1 JP WO2016047534A1
Authority
JP
Japan
Prior art keywords
layer
sic
semiconductor device
substrate
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016550139A
Other languages
Japanese (ja)
Inventor
英俊 浅村
英俊 浅村
川村 啓介
啓介 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Air Water Inc
Original Assignee
Air Water Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Air Water Inc filed Critical Air Water Inc
Publication of JPWO2016047534A1 publication Critical patent/JPWO2016047534A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02447Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高める。半導体装置は、Si(シリコン)基板と、Si基板の表面に形成されたSiO2(酸化シリコン)層と、SiO2層の表面に形成されたSi層と、Si層の表面上に形成されたSiC(炭化シリコン)層とを備えている。SiO2層の厚さは、1μm以上20μm以下である。The vertical breakdown voltage of the semiconductor device is increased while ensuring the quality of the semiconductor device. The semiconductor device includes a Si (silicon) substrate, a SiO2 (silicon oxide) layer formed on the surface of the Si substrate, a Si layer formed on the surface of the SiO2 layer, and a SiC ( Silicon carbide) layer. The thickness of the SiO2 layer is 1 μm or more and 20 μm or less.

Description

本発明は、SiC(炭化シリコン)層を備えた半導体装置に関する。   The present invention relates to a semiconductor device provided with a SiC (silicon carbide) layer.

SiCは、Si(シリコン)に比べてバンドギャップが大きく、高い絶縁破壊電界強度を有している。このため、SiCは、高耐圧を有する半導体装置の材料として期待されている。また、3C−SiC(3C型の結晶構造を有するSiC)は、GaN(窒化ガリウム)との格子定数が近いことから、GaNを成長させるための下地基板として使用することができる。GaNの絶縁破壊電界強度は3C−SiCの絶縁破壊電界よりも大きいため、3C−SiCをバッファ層とすることで、より高耐圧なGaNの半導体装置を実現することができる。   SiC has a larger band gap than Si (silicon), and has a high breakdown electric field strength. For this reason, SiC is expected as a material for a semiconductor device having a high breakdown voltage. 3C-SiC (SiC having a 3C type crystal structure) has a lattice constant close to that of GaN (gallium nitride), and thus can be used as a base substrate for growing GaN. Since the breakdown electric field strength of GaN is larger than the breakdown electric field of 3C-SiC, a GaN semiconductor device with higher breakdown voltage can be realized by using 3C-SiC as a buffer layer.

3C−SiC層を成長させるための下地基板としては、Si基板またはバルクのSiC基板が広く用いられている。このうちバルクのSiC基板は、現在のところ4インチ程度のものしか存在しておらず、大口径化が困難であるという問題を有している。安価で大口径のワイドギャップ半導体を得るためには、Si基板を用いることが好ましい。   As a base substrate for growing a 3C—SiC layer, a Si substrate or a bulk SiC substrate is widely used. Among these, only about 4 inches of bulk SiC substrates are present at present, and there is a problem that it is difficult to increase the diameter. In order to obtain an inexpensive and large-diameter wide gap semiconductor, it is preferable to use a Si substrate.

下記特許文献1〜3には、SiCを始めとするワイドギャップ半導体を用いた半導体装置に関する技術が開示されている。下記特許文献1には、立方晶{001}面を表面とする単結晶基板上に、エピタキシャル成長により2種類の元素A、Bからなる化合物単結晶(SiCやGaNなど)を成長させる方法が開示されている。この方法では、反位相領域境界面ならびに元素AおよびBに起因する積層欠陥を、表面に平行な<110>方向にそれぞれ等価に生じさせながら化合物単結晶を成長させる工程(I)と、工程(I)において生じた元素Aに起因する積層欠陥を、反位相領域境界面と会合消滅させる工程(II)と、工程(I)において生じた元素Bに起因する積層欠陥を、自己消滅させる工程(III)と、反位相領域境界を完全に会合消滅させる工程(IV)とを備えている。工程(IV)は、工程(II)および(III)と並行して、または工程(II)および(III)の後に行われる。   The following Patent Documents 1 to 3 disclose technologies related to semiconductor devices using wide gap semiconductors such as SiC. Patent Document 1 below discloses a method of growing a compound single crystal (SiC, GaN, etc.) composed of two kinds of elements A and B by epitaxial growth on a single crystal substrate having a cubic {001} plane as a surface. ing. In this method, the step (I) of growing a compound single crystal while causing the stacking fault caused by the antiphase region boundary surface and the elements A and B to be equivalently generated in the <110> direction parallel to the surface, The step (II) of causing the stacking fault caused by the element A generated in I) to associate and disappear with the antiphase region boundary surface, and the step of self-extinguishing the stacking fault caused by the element B generated in step (I) ( III) and a step (IV) of completely dissociating the antiphase region boundary. Step (IV) is performed in parallel with steps (II) and (III) or after steps (II) and (III).

下記特許文献2には、所定厚さの表面Si層と埋め込み絶縁層とを有するSi基板を準備し、上記Si基板を炭素系ガス雰囲気中で加熱して表面Si層を単結晶SiC層に変成させる単結晶SiC基板の製造方法が開示されている。この製造方法では、表面Si層を単結晶SiC層に変成させる際に、埋め込み絶縁層との界面近傍のSi層が、残存Si層として残される。埋め込み絶縁層は、1〜200nmの厚さを有するSiO2(酸化シリコン)よりなっており、SiC層は、100nm程度の厚さを有している。In Patent Document 2 below, a Si substrate having a surface Si layer and a buried insulating layer having a predetermined thickness is prepared, and the Si substrate is heated in a carbon-based gas atmosphere to transform the surface Si layer into a single crystal SiC layer. A method of manufacturing a single crystal SiC substrate is disclosed. In this manufacturing method, when the surface Si layer is transformed into a single crystal SiC layer, the Si layer near the interface with the buried insulating layer is left as a remaining Si layer. The buried insulating layer is made of SiO 2 (silicon oxide) having a thickness of 1 to 200 nm, and the SiC layer has a thickness of about 100 nm.

下記特許文献3には、SOI(Silicon On Insulator)基板と、SOI基板上に形成されたバッファ層としてのAlN(窒化アルミニウム)層と、AlN層上に形成されたチャネル層としてGaN層と、GaN層上に形成されたバリア層としてのAlGaN(窒化アルミニウムガリウム)層と、AlGaN層上に形成されたソース電極、ドレイン電極、およびゲート電極とを備えた半導体装置が開示されている。   In Patent Document 3 below, an SOI (Silicon On Insulator) substrate, an AlN (aluminum nitride) layer as a buffer layer formed on the SOI substrate, a GaN layer as a channel layer formed on the AlN layer, and GaN A semiconductor device including an AlGaN (aluminum gallium nitride) layer as a barrier layer formed on the layer and a source electrode, a drain electrode, and a gate electrode formed on the AlGaN layer is disclosed.

特開2011−84435号公報JP 2011-84435 A 特開2009−302097号公報JP 2009-302097 A 特開2008−34411号公報JP 2008-34411 A

SiCは、Siに比べて非常に高い絶縁破壊電界強度を有している。具体的には、Siの絶縁破壊電界強度は0.3MV/cmであり、3C−SiCの絶縁破壊電界強度は1.2MV/cmである。したがって、Si基板を下地基板としてSiC層を形成した構造を有する半導体装置において、縦方向(Si基板の主面の法線方向)の耐圧を向上するためには、SiC層の厚さを大きくすればよい。   SiC has a very high breakdown field strength compared to Si. Specifically, the breakdown field strength of Si is 0.3 MV / cm, and the breakdown field strength of 3C—SiC is 1.2 MV / cm. Therefore, in a semiconductor device having a structure in which a SiC layer is formed using a Si substrate as a base substrate, the thickness of the SiC layer should be increased in order to improve the breakdown voltage in the vertical direction (normal direction of the main surface of the Si substrate). That's fine.

しかし、Si基板を下地基板としてSiC層を形成した半導体装置では、格子定数や熱膨張係数が互いに異なるSiとSiCがヘテロ界面を構成しているため、SiC層の厚さのみを大きくした場合には、基板の変形やSiC層へのクラックの発生が起こりやすくなる。その結果、SiC層を厚くすることにより半導体装置の縦方向の耐圧を向上することには限界があった。   However, in a semiconductor device in which a SiC layer is formed using a Si substrate as a base substrate, Si and SiC having different lattice constants and thermal expansion coefficients constitute a heterointerface, so that only the thickness of the SiC layer is increased. Is liable to cause deformation of the substrate and occurrence of cracks in the SiC layer. As a result, there is a limit in improving the vertical breakdown voltage of the semiconductor device by increasing the thickness of the SiC layer.

なお、上記特許文献1の技術を用いてSiC層を形成した場合には、クラックの発生を抑止しつつ比較的厚いSiC層を形成することが可能であるが、工程が複雑化するのなどの問題があった。   In addition, when the SiC layer is formed using the technique disclosed in Patent Document 1, it is possible to form a relatively thick SiC layer while suppressing the occurrence of cracks, but the process becomes complicated. There was a problem.

本発明は、上記課題を解決するためのものであり、その目的は、半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高めることである。   The present invention is to solve the above-described problems, and an object thereof is to increase the vertical breakdown voltage of the semiconductor device while ensuring the quality of the semiconductor device.

本発明の一の局面に従う半導体装置は、Si基板と、Si基板の表面に形成されたSiO2層と、SiO2層の表面に形成されたSi層と、Si層の表面上に形成されたSiC層とを備え、SiO2層の厚さは、1μm以上20μm以下である。A semiconductor device according to one aspect of the present invention is formed on a surface of a Si substrate, a SiO 2 layer formed on the surface of the Si substrate, a Si layer formed on the surface of the SiO 2 layer, and a surface of the Si layer. A thickness of the SiO 2 layer is not less than 1 μm and not more than 20 μm.

上記半導体装置において好ましくは、SiC層は、3C−SiCであり、SiC層の厚さは、0.1μm以上3μm以下である。   In the semiconductor device, the SiC layer is preferably 3C—SiC, and the thickness of the SiC layer is not less than 0.1 μm and not more than 3 μm.

上記半導体装置において好ましくは、Si層の厚さは、5nm以上10nm以下である。   In the semiconductor device, the thickness of the Si layer is preferably 5 nm or more and 10 nm or less.

上記半導体装置において好ましくは、SiC層に形成された半導体素子をさらに備える。   Preferably, the semiconductor device further includes a semiconductor element formed in the SiC layer.

上記半導体装置において好ましくは、SiC層の表面上に形成された窒化物半導体層と、窒化物半導体層に形成された半導体素子とをさらに備える。   Preferably, the semiconductor device further includes a nitride semiconductor layer formed on the surface of the SiC layer, and a semiconductor element formed in the nitride semiconductor layer.

本発明によれば、半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高めることができる。   According to the present invention, it is possible to increase the vertical breakdown voltage of a semiconductor device while ensuring the quality of the semiconductor device.

本発明の第1の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 1st Embodiment of this invention. SiC層の厚さと、クラックの発生の有無およびSiC層の結晶性との関係を示す表である。It is a table | surface which shows the relationship between the thickness of a SiC layer, the presence or absence of generation | occurrence | production of a crack, and the crystallinity of a SiC layer. 基板のサイズおよびSiO2層の厚さと、基板の反り量Wtとの関係を示す表である。The thickness of the substrate size and SiO 2 layer is a table showing the relationship between the warpage amount Wt of the substrate. 本発明の第2の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第3の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 3rd Embodiment of this invention.

以下、本発明の実施の形態について、図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(第1の実施の形態)   (First embodiment)

図1は、本発明の第1の実施の形態における半導体装置の構成を示す断面図である。   FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.

図1を参照して、本実施の形態における半導体装置は、GaN−HEMT(High Electron Mobility Transistor)を含んでいる。半導体装置は、Si基板1と、SiO2層(埋め込みガラス層)2と、Si層3と、SiC層4と、GaN層5と、AlGaN層6と、ソース電極11およびドレイン電極12と、ゲート電極13とを備えている。GaN層5およびAlGaN層6は窒化物半導体層7を構成している。窒化物半導体層7にはHEMT(半導体素子の一例)が形成されている。Referring to FIG. 1, the semiconductor device in the present embodiment includes a GaN-HEMT (High Electron Mobility Transistor). The semiconductor device includes a Si substrate 1, a SiO 2 layer (embedded glass layer) 2, a Si layer 3, a SiC layer 4, a GaN layer 5, an AlGaN layer 6, a source electrode 11 and a drain electrode 12, and a gate. And an electrode 13. The GaN layer 5 and the AlGaN layer 6 constitute a nitride semiconductor layer 7. A HEMT (an example of a semiconductor element) is formed on the nitride semiconductor layer 7.

Si基板1はp型またはn型の導電型を有していてもよい。   The Si substrate 1 may have a p-type or n-type conductivity type.

SiO2層2は、Si基板1の表面に形成されている。SiO2層2の厚さは、1μm以上20μm以下である。SiO2層2の厚さは、1.2μm以上であることが好ましい。SiO2層2の厚さは、10μm以下であることが好ましく、5μm以下であることがより好ましい。The SiO 2 layer 2 is formed on the surface of the Si substrate 1. The thickness of the SiO 2 layer 2 is not less than 1 μm and not more than 20 μm. The thickness of the SiO 2 layer 2 is preferably 1.2 μm or more. The thickness of the SiO 2 layer 2 is preferably 10 μm or less, and more preferably 5 μm or less.

Si層3は、SiO2層2の表面に形成されている。Si層3の厚さは、5nm以上10nm以下であることが好ましい。なお、Si層3は、たとえばSi層3を構成するSiを酸化することでSiO2を形成し、このSiO2をエッチングすることにより、上記の範囲まで薄膜化されてもよい。The Si layer 3 is formed on the surface of the SiO 2 layer 2. The thickness of the Si layer 3 is preferably 5 nm or more and 10 nm or less. The Si layer 3 may be thinned to the above range by, for example, forming SiO 2 by oxidizing Si constituting the Si layer 3 and etching the SiO 2 .

Si基板1、SiO2層2、およびSi層3はSOI(Silicon On Insulator)基板を構成する。SiO2層2およびSi層3は、たとえば貼合せ法やSIMOX(Separation by IMplanted OXygen)法などを用いて形成される。The Si substrate 1, the SiO 2 layer 2, and the Si layer 3 constitute an SOI (Silicon On Insulator) substrate. The SiO 2 layer 2 and the Si layer 3 are formed using, for example, a bonding method or a SIMOX (Separation by IM planted Oxygen) method.

SiC層4は、Si層3の表面に形成されている。SiC層4は、たとえば3C−SiC、4H−SiC、または6H−SiCなどよりなっている。特に、SiC層4がSi基板1上にエピタキシャル成長されたものである場合、一般的に、SiC層4は3C−SiCよりなっている。この場合、SiC層4の厚さは、0.1μm以上であることが好ましく、0.5μm以上であることがより好ましい。またSiC層4の厚さは3μm以下であることが好ましく、2μm以下であることがより好ましい。   The SiC layer 4 is formed on the surface of the Si layer 3. The SiC layer 4 is made of, for example, 3C—SiC, 4H—SiC, or 6H—SiC. In particular, when the SiC layer 4 is epitaxially grown on the Si substrate 1, the SiC layer 4 is generally made of 3C—SiC. In this case, the thickness of the SiC layer 4 is preferably 0.1 μm or more, and more preferably 0.5 μm or more. The thickness of the SiC layer 4 is preferably 3 μm or less, more preferably 2 μm or less.

SiC層4は、Si層3の表面を炭化することで得られたSiCよりなる下地層上に、MBE(分子線エピタキシー)法、CVD(化学蒸着)法、またはLPE(液相エピタキシー)法などを用いて、SiCをホモエピタキシャル成長させることによって形成されてもよい。SiC層4は、Si層3の表面を炭化することのみによって形成されてもよい。さらに、SiC層4は、バッファ層を挟んでSi層3の表面上にSiCをヘテロエピタキシャル成長させることによって形成されてもよい。   The SiC layer 4 is an MBE (molecular beam epitaxy) method, a CVD (chemical vapor deposition) method, an LPE (liquid phase epitaxy) method, or the like on an underlying layer made of SiC obtained by carbonizing the surface of the Si layer 3. And may be formed by homoepitaxial growth of SiC. The SiC layer 4 may be formed only by carbonizing the surface of the Si layer 3. Furthermore, SiC layer 4 may be formed by heteroepitaxially growing SiC on the surface of Si layer 3 with the buffer layer interposed therebetween.

GaN層5は、SiC層4の表面に形成されている。GaN層5には不純物が導入されておらず、GaN層5はHEMTの電子走行層となる。   The GaN layer 5 is formed on the surface of the SiC layer 4. Impurities are not introduced into the GaN layer 5, and the GaN layer 5 becomes an electron transit layer of the HEMT.

AlGaN層6は、GaN層5の表面に形成されている。AlGaN層6はn型の導電型を有しており、HEMTの障壁層となる。AlGaN層6は、たとえばHVPE(水素化物気相エピタキシー)法、またはMOCVD(有機金属気相成長)法などにより形成される。   The AlGaN layer 6 is formed on the surface of the GaN layer 5. The AlGaN layer 6 has n-type conductivity and serves as a HEMT barrier layer. The AlGaN layer 6 is formed by, for example, the HVPE (hydride vapor phase epitaxy) method or the MOCVD (metal organic vapor phase epitaxy) method.

SiCとGaNとは格子定数が近似している。このためSiC層4は、GaN層5のバッファ層(下地層)としての役割を果たす。なお、GaN層5およびAlGaN層6は、SiC層4表面上に形成されればよく、SiC層4とGaN層5との間に、たとえばAlNよりなるバッファ層が形成されていてもよい。HEMTが形成される場合の窒化物半導体層は、第1の窒化物半導体層と、第1の窒化物半導体層の表面に形成され、第1の窒化物半導体層のバンドギャップよりも広いバンドギャップを有する第2の窒化物半導体層とを含んでいるものであればよく、GaNとAlGaNとの組合せ以外の窒化物半導体材料の組合せにより構成されていてもよい。   SiC and GaN have approximate lattice constants. For this reason, the SiC layer 4 serves as a buffer layer (underlying layer) of the GaN layer 5. Note that the GaN layer 5 and the AlGaN layer 6 may be formed on the surface of the SiC layer 4, and a buffer layer made of, for example, AlN may be formed between the SiC layer 4 and the GaN layer 5. When the HEMT is formed, the nitride semiconductor layer is formed on the first nitride semiconductor layer and the surface of the first nitride semiconductor layer, and has a wider band gap than the band gap of the first nitride semiconductor layer. As long as it includes a second nitride semiconductor layer having GaN, and may be formed of a combination of nitride semiconductor materials other than a combination of GaN and AlGaN.

ソース電極11およびドレイン電極12の各々は、窒化物半導体層7の表面に互いに間隔を空けて形成されている。ゲート電極13は、窒化物半導体層7の表面において、ソース電極11とドレイン電極12との間に形成されている。ソース電極11およびドレイン電極12の各々は、窒化物半導体層7にオーミック接触している。ゲート電極13は、窒化物半導体層7にショットキー接触している。ソース電極11およびドレイン電極12の各々は、たとえば、窒化物半導体層7側から順にTi(チタン)層およびAl(アルミニウム)層を積層した構造を有している。ゲート電極13は、たとえば、窒化物半導体層7側から順にNi(ニッケル)層およびAu(金)層を積層した構造を有している。ソース電極11、ドレイン電極12、およびゲート電極13の各々は、たとえば蒸着法、MOCVD法、またはスパッタ法などにより形成される。   Each of the source electrode 11 and the drain electrode 12 is formed on the surface of the nitride semiconductor layer 7 with a space therebetween. The gate electrode 13 is formed between the source electrode 11 and the drain electrode 12 on the surface of the nitride semiconductor layer 7. Each of the source electrode 11 and the drain electrode 12 is in ohmic contact with the nitride semiconductor layer 7. The gate electrode 13 is in Schottky contact with the nitride semiconductor layer 7. Each of the source electrode 11 and the drain electrode 12 has a structure in which, for example, a Ti (titanium) layer and an Al (aluminum) layer are stacked in this order from the nitride semiconductor layer 7 side. The gate electrode 13 has a structure in which, for example, a Ni (nickel) layer and an Au (gold) layer are stacked in this order from the nitride semiconductor layer 7 side. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed by, for example, an evaporation method, an MOCVD method, or a sputtering method.

なお、Si基板1の裏面の電位を固定するために、Si基板1の裏面1aと、ソース電極11またはドレイン電極12とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 may be electrically connected.

半導体装置を構成する各層の厚さは、分光エリプソメーターを用いて測定される。分光エリプソメーターは、偏光である入射光を測定対象に照射し、測定対象からの反射光を受光する。S偏光とP偏光とでは位相のズレや反射率の違いがあるため、反射光の偏光状態は、入射光の偏光状態とは異なるものになっている。この偏光状態の変化は、入射光の波長、入射角度、膜の光学定数、および膜厚などに依存する。分光エリプソメーターは、得られた反射光から、入射光の波長や入射角に基づいて膜の光学定数や膜厚を算出する。   The thickness of each layer constituting the semiconductor device is measured using a spectroscopic ellipsometer. The spectroscopic ellipsometer irradiates a measurement target with incident light that is polarized light, and receives reflected light from the measurement target. Since there is a phase shift or reflectance difference between S-polarized light and P-polarized light, the polarization state of the reflected light is different from the polarization state of the incident light. The change in the polarization state depends on the wavelength of incident light, the incident angle, the optical constant of the film, the film thickness, and the like. The spectroscopic ellipsometer calculates the optical constant and film thickness of the film from the obtained reflected light based on the wavelength and incident angle of the incident light.

本実施の形態の半導体装置の動作は次の通りである。ソース電極11は常に接地電位(基準となる電位)に保たれる。ゲート電極13に電圧が印加されていない状態では、GaN層5とAlGaN層6とのバンドギャップの差に起因して、AlGaN層6で発生した電子は、GaN層5におけるAlGaN層6とのヘテロ接合界面に集まり、二次元電子ガスを形成する。二次元電子ガスの形成に伴い、AlGaN層6内は、GaN層5とのヘテロ接合界面から図1中上方向に延びる空乏層と、ゲート電極13との接合界面から図1中下方向に延びる空乏層とで完全に空乏層化される。一方、ゲート電極13に正の電圧が印加されると、電界効果により二次元電子ガスの濃度が高くなる。その結果、ドレイン電極12に正の電圧が印加された場合には、ドレイン電極12からソース電極11へ電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The source electrode 11 is always kept at the ground potential (reference potential). When no voltage is applied to the gate electrode 13, electrons generated in the AlGaN layer 6 are heterogeneous with the AlGaN layer 6 in the GaN layer 5 due to the difference in band gap between the GaN layer 5 and the AlGaN layer 6. Collects at the bonding interface to form a two-dimensional electron gas. Along with the formation of the two-dimensional electron gas, the inside of the AlGaN layer 6 extends from the heterojunction interface with the GaN layer 5 upward in FIG. The depletion layer is completely depleted. On the other hand, when a positive voltage is applied to the gate electrode 13, the concentration of the two-dimensional electron gas increases due to the field effect. As a result, when a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

本実施の形態によれば、SiO2層2の厚さが1μm以上であることにより、SiC層4の厚みをクラックが発生しない程度の厚みとすることができると同時に、窒化物半導体層7にHEMTが形成された半導体装置の縦方向の耐圧を高めることができる。また、SiO2層2の厚さが20μm以下であることにより、Si基板1の反りを抑止することができる。その結果、HEMTを含む半導体装置の品質を確保しつつ、HEMTを含む半導体装置の縦方向の耐圧を高めることができる。これについて以下に詳細に説明する。According to the present embodiment, the thickness of the SiO 2 layer 2 is 1 μm or more, so that the thickness of the SiC layer 4 can be reduced to a level at which cracks do not occur. The breakdown voltage in the vertical direction of the semiconductor device in which the HEMT is formed can be increased. Further, when the thickness of the SiO 2 layer 2 is 20 μm or less, the warpage of the Si substrate 1 can be suppressed. As a result, the vertical breakdown voltage of the semiconductor device including the HEMT can be increased while ensuring the quality of the semiconductor device including the HEMT. This will be described in detail below.

理論上、SiO2の絶縁破壊電界強度は2〜8MV/cmである。つまり、SiO2層の厚さが1μm増加するに従って、半導体装置の縦方向の耐圧は200〜800Vだけ増加する。また、理論上、3C型のSiCの絶縁破壊電界強度は1.2MV/cmである。つまり、SiC層の厚さが1μm増加するに従って、半導体装置の縦方向の耐圧は120Vだけ増加する。Theoretically, the dielectric breakdown electric field strength of SiO 2 is 2 to 8 MV / cm. That is, as the thickness of the SiO 2 layer increases by 1 μm, the vertical breakdown voltage of the semiconductor device increases by 200 to 800V. Theoretically, the dielectric breakdown electric field strength of 3C type SiC is 1.2 MV / cm. That is, the vertical breakdown voltage of the semiconductor device increases by 120V as the thickness of the SiC layer increases by 1 μm.

一般的に、パワーデバイスとしての半導体装置においては、半導体装置におけるSi基板を除く部分で、560V程度の縦方向の耐圧が要求されている。しかし、SiC層の厚みを大きくしすぎると、SiC層にクラックが発生しやすくなる。   Generally, in a semiconductor device as a power device, a vertical breakdown voltage of about 560 V is required in a portion excluding the Si substrate in the semiconductor device. However, if the thickness of the SiC layer is too large, cracks are likely to occur in the SiC layer.

本願発明者らは、SiC層の厚さと、クラックの発生の有無およびSiC層の結晶性との関係について調べた。図2は、SiC層の厚さと、クラックの発生の有無およびSiC層の結晶性との関係を示す表である。   The inventors of the present application investigated the relationship between the thickness of the SiC layer, the presence or absence of cracks, and the crystallinity of the SiC layer. FIG. 2 is a table showing the relationship between the thickness of the SiC layer, the presence / absence of cracks, and the crystallinity of the SiC layer.

図2を参照して、SiC層の厚さを3μm以下、好ましくは2μm以下とすることで、クラックの発生を抑止することができる。一方、SiC層4の厚さを0.1μm以上、好ましくは0.5μm以上とすることで、SiC層4の結晶性を確保することができる。   Referring to FIG. 2, the occurrence of cracks can be suppressed by setting the thickness of the SiC layer to 3 μm or less, preferably 2 μm or less. On the other hand, the crystallinity of the SiC layer 4 can be ensured by setting the thickness of the SiC layer 4 to 0.1 μm or more, preferably 0.5 μm or more.

SiC層の厚さを3μm以下にした場合、SiC層の縦方向の耐圧は理論上、360V以下となる。SiO2の絶縁破壊電界強度を考慮すると、SiO2層の厚さを1μm以上、好ましくは1.2μm以上とすることで、パワーデバイスとしての半導体装置に要求される縦方向の耐圧を確保することができる。When the thickness of the SiC layer is 3 μm or less, the longitudinal breakdown voltage of the SiC layer is theoretically 360 V or less. In view of the breakdown field strength of SiO 2, the thickness of the SiO 2 layer 1μm or more, preferably by a 1.2μm or more, to ensure the vertical breakdown voltage required for a semiconductor device as a power device Can do.

また本願発明者らは、Si基板のサイズおよびSiO2層の厚さと、Si基板の反り量との関係について調べた。図3は、Si基板のサイズおよびSiO2層の厚さと、Si基板の反り量Wtとの関係を示す表である。The inventors of the present application also examined the relationship between the Si substrate size and SiO 2 layer thickness and the amount of warpage of the Si substrate. FIG. 3 is a table showing the relationship between the size of the Si substrate and the thickness of the SiO 2 layer, and the warpage amount Wt of the Si substrate.

図3を参照して、直径8インチ、厚さ725μmの基板(試料1)、直径8インチ、厚さ1500μmの基板(試料2)、および直径6インチ、厚さ1500μmの基板(試料3)という3種類のSi基板を準備した。試料1〜3の各々に対して、0.5μmより大きく5μm以下の厚さのSiO2層、5μmより大きく10μm以下の厚さのSiO2層、10μmより大きく20μm以下の厚さのSiO2層、および20μmより大きい厚さのSiO2層をそれぞれ形成した。SiO2層形成後のSi基板の反り量Wtを測定した。Referring to FIG. 3, a substrate having a diameter of 8 inches and a thickness of 725 μm (sample 1), a substrate having a diameter of 8 inches and a thickness of 1500 μm (sample 2), and a substrate having a diameter of 6 inches and a thickness of 1500 μm (sample 3). Three types of Si substrates were prepared. For each of the samples 1 to 3, increased 5 [mu] m thick or less SiO 2 layer from 0.5 [mu] m, greater 10 [mu] m thick or less SiO 2 layer than 5 [mu] m, the SiO 2 layer of a thickness of less than greater than 10 [mu] m 20 [mu] m , And a SiO 2 layer having a thickness greater than 20 μm. The warpage amount Wt of the Si substrate after the formation of the SiO 2 layer was measured.

その結果、20μmより大きい厚さのSiO2層を形成した場合には、試料1〜3のいずれにおいても反り量の影響が大きかった。10μmより大きく20μm以下の厚さのSiO2層を形成した場合には、試料1および2では反り量の影響が大きかった一方、試料3では反り量の影響がほとんど無かった。5μmより大きく10μm以下の厚さのSiO2層を形成した場合には、試料1では反り量の影響が大きかった一方、試料2および3では反り量の影響がほとんど無かった。0.5μmより大きく5μm以下の厚さのSiO2層を形成した場合には、試料1〜3のいずれにおいても反り量の影響がほとんど無かった。As a result, when the SiO 2 layer having a thickness larger than 20 μm was formed, the influence of the warpage amount was great in any of samples 1 to 3. When an SiO 2 layer having a thickness greater than 10 μm and not more than 20 μm was formed, Samples 1 and 2 had a large influence on the amount of warpage, whereas Sample 3 had almost no influence on the amount of warp. When an SiO 2 layer having a thickness greater than 5 μm and less than or equal to 10 μm was formed, Sample 1 had a large influence on the amount of warpage, while Samples 2 and 3 had almost no influence on the amount of warpage. When an SiO 2 layer having a thickness of 0.5 μm or more and 5 μm or less was formed, there was almost no influence of the warpage amount in any of Samples 1 to 3.

以上の結果から、SiO2層の厚さを20μm以下、好ましくは10μm以下、より好ましくは5μm以下とすることで、基板の反りを抑止することができる。From the above results, the warp of the substrate can be suppressed by setting the thickness of the SiO 2 layer to 20 μm or less, preferably 10 μm or less, more preferably 5 μm or less.

加えて本実施の形態によれば、SiC層4が窒化物半導体層7のバッファ層としての役割を果たすので、高品質な窒化物半導体層7を形成することができる。   In addition, according to the present embodiment, since SiC layer 4 serves as a buffer layer for nitride semiconductor layer 7, high-quality nitride semiconductor layer 7 can be formed.

[第2の実施の形態]   [Second Embodiment]

図4は、本発明の第2の実施の形態における半導体装置の構成を示す断面図である。   FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention.

図4を参照して、本実施の形態における半導体装置は、SBD(Schottky Barrier Diode)を含んでいる。半導体装置は、Si基板1と、SiO2層2と、Si層3と、SiC層4と、オーミック電極14およびショットキー電極15とを備えている。SiC層4にはSBD(半導体素子の一例)が形成されている。SiO2層2、Si層3、およびSiC層4の各々の厚みは、第1の実施の形態と場合と同様である。半導体装置は窒化物半導体層を備えていない。Referring to FIG. 4, the semiconductor device according to the present embodiment includes an SBD (Schottky Barrier Diode). The semiconductor device includes a Si substrate 1, a SiO 2 layer 2, a Si layer 3, a SiC layer 4, an ohmic electrode 14 and a Schottky electrode 15. In the SiC layer 4, SBD (an example of a semiconductor element) is formed. The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that in the first embodiment. The semiconductor device does not include a nitride semiconductor layer.

SiC層4はn型の導電型を有している。SiC層4をn型化する不純物としては、たとえばN(窒素)、P(リン)、およびAs(砒素)のうち少なくとも1種類のものを用いることができる。   SiC layer 4 has n-type conductivity. As an impurity that makes SiC layer 4 n-type, for example, at least one of N (nitrogen), P (phosphorus), and As (arsenic) can be used.

オーミック電極14およびショットキー電極15の各々は、SiC層4の表面に互いに間隔を空けて形成されている。SiC層4がn型の導電型を有する場合、オーミック電極14は、たとえばNiまたはAlなどよりなっている。ショットキー電極15は、たとえばAu、Pt(白金)、またはAl−Ti合金などよりなっている。オーミック電極14およびショットキー電極15は、たとえば蒸着法、MOCVD法、またはスパッタ法などにより形成される。   Each of ohmic electrode 14 and Schottky electrode 15 is formed on the surface of SiC layer 4 at a distance from each other. When SiC layer 4 has n-type conductivity, ohmic electrode 14 is made of, for example, Ni or Al. The Schottky electrode 15 is made of, for example, Au, Pt (platinum), or an Al—Ti alloy. The ohmic electrode 14 and the Schottky electrode 15 are formed by, for example, vapor deposition, MOCVD, or sputtering.

なお、Si基板1の裏面の電位を固定するために、Si基板1の裏面1aと、オーミック電極14またはショットキー電極15とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the ohmic electrode 14 or the Schottky electrode 15 may be electrically connected.

上述以外の半導体装置の構成は、図1に示す第1の実施の形態の構成と同様であるので、同一の部材には同一の符号を付し、その説明は繰り返さない。   Since the configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals, and description thereof will not be repeated.

本実施の形態の半導体装置の動作は次の通りである。オーミック電極14は常に接地電位(基準となる電位)に保たれる。ショットキー電極15に電圧が印加されていない状態、またはショットキー電極15に負の電圧が印加されている状態では、逆方向バイアスとなり、SBDに電流は流れない。一方、ショットキー電極15に正の電圧が印加されている状態では、順方向バイアスとなり、ショットキー電極15からオーミック電極14に電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The ohmic electrode 14 is always kept at the ground potential (reference potential). When no voltage is applied to the Schottky electrode 15 or when a negative voltage is applied to the Schottky electrode 15, a reverse bias is applied, and no current flows through the SBD. On the other hand, when a positive voltage is applied to the Schottky electrode 15, a forward bias is applied, and a current flows from the Schottky electrode 15 to the ohmic electrode 14.

本実施の形態によれば、SBDを含む半導体装置の品質を確保しつつ、SBDを含む半導体装置の縦方向の耐圧を高めることができる。   According to the present embodiment, the vertical breakdown voltage of the semiconductor device including the SBD can be increased while ensuring the quality of the semiconductor device including the SBD.

なお、SiC層4はp型の導電型を有していてもよい。SiC層4をp型化する不純物としては、たとえばB(ホウ素)、Al、Ga(ガリウム)、およびIn(インジウム)のうち少なくとも1種類のものを用いることができる。SiC層4がp型の導電型を有する場合、オーミック電極14は、たとえばAu、Pt、またはAl−Ti合金などで形成される。ショットキー電極15は、たとえばNiまたはAlなどで形成される。   SiC layer 4 may have p-type conductivity. For example, at least one of B (boron), Al, Ga (gallium), and In (indium) can be used as an impurity for making the SiC layer 4 p-type. When SiC layer 4 has a p-type conductivity type, ohmic electrode 14 is formed of, for example, Au, Pt, or an Al—Ti alloy. Schottky electrode 15 is made of, for example, Ni or Al.

[第3の実施の形態]   [Third Embodiment]

図5は、本発明の第3の実施の形態における半導体装置の構成を示す断面図である。   FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention.

図5を参照して、本実施の形態における半導体装置は、n型MOSFET(Metal−Oxide−Semiconductor Field−Effect Transistor)を含んでいる。半導体装置は、Si基板1と、SiO2層2と、Si層3と、SiC層4と、不純物領域8aおよび8bと、ソース電極11およびドレイン電極12と、ゲート電極13とを備えている。SiC層4にはn型MOSFET(半導体素子の一例)が形成されている。SiO2層2、Si層3、およびSiC層4の各々の厚みは、第1の実施の形態と場合と同様である。半導体装置は窒化物半導体層を備えていない。Referring to FIG. 5, the semiconductor device in the present embodiment includes an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device includes a Si substrate 1, a SiO 2 layer 2, a Si layer 3, a SiC layer 4, impurity regions 8 a and 8 b, a source electrode 11 and a drain electrode 12, and a gate electrode 13. In the SiC layer 4, an n-type MOSFET (an example of a semiconductor element) is formed. The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that in the first embodiment. The semiconductor device does not include a nitride semiconductor layer.

SiC層4はn型の導電型を有している。不純物領域8aおよび8bの各々は、p型の導電型を有しており、SiC層4の表面に互いに間隔を開けて形成されている。不純物領域8aおよび8bはイオン注入法や熱拡散法などによって形成される。不純物領域8aおよび8bをp型化するための不純物としては、たとえばB、Al、Ga、およびInのうち少なくとも1種類のものを用いることができる。   SiC layer 4 has n-type conductivity. Impurity regions 8a and 8b each have a p-type conductivity type, and are formed on the surface of SiC layer 4 at a distance from each other. Impurity regions 8a and 8b are formed by ion implantation or thermal diffusion. As an impurity for making the impurity regions 8a and 8b p-type, for example, at least one of B, Al, Ga, and In can be used.

ソース電極11およびドレイン電極12の各々は、不純物領域8aおよび8bの各々の表面に形成されている。ゲート電極13は、不純物領域8aと不純物領域8bとの間のSiC層4の表面に、ゲート絶縁層16を挟んで形成されている。ゲート電極13およびゲート絶縁層16は、ソース電極11とドレイン電極12との間に形成されている。ソース電極11、ドレイン電極12、およびゲート電極13の各々は、AlまたはCu(銅)などよりなっている。ゲート絶縁層16は、たとえばSiO2よりなっている。ゲート絶縁層16は、Hf(ハフニウム)、Zr(ジルコニウム)、Al、またはTiなどの各酸化物や、これらのシリケイト化合物よりなっていてもよい。ソース電極11、ドレイン電極12、およびゲート電極13の各々は、たとえば蒸着法、MOCVD法、またはスパッタ法などにより形成される。ゲート絶縁層16は、たとえばプラズマCVD法などにより形成される。Each of source electrode 11 and drain electrode 12 is formed on the surface of each of impurity regions 8a and 8b. The gate electrode 13 is formed on the surface of the SiC layer 4 between the impurity region 8a and the impurity region 8b with the gate insulating layer 16 interposed therebetween. The gate electrode 13 and the gate insulating layer 16 are formed between the source electrode 11 and the drain electrode 12. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is made of Al or Cu (copper). The gate insulating layer 16 is made of, for example, SiO 2 . The gate insulating layer 16 may be made of an oxide such as Hf (hafnium), Zr (zirconium), Al, or Ti, or a silicate compound thereof. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed by, for example, an evaporation method, an MOCVD method, or a sputtering method. The gate insulating layer 16 is formed by, for example, a plasma CVD method.

なお、Si基板1の裏面の電位を固定するために、Si基板1の裏面1aと、ソース電極11またはドレイン電極12とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 may be electrically connected.

上述以外の半導体装置の構成は、図1に示す第1の実施の形態の構成と同様であるので、同一の部材には同一の符号を付し、その説明は繰り返さない。   Since the configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals, and description thereof will not be repeated.

本実施の形態の半導体装置の動作は次の通りである。ソース電極11は常に接地電位(基準となる電位)に保たれる。ゲート電極13に電圧が印加されていない状態、またはゲート電極13に負の電圧が印加されている状態では、ソース電極11とドレイン電極12との間には電流は流れない。一方、ゲート電極13に正の電圧が印加されると、SiC層4内に存在する電子が、ゲート絶縁層16との界面を構成するSiC層4の表面に引き寄せられ、不純物領域8aと不純物領域8aとの間にn型の反転層を形成する。その結果、ドレイン電極12に正の電圧が印加された場合には、ドレイン電極12からソース電極11へ電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The source electrode 11 is always kept at the ground potential (reference potential). In the state where no voltage is applied to the gate electrode 13 or the state where a negative voltage is applied to the gate electrode 13, no current flows between the source electrode 11 and the drain electrode 12. On the other hand, when a positive voltage is applied to gate electrode 13, electrons present in SiC layer 4 are attracted to the surface of SiC layer 4 constituting the interface with gate insulating layer 16, and impurity region 8a and impurity region An n-type inversion layer is formed between 8a and 8a. As a result, when a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

本実施の形態によれば、MOSFETを含む半導体装置の品質を確保しつつ、MOSFETを含む半導体装置の縦方向の耐圧を高めることができる。   According to the present embodiment, the vertical breakdown voltage of the semiconductor device including the MOSFET can be increased while ensuring the quality of the semiconductor device including the MOSFET.

なお、半導体装置はp型MOSFETを含んでいてもよい。この場合、SiC層4はp型の導電型とされ、不純物領域8aおよび8bはn型の導電型とされる。不純物領域8aおよび8bをn型化するための不純物としては、たとえばN、P、およびAsのうち少なくとも1種類のものを用いることができる。   Note that the semiconductor device may include a p-type MOSFET. In this case, SiC layer 4 is of p-type conductivity, and impurity regions 8a and 8b are of n-type conductivity. As an impurity for making the impurity regions 8a and 8b n-type, for example, at least one of N, P, and As can be used.

[その他]   [Others]

半導体装置に形成される半導体素子は任意のものであればよく、たとえばダイオード、トランジスタ、サイリスタ、または半導体レーザーなどであってもよい。半導体素子は横型のもの(SiO2層の表面上に形成された層での電気伝導により動作するもの)であることが好ましい。Any semiconductor element may be formed in the semiconductor device, for example, a diode, a transistor, a thyristor, or a semiconductor laser. The semiconductor element is preferably of a lateral type (operated by electrical conduction in a layer formed on the surface of the SiO 2 layer).

上述の実施の形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The above-described embodiment is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Si(シリコン)基板
1a Si基板の裏面
2 SiO2(酸化シリコン)層
3 Si層
4 SiC(炭化シリコン)層
5 GaN(窒化ガリウム)層
6 AlGaN(窒化アルミニウムガリウム)層
7 窒化物半導体層
8a,8b 不純物領域
11 ソース電極
12 ドレイン電極
13 ゲート電極
14 オーミック電極
15 ショットキー電極
16 ゲート絶縁層
1 Si (silicon) substrate 1a Si substrate of the back 2 SiO 2 (silicon oxide) layer 3 Si layer 4 SiC (silicon carbide) layer 5 GaN (gallium nitride) layer 6 AlGaN (aluminum gallium nitride) layer 7 nitride semiconductor layer 8a 8b Impurity region 11 Source electrode 12 Drain electrode 13 Gate electrode 14 Ohmic electrode 15 Schottky electrode 16 Gate insulating layer

Claims (5)

シリコン基板と、
前記シリコン基板の表面に形成された酸化シリコン層と、
前記酸化シリコン層の表面に形成されたシリコン層と、
前記シリコン層の表面上に形成された炭化シリコン層とを備え、
前記酸化シリコン層の厚さは、1μm以上20μm以下である、半導体装置。
A silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A silicon layer formed on the surface of the silicon oxide layer;
A silicon carbide layer formed on the surface of the silicon layer,
The semiconductor device, wherein the silicon oxide layer has a thickness of 1 μm to 20 μm.
前記炭化シリコン層は、3C−SiCであり、
前記炭化シリコン層の厚さは、0.1μm以上3μm以下である、請求項1に記載の半導体装置。
The silicon carbide layer is 3C-SiC;
The semiconductor device according to claim 1, wherein a thickness of the silicon carbide layer is not less than 0.1 μm and not more than 3 μm.
前記シリコン層の厚さは、5nm以上10nm以下である、請求項1に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thickness of the silicon layer is not less than 5 nm and not more than 10 nm. 前記炭化シリコン層に形成された半導体素子をさらに備えた、請求項1に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a semiconductor element formed in the silicon carbide layer. 前記炭化シリコン層の表面上に形成された窒化物半導体層と、
前記窒化物半導体層に形成された半導体素子とをさらに備えた、請求項1に記載の半導体装置。
A nitride semiconductor layer formed on a surface of the silicon carbide layer;
The semiconductor device according to claim 1, further comprising a semiconductor element formed in the nitride semiconductor layer.
JP2016550139A 2014-09-24 2015-09-16 Semiconductor device provided with SiC layer Pending JPWO2016047534A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014193781 2014-09-24
JP2014193781 2014-09-24
PCT/JP2015/076364 WO2016047534A1 (en) 2014-09-24 2015-09-16 SEMICONDUCTOR DEVICE EQUIPPED WITH SiC LAYER

Publications (1)

Publication Number Publication Date
JPWO2016047534A1 true JPWO2016047534A1 (en) 2017-07-27

Family

ID=55581061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016550139A Pending JPWO2016047534A1 (en) 2014-09-24 2015-09-16 Semiconductor device provided with SiC layer

Country Status (3)

Country Link
JP (1) JPWO2016047534A1 (en)
TW (1) TWI680504B (en)
WO (1) WO2016047534A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563428A (en) * 1995-01-30 1996-10-08 Ek; Bruce A. Layered structure of a substrate, a dielectric layer and a single crystal layer
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
JP3920103B2 (en) * 2002-01-31 2007-05-30 大阪府 Insulating layer embedded type semiconductor silicon carbide substrate manufacturing method and manufacturing apparatus thereof
JP4802624B2 (en) * 2005-09-07 2011-10-26 信越半導体株式会社 Manufacturing method of bonded SOI wafer
KR20110015009A (en) * 2008-06-10 2011-02-14 에어 워터 가부시키가이샤 Method for manufacturing nitrogen compound semiconductor substrate, nitrogen compound semiconductor substrate, method for manufacturing single crystal sic substrate, and single crystal sic substrate
JP2011029594A (en) * 2009-06-22 2011-02-10 Shin Etsu Handotai Co Ltd Method of manufacturing soi wafer, and soi wafer

Also Published As

Publication number Publication date
TWI680504B (en) 2019-12-21
TW201628070A (en) 2016-08-01
WO2016047534A1 (en) 2016-03-31

Similar Documents

Publication Publication Date Title
US8415690B2 (en) Epitaxial substrate for semiconductor element, semiconductor element, and method for producing epitaxial substrate for semiconductor element
US10566450B2 (en) Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof
JP4525894B2 (en) Semiconductor device forming plate-like substrate, manufacturing method thereof, and semiconductor device using the same
TWI712075B (en) Compound semiconductor substrate
US20150349064A1 (en) Nucleation and buffer layers for group iii-nitride based semiconductor devices
JP2011166067A (en) Nitride semiconductor device
CN104126223A (en) Semiconductor element and method for manufacturing semiconductor element
JP6649208B2 (en) Semiconductor device
TWI641133B (en) Semiconductor cell
JP2009206163A (en) Heterojunction-type field effect transistor
US8405067B2 (en) Nitride semiconductor element
US10332975B2 (en) Epitaxial substrate for semiconductor device and method for manufacturing same
TWI569439B (en) Semiconductor cell
JP2007250727A (en) Field effect transistor
US10381471B2 (en) Semiconductor device and manufacturing method
KR101027138B1 (en) Nitride based semiconductor device employing dlc passivation and method for fabricating the same
JP6553336B2 (en) Semiconductor device
CN114496788A (en) P-type channel gallium nitride transistor and preparation method thereof
WO2016047534A1 (en) SEMICONDUCTOR DEVICE EQUIPPED WITH SiC LAYER
US10158012B1 (en) Semiconductor device
KR20210082523A (en) Compound semiconductor device, compound semiconductor substrate, and method for manufacturing compound semiconductor device
US20230015133A1 (en) Semi-conductor structure and manufacturing method thereof
JP7231826B2 (en) Semiconductor device, method for manufacturing semiconductor device, and electronic device
JP6781293B2 (en) Semiconductor device
JP2024015771A (en) Semiconductor device

Legal Events

Date Code Title Description
AA64 Notification of invalidation of claim of internal priority (with term)

Free format text: JAPANESE INTERMEDIATE CODE: A241764

Effective date: 20170530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170602

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180809

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191008

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200114

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200310

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200324

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200622

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20200622

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20200630

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20200707

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20200717

C211 Notice of termination of reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C211

Effective date: 20200721

C22 Notice of designation (change) of administrative judge

Free format text: JAPANESE INTERMEDIATE CODE: C22

Effective date: 20201117

C23 Notice of termination of proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C23

Effective date: 20210316

C03 Trial/appeal decision taken

Free format text: JAPANESE INTERMEDIATE CODE: C03

Effective date: 20210427

C30A Notification sent

Free format text: JAPANESE INTERMEDIATE CODE: C3012

Effective date: 20210427