JPWO2016047534A1 - Semiconductor device provided with SiC layer - Google Patents

Semiconductor device provided with SiC layer Download PDF

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JPWO2016047534A1
JPWO2016047534A1 JP2016550139A JP2016550139A JPWO2016047534A1 JP WO2016047534 A1 JPWO2016047534 A1 JP WO2016047534A1 JP 2016550139 A JP2016550139 A JP 2016550139A JP 2016550139 A JP2016550139 A JP 2016550139A JP WO2016047534 A1 JPWO2016047534 A1 JP WO2016047534A1
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英俊 浅村
英俊 浅村
川村　啓介
啓介 川村
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Abstract

半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高める。半導体装置は、Ｓｉ（シリコン）基板と、Ｓｉ基板の表面に形成されたＳｉＯ2（酸化シリコン）層と、ＳｉＯ2層の表面に形成されたＳｉ層と、Ｓｉ層の表面上に形成されたＳｉＣ（炭化シリコン）層とを備えている。ＳｉＯ2層の厚さは、１μｍ以上２０μｍ以下である。The vertical breakdown voltage of the semiconductor device is increased while ensuring the quality of the semiconductor device. The semiconductor device includes a Si (silicon) substrate, a SiO2 (silicon oxide) layer formed on the surface of the Si substrate, a Si layer formed on the surface of the SiO2 layer, and a SiC ( Silicon carbide) layer. The thickness of the SiO2 layer is 1 μm or more and 20 μm or less.

Description

本発明は、ＳｉＣ（炭化シリコン）層を備えた半導体装置に関する。   The present invention relates to a semiconductor device provided with a SiC (silicon carbide) layer.

ＳｉＣは、Ｓｉ（シリコン）に比べてバンドギャップが大きく、高い絶縁破壊電界強度を有している。このため、ＳｉＣは、高耐圧を有する半導体装置の材料として期待されている。また、３Ｃ−ＳｉＣ（３Ｃ型の結晶構造を有するＳｉＣ）は、ＧａＮ（窒化ガリウム）との格子定数が近いことから、ＧａＮを成長させるための下地基板として使用することができる。ＧａＮの絶縁破壊電界強度は３Ｃ−ＳｉＣの絶縁破壊電界よりも大きいため、３Ｃ−ＳｉＣをバッファ層とすることで、より高耐圧なＧａＮの半導体装置を実現することができる。   SiC has a larger band gap than Si (silicon), and has a high breakdown electric field strength. For this reason, SiC is expected as a material for a semiconductor device having a high breakdown voltage. 3C-SiC (SiC having a 3C type crystal structure) has a lattice constant close to that of GaN (gallium nitride), and thus can be used as a base substrate for growing GaN. Since the breakdown electric field strength of GaN is larger than the breakdown electric field of 3C-SiC, a GaN semiconductor device with higher breakdown voltage can be realized by using 3C-SiC as a buffer layer.

３Ｃ−ＳｉＣ層を成長させるための下地基板としては、Ｓｉ基板またはバルクのＳｉＣ基板が広く用いられている。このうちバルクのＳｉＣ基板は、現在のところ４インチ程度のものしか存在しておらず、大口径化が困難であるという問題を有している。安価で大口径のワイドギャップ半導体を得るためには、Ｓｉ基板を用いることが好ましい。   As a base substrate for growing a 3C—SiC layer, a Si substrate or a bulk SiC substrate is widely used. Among these, only about 4 inches of bulk SiC substrates are present at present, and there is a problem that it is difficult to increase the diameter. In order to obtain an inexpensive and large-diameter wide gap semiconductor, it is preferable to use a Si substrate.

下記特許文献１〜３には、ＳｉＣを始めとするワイドギャップ半導体を用いた半導体装置に関する技術が開示されている。下記特許文献１には、立方晶｛００１｝面を表面とする単結晶基板上に、エピタキシャル成長により２種類の元素Ａ、Ｂからなる化合物単結晶（ＳｉＣやＧａＮなど）を成長させる方法が開示されている。この方法では、反位相領域境界面ならびに元素ＡおよびＢに起因する積層欠陥を、表面に平行な＜１１０＞方向にそれぞれ等価に生じさせながら化合物単結晶を成長させる工程（Ｉ）と、工程（Ｉ）において生じた元素Ａに起因する積層欠陥を、反位相領域境界面と会合消滅させる工程（ＩＩ）と、工程（Ｉ）において生じた元素Ｂに起因する積層欠陥を、自己消滅させる工程（ＩＩＩ）と、反位相領域境界を完全に会合消滅させる工程（ＩＶ）とを備えている。工程（ＩＶ）は、工程（ＩＩ）および（ＩＩＩ）と並行して、または工程（ＩＩ）および（ＩＩＩ）の後に行われる。   The following Patent Documents 1 to 3 disclose technologies related to semiconductor devices using wide gap semiconductors such as SiC. Patent Document 1 below discloses a method of growing a compound single crystal (SiC, GaN, etc.) composed of two kinds of elements A and B by epitaxial growth on a single crystal substrate having a cubic {001} plane as a surface. ing. In this method, the step (I) of growing a compound single crystal while causing the stacking fault caused by the antiphase region boundary surface and the elements A and B to be equivalently generated in the <110> direction parallel to the surface, The step (II) of causing the stacking fault caused by the element A generated in I) to associate and disappear with the antiphase region boundary surface, and the step of self-extinguishing the stacking fault caused by the element B generated in step (I) ( III) and a step (IV) of completely dissociating the antiphase region boundary. Step (IV) is performed in parallel with steps (II) and (III) or after steps (II) and (III).

下記特許文献２には、所定厚さの表面Ｓｉ層と埋め込み絶縁層とを有するＳｉ基板を準備し、上記Ｓｉ基板を炭素系ガス雰囲気中で加熱して表面Ｓｉ層を単結晶ＳｉＣ層に変成させる単結晶ＳｉＣ基板の製造方法が開示されている。この製造方法では、表面Ｓｉ層を単結晶ＳｉＣ層に変成させる際に、埋め込み絶縁層との界面近傍のＳｉ層が、残存Ｓｉ層として残される。埋め込み絶縁層は、１〜２００ｎｍの厚さを有するＳｉＯ2（酸化シリコン）よりなっており、ＳｉＣ層は、１００ｎｍ程度の厚さを有している。In Patent Document 2 below, a Si substrate having a surface Si layer and a buried insulating layer having a predetermined thickness is prepared, and the Si substrate is heated in a carbon-based gas atmosphere to transform the surface Si layer into a single crystal SiC layer. A method of manufacturing a single crystal SiC substrate is disclosed. In this manufacturing method, when the surface Si layer is transformed into a single crystal SiC layer, the Si layer near the interface with the buried insulating layer is left as a remaining Si layer. The buried insulating layer is made of SiO 2 (silicon oxide) having a thickness of 1 to 200 nm, and the SiC layer has a thickness of about 100 nm.

下記特許文献３には、ＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板と、ＳＯＩ基板上に形成されたバッファ層としてのＡｌＮ（窒化アルミニウム）層と、ＡｌＮ層上に形成されたチャネル層としてＧａＮ層と、ＧａＮ層上に形成されたバリア層としてのＡｌＧａＮ（窒化アルミニウムガリウム）層と、ＡｌＧａＮ層上に形成されたソース電極、ドレイン電極、およびゲート電極とを備えた半導体装置が開示されている。   In Patent Document 3 below, an SOI (Silicon On Insulator) substrate, an AlN (aluminum nitride) layer as a buffer layer formed on the SOI substrate, a GaN layer as a channel layer formed on the AlN layer, and GaN A semiconductor device including an AlGaN (aluminum gallium nitride) layer as a barrier layer formed on the layer and a source electrode, a drain electrode, and a gate electrode formed on the AlGaN layer is disclosed.

特開２０１１−８４４３５号公報JP 2011-84435 A 特開２００９−３０２０９７号公報JP 2009-302097 A 特開２００８−３４４１１号公報JP 2008-34411 A

ＳｉＣは、Ｓｉに比べて非常に高い絶縁破壊電界強度を有している。具体的には、Ｓｉの絶縁破壊電界強度は０．３ＭＶ／ｃｍであり、３Ｃ−ＳｉＣの絶縁破壊電界強度は１．２ＭＶ／ｃｍである。したがって、Ｓｉ基板を下地基板としてＳｉＣ層を形成した構造を有する半導体装置において、縦方向（Ｓｉ基板の主面の法線方向）の耐圧を向上するためには、ＳｉＣ層の厚さを大きくすればよい。   SiC has a very high breakdown field strength compared to Si. Specifically, the breakdown field strength of Si is 0.3 MV / cm, and the breakdown field strength of 3C—SiC is 1.2 MV / cm. Therefore, in a semiconductor device having a structure in which a SiC layer is formed using a Si substrate as a base substrate, the thickness of the SiC layer should be increased in order to improve the breakdown voltage in the vertical direction (normal direction of the main surface of the Si substrate). That's fine.

しかし、Ｓｉ基板を下地基板としてＳｉＣ層を形成した半導体装置では、格子定数や熱膨張係数が互いに異なるＳｉとＳｉＣがヘテロ界面を構成しているため、ＳｉＣ層の厚さのみを大きくした場合には、基板の変形やＳｉＣ層へのクラックの発生が起こりやすくなる。その結果、ＳｉＣ層を厚くすることにより半導体装置の縦方向の耐圧を向上することには限界があった。   However, in a semiconductor device in which a SiC layer is formed using a Si substrate as a base substrate, Si and SiC having different lattice constants and thermal expansion coefficients constitute a heterointerface, so that only the thickness of the SiC layer is increased. Is liable to cause deformation of the substrate and occurrence of cracks in the SiC layer. As a result, there is a limit in improving the vertical breakdown voltage of the semiconductor device by increasing the thickness of the SiC layer.

なお、上記特許文献１の技術を用いてＳｉＣ層を形成した場合には、クラックの発生を抑止しつつ比較的厚いＳｉＣ層を形成することが可能であるが、工程が複雑化するのなどの問題があった。   In addition, when the SiC layer is formed using the technique disclosed in Patent Document 1, it is possible to form a relatively thick SiC layer while suppressing the occurrence of cracks, but the process becomes complicated. There was a problem.

本発明は、上記課題を解決するためのものであり、その目的は、半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高めることである。   The present invention is to solve the above-described problems, and an object thereof is to increase the vertical breakdown voltage of the semiconductor device while ensuring the quality of the semiconductor device.

本発明の一の局面に従う半導体装置は、Ｓｉ基板と、Ｓｉ基板の表面に形成されたＳｉＯ2層と、ＳｉＯ2層の表面に形成されたＳｉ層と、Ｓｉ層の表面上に形成されたＳｉＣ層とを備え、ＳｉＯ2層の厚さは、１μｍ以上２０μｍ以下である。A semiconductor device according to one aspect of the present invention is formed on a surface of a Si substrate, a SiO 2 layer formed on the surface of the Si substrate, a Si layer formed on the surface of the SiO 2 layer, and a surface of the Si layer. A thickness of the SiO 2 layer is not less than 1 μm and not more than 20 μm.

上記半導体装置において好ましくは、ＳｉＣ層は、３Ｃ−ＳｉＣであり、ＳｉＣ層の厚さは、０．１μｍ以上３μｍ以下である。   In the semiconductor device, the SiC layer is preferably 3C—SiC, and the thickness of the SiC layer is not less than 0.1 μm and not more than 3 μm.

上記半導体装置において好ましくは、Ｓｉ層の厚さは、５ｎｍ以上１０ｎｍ以下である。   In the semiconductor device, the thickness of the Si layer is preferably 5 nm or more and 10 nm or less.

上記半導体装置において好ましくは、ＳｉＣ層に形成された半導体素子をさらに備える。   Preferably, the semiconductor device further includes a semiconductor element formed in the SiC layer.

上記半導体装置において好ましくは、ＳｉＣ層の表面上に形成された窒化物半導体層と、窒化物半導体層に形成された半導体素子とをさらに備える。   Preferably, the semiconductor device further includes a nitride semiconductor layer formed on the surface of the SiC layer, and a semiconductor element formed in the nitride semiconductor layer.

本発明によれば、半導体装置の品質を確保しつつ、半導体装置の縦方向の耐圧を高めることができる。   According to the present invention, it is possible to increase the vertical breakdown voltage of a semiconductor device while ensuring the quality of the semiconductor device.

本発明の第１の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 1st Embodiment of this invention. ＳｉＣ層の厚さと、クラックの発生の有無およびＳｉＣ層の結晶性との関係を示す表である。It is a table | surface which shows the relationship between the thickness of a SiC layer, the presence or absence of generation | occurrence | production of a crack, and the crystallinity of a SiC layer. 基板のサイズおよびＳｉＯ2層の厚さと、基板の反り量Ｗｔとの関係を示す表である。The thickness of the substrate size and SiO 2 layer is a table showing the relationship between the warpage amount Wt of the substrate. 本発明の第２の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第３の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in the 3rd Embodiment of this invention.

以下、本発明の実施の形態について、図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（第１の実施の形態）   (First embodiment)

図１は、本発明の第１の実施の形態における半導体装置の構成を示す断面図である。   FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.

図１を参照して、本実施の形態における半導体装置は、ＧａＮ−ＨＥＭＴ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ）を含んでいる。半導体装置は、Ｓｉ基板１と、ＳｉＯ2層（埋め込みガラス層）２と、Ｓｉ層３と、ＳｉＣ層４と、ＧａＮ層５と、ＡｌＧａＮ層６と、ソース電極１１およびドレイン電極１２と、ゲート電極１３とを備えている。ＧａＮ層５およびＡｌＧａＮ層６は窒化物半導体層７を構成している。窒化物半導体層７にはＨＥＭＴ（半導体素子の一例）が形成されている。Referring to FIG. 1, the semiconductor device in the present embodiment includes a GaN-HEMT (High Electron Mobility Transistor). The semiconductor device includes a Si substrate 1, a SiO 2 layer (embedded glass layer) 2, a Si layer 3, a SiC layer 4, a GaN layer 5, an AlGaN layer 6, a source electrode 11 and a drain electrode 12, and a gate. And an electrode 13. The GaN layer 5 and the AlGaN layer 6 constitute a nitride semiconductor layer 7. A HEMT (an example of a semiconductor element) is formed on the nitride semiconductor layer 7.

Ｓｉ基板１はｐ型またはｎ型の導電型を有していてもよい。   The Si substrate 1 may have a p-type or n-type conductivity type.

ＳｉＯ2層２は、Ｓｉ基板１の表面に形成されている。ＳｉＯ2層２の厚さは、１μｍ以上２０μｍ以下である。ＳｉＯ2層２の厚さは、１．２μｍ以上であることが好ましい。ＳｉＯ2層２の厚さは、１０μｍ以下であることが好ましく、５μｍ以下であることがより好ましい。The SiO 2 layer 2 is formed on the surface of the Si substrate 1. The thickness of the SiO 2 layer 2 is not less than 1 μm and not more than 20 μm. The thickness of the SiO 2 layer 2 is preferably 1.2 μm or more. The thickness of the SiO 2 layer 2 is preferably 10 μm or less, and more preferably 5 μm or less.

Ｓｉ層３は、ＳｉＯ2層２の表面に形成されている。Ｓｉ層３の厚さは、５ｎｍ以上１０ｎｍ以下であることが好ましい。なお、Ｓｉ層３は、たとえばＳｉ層３を構成するＳｉを酸化することでＳｉＯ2を形成し、このＳｉＯ2をエッチングすることにより、上記の範囲まで薄膜化されてもよい。The Si layer 3 is formed on the surface of the SiO 2 layer 2. The thickness of the Si layer 3 is preferably 5 nm or more and 10 nm or less. The Si layer 3 may be thinned to the above range by, for example, forming SiO 2 by oxidizing Si constituting the Si layer 3 and etching the SiO 2 .

Ｓｉ基板１、ＳｉＯ2層２、およびＳｉ層３はＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板を構成する。ＳｉＯ2層２およびＳｉ層３は、たとえば貼合せ法やＳＩＭＯＸ（Ｓｅｐａｒａｔｉｏｎ ｂｙ ＩＭｐｌａｎｔｅｄ ＯＸｙｇｅｎ）法などを用いて形成される。The Si substrate 1, the SiO 2 layer 2, and the Si layer 3 constitute an SOI (Silicon On Insulator) substrate. The SiO 2 layer 2 and the Si layer 3 are formed using, for example, a bonding method or a SIMOX (Separation by IM planted Oxygen) method.

ＳｉＣ層４は、Ｓｉ層３の表面に形成されている。ＳｉＣ層４は、たとえば３Ｃ−ＳｉＣ、４Ｈ−ＳｉＣ、または６Ｈ−ＳｉＣなどよりなっている。特に、ＳｉＣ層４がＳｉ基板１上にエピタキシャル成長されたものである場合、一般的に、ＳｉＣ層４は３Ｃ−ＳｉＣよりなっている。この場合、ＳｉＣ層４の厚さは、０．１μｍ以上であることが好ましく、０．５μｍ以上であることがより好ましい。またＳｉＣ層４の厚さは３μｍ以下であることが好ましく、２μｍ以下であることがより好ましい。   The SiC layer 4 is formed on the surface of the Si layer 3. The SiC layer 4 is made of, for example, 3C—SiC, 4H—SiC, or 6H—SiC. In particular, when the SiC layer 4 is epitaxially grown on the Si substrate 1, the SiC layer 4 is generally made of 3C—SiC. In this case, the thickness of the SiC layer 4 is preferably 0.1 μm or more, and more preferably 0.5 μm or more. The thickness of the SiC layer 4 is preferably 3 μm or less, more preferably 2 μm or less.

ＳｉＣ層４は、Ｓｉ層３の表面を炭化することで得られたＳｉＣよりなる下地層上に、ＭＢＥ（分子線エピタキシー）法、ＣＶＤ（化学蒸着）法、またはＬＰＥ（液相エピタキシー）法などを用いて、ＳｉＣをホモエピタキシャル成長させることによって形成されてもよい。ＳｉＣ層４は、Ｓｉ層３の表面を炭化することのみによって形成されてもよい。さらに、ＳｉＣ層４は、バッファ層を挟んでＳｉ層３の表面上にＳｉＣをヘテロエピタキシャル成長させることによって形成されてもよい。   The SiC layer 4 is an MBE (molecular beam epitaxy) method, a CVD (chemical vapor deposition) method, an LPE (liquid phase epitaxy) method, or the like on an underlying layer made of SiC obtained by carbonizing the surface of the Si layer 3. And may be formed by homoepitaxial growth of SiC. The SiC layer 4 may be formed only by carbonizing the surface of the Si layer 3. Furthermore, SiC layer 4 may be formed by heteroepitaxially growing SiC on the surface of Si layer 3 with the buffer layer interposed therebetween.

ＧａＮ層５は、ＳｉＣ層４の表面に形成されている。ＧａＮ層５には不純物が導入されておらず、ＧａＮ層５はＨＥＭＴの電子走行層となる。   The GaN layer 5 is formed on the surface of the SiC layer 4. Impurities are not introduced into the GaN layer 5, and the GaN layer 5 becomes an electron transit layer of the HEMT.

ＡｌＧａＮ層６は、ＧａＮ層５の表面に形成されている。ＡｌＧａＮ層６はｎ型の導電型を有しており、ＨＥＭＴの障壁層となる。ＡｌＧａＮ層６は、たとえばＨＶＰＥ（水素化物気相エピタキシー）法、またはＭＯＣＶＤ（有機金属気相成長）法などにより形成される。   The AlGaN layer 6 is formed on the surface of the GaN layer 5. The AlGaN layer 6 has n-type conductivity and serves as a HEMT barrier layer. The AlGaN layer 6 is formed by, for example, the HVPE (hydride vapor phase epitaxy) method or the MOCVD (metal organic vapor phase epitaxy) method.

ＳｉＣとＧａＮとは格子定数が近似している。このためＳｉＣ層４は、ＧａＮ層５のバッファ層（下地層）としての役割を果たす。なお、ＧａＮ層５およびＡｌＧａＮ層６は、ＳｉＣ層４表面上に形成されればよく、ＳｉＣ層４とＧａＮ層５との間に、たとえばＡｌＮよりなるバッファ層が形成されていてもよい。ＨＥＭＴが形成される場合の窒化物半導体層は、第１の窒化物半導体層と、第１の窒化物半導体層の表面に形成され、第１の窒化物半導体層のバンドギャップよりも広いバンドギャップを有する第２の窒化物半導体層とを含んでいるものであればよく、ＧａＮとＡｌＧａＮとの組合せ以外の窒化物半導体材料の組合せにより構成されていてもよい。   SiC and GaN have approximate lattice constants. For this reason, the SiC layer 4 serves as a buffer layer (underlying layer) of the GaN layer 5. Note that the GaN layer 5 and the AlGaN layer 6 may be formed on the surface of the SiC layer 4, and a buffer layer made of, for example, AlN may be formed between the SiC layer 4 and the GaN layer 5. When the HEMT is formed, the nitride semiconductor layer is formed on the first nitride semiconductor layer and the surface of the first nitride semiconductor layer, and has a wider band gap than the band gap of the first nitride semiconductor layer. As long as it includes a second nitride semiconductor layer having GaN, and may be formed of a combination of nitride semiconductor materials other than a combination of GaN and AlGaN.

ソース電極１１およびドレイン電極１２の各々は、窒化物半導体層７の表面に互いに間隔を空けて形成されている。ゲート電極１３は、窒化物半導体層７の表面において、ソース電極１１とドレイン電極１２との間に形成されている。ソース電極１１およびドレイン電極１２の各々は、窒化物半導体層７にオーミック接触している。ゲート電極１３は、窒化物半導体層７にショットキー接触している。ソース電極１１およびドレイン電極１２の各々は、たとえば、窒化物半導体層７側から順にＴｉ（チタン）層およびＡｌ（アルミニウム）層を積層した構造を有している。ゲート電極１３は、たとえば、窒化物半導体層７側から順にＮｉ（ニッケル）層およびＡｕ（金）層を積層した構造を有している。ソース電極１１、ドレイン電極１２、およびゲート電極１３の各々は、たとえば蒸着法、ＭＯＣＶＤ法、またはスパッタ法などにより形成される。   Each of the source electrode 11 and the drain electrode 12 is formed on the surface of the nitride semiconductor layer 7 with a space therebetween. The gate electrode 13 is formed between the source electrode 11 and the drain electrode 12 on the surface of the nitride semiconductor layer 7. Each of the source electrode 11 and the drain electrode 12 is in ohmic contact with the nitride semiconductor layer 7. The gate electrode 13 is in Schottky contact with the nitride semiconductor layer 7. Each of the source electrode 11 and the drain electrode 12 has a structure in which, for example, a Ti (titanium) layer and an Al (aluminum) layer are stacked in this order from the nitride semiconductor layer 7 side. The gate electrode 13 has a structure in which, for example, a Ni (nickel) layer and an Au (gold) layer are stacked in this order from the nitride semiconductor layer 7 side. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed by, for example, an evaporation method, an MOCVD method, or a sputtering method.

なお、Ｓｉ基板１の裏面の電位を固定するために、Ｓｉ基板１の裏面１ａと、ソース電極１１またはドレイン電極１２とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 may be electrically connected.

半導体装置を構成する各層の厚さは、分光エリプソメーターを用いて測定される。分光エリプソメーターは、偏光である入射光を測定対象に照射し、測定対象からの反射光を受光する。Ｓ偏光とＰ偏光とでは位相のズレや反射率の違いがあるため、反射光の偏光状態は、入射光の偏光状態とは異なるものになっている。この偏光状態の変化は、入射光の波長、入射角度、膜の光学定数、および膜厚などに依存する。分光エリプソメーターは、得られた反射光から、入射光の波長や入射角に基づいて膜の光学定数や膜厚を算出する。   The thickness of each layer constituting the semiconductor device is measured using a spectroscopic ellipsometer. The spectroscopic ellipsometer irradiates a measurement target with incident light that is polarized light, and receives reflected light from the measurement target. Since there is a phase shift or reflectance difference between S-polarized light and P-polarized light, the polarization state of the reflected light is different from the polarization state of the incident light. The change in the polarization state depends on the wavelength of incident light, the incident angle, the optical constant of the film, the film thickness, and the like. The spectroscopic ellipsometer calculates the optical constant and film thickness of the film from the obtained reflected light based on the wavelength and incident angle of the incident light.

本実施の形態の半導体装置の動作は次の通りである。ソース電極１１は常に接地電位（基準となる電位）に保たれる。ゲート電極１３に電圧が印加されていない状態では、ＧａＮ層５とＡｌＧａＮ層６とのバンドギャップの差に起因して、ＡｌＧａＮ層６で発生した電子は、ＧａＮ層５におけるＡｌＧａＮ層６とのヘテロ接合界面に集まり、二次元電子ガスを形成する。二次元電子ガスの形成に伴い、ＡｌＧａＮ層６内は、ＧａＮ層５とのヘテロ接合界面から図１中上方向に延びる空乏層と、ゲート電極１３との接合界面から図１中下方向に延びる空乏層とで完全に空乏層化される。一方、ゲート電極１３に正の電圧が印加されると、電界効果により二次元電子ガスの濃度が高くなる。その結果、ドレイン電極１２に正の電圧が印加された場合には、ドレイン電極１２からソース電極１１へ電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The source electrode 11 is always kept at the ground potential (reference potential). When no voltage is applied to the gate electrode 13, electrons generated in the AlGaN layer 6 are heterogeneous with the AlGaN layer 6 in the GaN layer 5 due to the difference in band gap between the GaN layer 5 and the AlGaN layer 6. Collects at the bonding interface to form a two-dimensional electron gas. Along with the formation of the two-dimensional electron gas, the inside of the AlGaN layer 6 extends from the heterojunction interface with the GaN layer 5 upward in FIG. The depletion layer is completely depleted. On the other hand, when a positive voltage is applied to the gate electrode 13, the concentration of the two-dimensional electron gas increases due to the field effect. As a result, when a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

本実施の形態によれば、ＳｉＯ2層２の厚さが１μｍ以上であることにより、ＳｉＣ層４の厚みをクラックが発生しない程度の厚みとすることができると同時に、窒化物半導体層７にＨＥＭＴが形成された半導体装置の縦方向の耐圧を高めることができる。また、ＳｉＯ2層２の厚さが２０μｍ以下であることにより、Ｓｉ基板１の反りを抑止することができる。その結果、ＨＥＭＴを含む半導体装置の品質を確保しつつ、ＨＥＭＴを含む半導体装置の縦方向の耐圧を高めることができる。これについて以下に詳細に説明する。According to the present embodiment, the thickness of the SiO 2 layer 2 is 1 μm or more, so that the thickness of the SiC layer 4 can be reduced to a level at which cracks do not occur. The breakdown voltage in the vertical direction of the semiconductor device in which the HEMT is formed can be increased. Further, when the thickness of the SiO 2 layer 2 is 20 μm or less, the warpage of the Si substrate 1 can be suppressed. As a result, the vertical breakdown voltage of the semiconductor device including the HEMT can be increased while ensuring the quality of the semiconductor device including the HEMT. This will be described in detail below.

理論上、ＳｉＯ2の絶縁破壊電界強度は２〜８ＭＶ／ｃｍである。つまり、ＳｉＯ2層の厚さが１μｍ増加するに従って、半導体装置の縦方向の耐圧は２００〜８００Ｖだけ増加する。また、理論上、３Ｃ型のＳｉＣの絶縁破壊電界強度は１．２ＭＶ／ｃｍである。つまり、ＳｉＣ層の厚さが１μｍ増加するに従って、半導体装置の縦方向の耐圧は１２０Ｖだけ増加する。Theoretically, the dielectric breakdown electric field strength of SiO 2 is 2 to 8 MV / cm. That is, as the thickness of the SiO 2 layer increases by 1 μm, the vertical breakdown voltage of the semiconductor device increases by 200 to 800V. Theoretically, the dielectric breakdown electric field strength of 3C type SiC is 1.2 MV / cm. That is, the vertical breakdown voltage of the semiconductor device increases by 120V as the thickness of the SiC layer increases by 1 μm.

一般的に、パワーデバイスとしての半導体装置においては、半導体装置におけるＳｉ基板を除く部分で、５６０Ｖ程度の縦方向の耐圧が要求されている。しかし、ＳｉＣ層の厚みを大きくしすぎると、ＳｉＣ層にクラックが発生しやすくなる。   Generally, in a semiconductor device as a power device, a vertical breakdown voltage of about 560 V is required in a portion excluding the Si substrate in the semiconductor device. However, if the thickness of the SiC layer is too large, cracks are likely to occur in the SiC layer.

本願発明者らは、ＳｉＣ層の厚さと、クラックの発生の有無およびＳｉＣ層の結晶性との関係について調べた。図２は、ＳｉＣ層の厚さと、クラックの発生の有無およびＳｉＣ層の結晶性との関係を示す表である。   The inventors of the present application investigated the relationship between the thickness of the SiC layer, the presence or absence of cracks, and the crystallinity of the SiC layer. FIG. 2 is a table showing the relationship between the thickness of the SiC layer, the presence / absence of cracks, and the crystallinity of the SiC layer.

図２を参照して、ＳｉＣ層の厚さを３μｍ以下、好ましくは２μｍ以下とすることで、クラックの発生を抑止することができる。一方、ＳｉＣ層４の厚さを０．１μｍ以上、好ましくは０．５μｍ以上とすることで、ＳｉＣ層４の結晶性を確保することができる。   Referring to FIG. 2, the occurrence of cracks can be suppressed by setting the thickness of the SiC layer to 3 μm or less, preferably 2 μm or less. On the other hand, the crystallinity of the SiC layer 4 can be ensured by setting the thickness of the SiC layer 4 to 0.1 μm or more, preferably 0.5 μm or more.

ＳｉＣ層の厚さを３μｍ以下にした場合、ＳｉＣ層の縦方向の耐圧は理論上、３６０Ｖ以下となる。ＳｉＯ2の絶縁破壊電界強度を考慮すると、ＳｉＯ2層の厚さを１μｍ以上、好ましくは１．２μｍ以上とすることで、パワーデバイスとしての半導体装置に要求される縦方向の耐圧を確保することができる。When the thickness of the SiC layer is 3 μm or less, the longitudinal breakdown voltage of the SiC layer is theoretically 360 V or less. In view of the breakdown field strength of SiO 2, the thickness of the SiO 2 layer 1μm or more, preferably by a 1.2μm or more, to ensure the vertical breakdown voltage required for a semiconductor device as a power device Can do.

また本願発明者らは、Ｓｉ基板のサイズおよびＳｉＯ2層の厚さと、Ｓｉ基板の反り量との関係について調べた。図３は、Ｓｉ基板のサイズおよびＳｉＯ2層の厚さと、Ｓｉ基板の反り量Ｗｔとの関係を示す表である。The inventors of the present application also examined the relationship between the Si substrate size and SiO 2 layer thickness and the amount of warpage of the Si substrate. FIG. 3 is a table showing the relationship between the size of the Si substrate and the thickness of the SiO 2 layer, and the warpage amount Wt of the Si substrate.

図３を参照して、直径８インチ、厚さ７２５μｍの基板（試料１）、直径８インチ、厚さ１５００μｍの基板（試料２）、および直径６インチ、厚さ１５００μｍの基板（試料３）という３種類のＳｉ基板を準備した。試料１〜３の各々に対して、０．５μｍより大きく５μｍ以下の厚さのＳｉＯ2層、５μｍより大きく１０μｍ以下の厚さのＳｉＯ2層、１０μｍより大きく２０μｍ以下の厚さのＳｉＯ2層、および２０μｍより大きい厚さのＳｉＯ2層をそれぞれ形成した。ＳｉＯ2層形成後のＳｉ基板の反り量Ｗｔを測定した。Referring to FIG. 3, a substrate having a diameter of 8 inches and a thickness of 725 μm (sample 1), a substrate having a diameter of 8 inches and a thickness of 1500 μm (sample 2), and a substrate having a diameter of 6 inches and a thickness of 1500 μm (sample 3). Three types of Si substrates were prepared. For each of the samples 1 to 3, increased 5 [mu] m thick or less SiO 2 layer from 0.5 [mu] m, greater 10 [mu] m thick or less SiO 2 layer than 5 [mu] m, the SiO 2 layer of a thickness of less than greater than 10 [mu] m 20 [mu] m , And a SiO 2 layer having a thickness greater than 20 μm. The warpage amount Wt of the Si substrate after the formation of the SiO 2 layer was measured.

その結果、２０μｍより大きい厚さのＳｉＯ2層を形成した場合には、試料１〜３のいずれにおいても反り量の影響が大きかった。１０μｍより大きく２０μｍ以下の厚さのＳｉＯ2層を形成した場合には、試料１および２では反り量の影響が大きかった一方、試料３では反り量の影響がほとんど無かった。５μｍより大きく１０μｍ以下の厚さのＳｉＯ2層を形成した場合には、試料１では反り量の影響が大きかった一方、試料２および３では反り量の影響がほとんど無かった。０．５μｍより大きく５μｍ以下の厚さのＳｉＯ2層を形成した場合には、試料１〜３のいずれにおいても反り量の影響がほとんど無かった。As a result, when the SiO 2 layer having a thickness larger than 20 μm was formed, the influence of the warpage amount was great in any of samples 1 to 3. When an SiO 2 layer having a thickness greater than 10 μm and not more than 20 μm was formed, Samples 1 and 2 had a large influence on the amount of warpage, whereas Sample 3 had almost no influence on the amount of warp. When an SiO 2 layer having a thickness greater than 5 μm and less than or equal to 10 μm was formed, Sample 1 had a large influence on the amount of warpage, while Samples 2 and 3 had almost no influence on the amount of warpage. When an SiO 2 layer having a thickness of 0.5 μm or more and 5 μm or less was formed, there was almost no influence of the warpage amount in any of Samples 1 to 3.

以上の結果から、ＳｉＯ2層の厚さを２０μｍ以下、好ましくは１０μｍ以下、より好ましくは５μｍ以下とすることで、基板の反りを抑止することができる。From the above results, the warp of the substrate can be suppressed by setting the thickness of the SiO 2 layer to 20 μm or less, preferably 10 μm or less, more preferably 5 μm or less.

加えて本実施の形態によれば、ＳｉＣ層４が窒化物半導体層７のバッファ層としての役割を果たすので、高品質な窒化物半導体層７を形成することができる。   In addition, according to the present embodiment, since SiC layer 4 serves as a buffer layer for nitride semiconductor layer 7, high-quality nitride semiconductor layer 7 can be formed.

［第２の実施の形態］   [Second Embodiment]

図４は、本発明の第２の実施の形態における半導体装置の構成を示す断面図である。   FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention.

図４を参照して、本実施の形態における半導体装置は、ＳＢＤ（Ｓｃｈｏｔｔｋｙ Ｂａｒｒｉｅｒ Ｄｉｏｄｅ）を含んでいる。半導体装置は、Ｓｉ基板１と、ＳｉＯ2層２と、Ｓｉ層３と、ＳｉＣ層４と、オーミック電極１４およびショットキー電極１５とを備えている。ＳｉＣ層４にはＳＢＤ（半導体素子の一例）が形成されている。ＳｉＯ2層２、Ｓｉ層３、およびＳｉＣ層４の各々の厚みは、第１の実施の形態と場合と同様である。半導体装置は窒化物半導体層を備えていない。Referring to FIG. 4, the semiconductor device according to the present embodiment includes an SBD (Schottky Barrier Diode). The semiconductor device includes a Si substrate 1, a SiO 2 layer 2, a Si layer 3, a SiC layer 4, an ohmic electrode 14 and a Schottky electrode 15. In the SiC layer 4, SBD (an example of a semiconductor element) is formed. The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that in the first embodiment. The semiconductor device does not include a nitride semiconductor layer.

ＳｉＣ層４はｎ型の導電型を有している。ＳｉＣ層４をｎ型化する不純物としては、たとえばＮ（窒素）、Ｐ（リン）、およびＡｓ（砒素）のうち少なくとも１種類のものを用いることができる。   SiC layer 4 has n-type conductivity. As an impurity that makes SiC layer 4 n-type, for example, at least one of N (nitrogen), P (phosphorus), and As (arsenic) can be used.

オーミック電極１４およびショットキー電極１５の各々は、ＳｉＣ層４の表面に互いに間隔を空けて形成されている。ＳｉＣ層４がｎ型の導電型を有する場合、オーミック電極１４は、たとえばＮｉまたはＡｌなどよりなっている。ショットキー電極１５は、たとえばＡｕ、Ｐｔ（白金）、またはＡｌ−Ｔｉ合金などよりなっている。オーミック電極１４およびショットキー電極１５は、たとえば蒸着法、ＭＯＣＶＤ法、またはスパッタ法などにより形成される。   Each of ohmic electrode 14 and Schottky electrode 15 is formed on the surface of SiC layer 4 at a distance from each other. When SiC layer 4 has n-type conductivity, ohmic electrode 14 is made of, for example, Ni or Al. The Schottky electrode 15 is made of, for example, Au, Pt (platinum), or an Al—Ti alloy. The ohmic electrode 14 and the Schottky electrode 15 are formed by, for example, vapor deposition, MOCVD, or sputtering.

なお、Ｓｉ基板１の裏面の電位を固定するために、Ｓｉ基板１の裏面１ａと、オーミック電極１４またはショットキー電極１５とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the ohmic electrode 14 or the Schottky electrode 15 may be electrically connected.

上述以外の半導体装置の構成は、図１に示す第１の実施の形態の構成と同様であるので、同一の部材には同一の符号を付し、その説明は繰り返さない。   Since the configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals, and description thereof will not be repeated.

本実施の形態の半導体装置の動作は次の通りである。オーミック電極１４は常に接地電位（基準となる電位）に保たれる。ショットキー電極１５に電圧が印加されていない状態、またはショットキー電極１５に負の電圧が印加されている状態では、逆方向バイアスとなり、ＳＢＤに電流は流れない。一方、ショットキー電極１５に正の電圧が印加されている状態では、順方向バイアスとなり、ショットキー電極１５からオーミック電極１４に電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The ohmic electrode 14 is always kept at the ground potential (reference potential). When no voltage is applied to the Schottky electrode 15 or when a negative voltage is applied to the Schottky electrode 15, a reverse bias is applied, and no current flows through the SBD. On the other hand, when a positive voltage is applied to the Schottky electrode 15, a forward bias is applied, and a current flows from the Schottky electrode 15 to the ohmic electrode 14.

本実施の形態によれば、ＳＢＤを含む半導体装置の品質を確保しつつ、ＳＢＤを含む半導体装置の縦方向の耐圧を高めることができる。   According to the present embodiment, the vertical breakdown voltage of the semiconductor device including the SBD can be increased while ensuring the quality of the semiconductor device including the SBD.

なお、ＳｉＣ層４はｐ型の導電型を有していてもよい。ＳｉＣ層４をｐ型化する不純物としては、たとえばＢ（ホウ素）、Ａｌ、Ｇａ（ガリウム）、およびＩｎ（インジウム）のうち少なくとも１種類のものを用いることができる。ＳｉＣ層４がｐ型の導電型を有する場合、オーミック電極１４は、たとえばＡｕ、Ｐｔ、またはＡｌ−Ｔｉ合金などで形成される。ショットキー電極１５は、たとえばＮｉまたはＡｌなどで形成される。   SiC layer 4 may have p-type conductivity. For example, at least one of B (boron), Al, Ga (gallium), and In (indium) can be used as an impurity for making the SiC layer 4 p-type. When SiC layer 4 has a p-type conductivity type, ohmic electrode 14 is formed of, for example, Au, Pt, or an Al—Ti alloy. Schottky electrode 15 is made of, for example, Ni or Al.

［第３の実施の形態］   [Third Embodiment]

図５は、本発明の第３の実施の形態における半導体装置の構成を示す断面図である。   FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention.

図５を参照して、本実施の形態における半導体装置は、ｎ型ＭＯＳＦＥＴ（Ｍｅｔａｌ−Ｏｘｉｄｅ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ−Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）を含んでいる。半導体装置は、Ｓｉ基板１と、ＳｉＯ2層２と、Ｓｉ層３と、ＳｉＣ層４と、不純物領域８ａおよび８ｂと、ソース電極１１およびドレイン電極１２と、ゲート電極１３とを備えている。ＳｉＣ層４にはｎ型ＭＯＳＦＥＴ（半導体素子の一例）が形成されている。ＳｉＯ2層２、Ｓｉ層３、およびＳｉＣ層４の各々の厚みは、第１の実施の形態と場合と同様である。半導体装置は窒化物半導体層を備えていない。Referring to FIG. 5, the semiconductor device in the present embodiment includes an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device includes a Si substrate 1, a SiO 2 layer 2, a Si layer 3, a SiC layer 4, impurity regions 8 a and 8 b, a source electrode 11 and a drain electrode 12, and a gate electrode 13. In the SiC layer 4, an n-type MOSFET (an example of a semiconductor element) is formed. The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that in the first embodiment. The semiconductor device does not include a nitride semiconductor layer.

ＳｉＣ層４はｎ型の導電型を有している。不純物領域８ａおよび８ｂの各々は、ｐ型の導電型を有しており、ＳｉＣ層４の表面に互いに間隔を開けて形成されている。不純物領域８ａおよび８ｂはイオン注入法や熱拡散法などによって形成される。不純物領域８ａおよび８ｂをｐ型化するための不純物としては、たとえばＢ、Ａｌ、Ｇａ、およびＩｎのうち少なくとも１種類のものを用いることができる。   SiC layer 4 has n-type conductivity. Impurity regions 8a and 8b each have a p-type conductivity type, and are formed on the surface of SiC layer 4 at a distance from each other. Impurity regions 8a and 8b are formed by ion implantation or thermal diffusion. As an impurity for making the impurity regions 8a and 8b p-type, for example, at least one of B, Al, Ga, and In can be used.

ソース電極１１およびドレイン電極１２の各々は、不純物領域８ａおよび８ｂの各々の表面に形成されている。ゲート電極１３は、不純物領域８ａと不純物領域８ｂとの間のＳｉＣ層４の表面に、ゲート絶縁層１６を挟んで形成されている。ゲート電極１３およびゲート絶縁層１６は、ソース電極１１とドレイン電極１２との間に形成されている。ソース電極１１、ドレイン電極１２、およびゲート電極１３の各々は、ＡｌまたはＣｕ（銅）などよりなっている。ゲート絶縁層１６は、たとえばＳｉＯ2よりなっている。ゲート絶縁層１６は、Ｈｆ（ハフニウム）、Ｚｒ（ジルコニウム）、Ａｌ、またはＴｉなどの各酸化物や、これらのシリケイト化合物よりなっていてもよい。ソース電極１１、ドレイン電極１２、およびゲート電極１３の各々は、たとえば蒸着法、ＭＯＣＶＤ法、またはスパッタ法などにより形成される。ゲート絶縁層１６は、たとえばプラズマＣＶＤ法などにより形成される。Each of source electrode 11 and drain electrode 12 is formed on the surface of each of impurity regions 8a and 8b. The gate electrode 13 is formed on the surface of the SiC layer 4 between the impurity region 8a and the impurity region 8b with the gate insulating layer 16 interposed therebetween. The gate electrode 13 and the gate insulating layer 16 are formed between the source electrode 11 and the drain electrode 12. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is made of Al or Cu (copper). The gate insulating layer 16 is made of, for example, SiO 2 . The gate insulating layer 16 may be made of an oxide such as Hf (hafnium), Zr (zirconium), Al, or Ti, or a silicate compound thereof. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed by, for example, an evaporation method, an MOCVD method, or a sputtering method. The gate insulating layer 16 is formed by, for example, a plasma CVD method.

なお、Ｓｉ基板１の裏面の電位を固定するために、Ｓｉ基板１の裏面１ａと、ソース電極１１またはドレイン電極１２とが電気的に接続されてもよい。   In order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 may be electrically connected.

上述以外の半導体装置の構成は、図１に示す第１の実施の形態の構成と同様であるので、同一の部材には同一の符号を付し、その説明は繰り返さない。   Since the configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals, and description thereof will not be repeated.

本実施の形態の半導体装置の動作は次の通りである。ソース電極１１は常に接地電位（基準となる電位）に保たれる。ゲート電極１３に電圧が印加されていない状態、またはゲート電極１３に負の電圧が印加されている状態では、ソース電極１１とドレイン電極１２との間には電流は流れない。一方、ゲート電極１３に正の電圧が印加されると、ＳｉＣ層４内に存在する電子が、ゲート絶縁層１６との界面を構成するＳｉＣ層４の表面に引き寄せられ、不純物領域８ａと不純物領域８ａとの間にｎ型の反転層を形成する。その結果、ドレイン電極１２に正の電圧が印加された場合には、ドレイン電極１２からソース電極１１へ電流が流れる。   The operation of the semiconductor device of this embodiment is as follows. The source electrode 11 is always kept at the ground potential (reference potential). In the state where no voltage is applied to the gate electrode 13 or the state where a negative voltage is applied to the gate electrode 13, no current flows between the source electrode 11 and the drain electrode 12. On the other hand, when a positive voltage is applied to gate electrode 13, electrons present in SiC layer 4 are attracted to the surface of SiC layer 4 constituting the interface with gate insulating layer 16, and impurity region 8a and impurity region An n-type inversion layer is formed between 8a and 8a. As a result, when a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

本実施の形態によれば、ＭＯＳＦＥＴを含む半導体装置の品質を確保しつつ、ＭＯＳＦＥＴを含む半導体装置の縦方向の耐圧を高めることができる。   According to the present embodiment, the vertical breakdown voltage of the semiconductor device including the MOSFET can be increased while ensuring the quality of the semiconductor device including the MOSFET.

なお、半導体装置はｐ型ＭＯＳＦＥＴを含んでいてもよい。この場合、ＳｉＣ層４はｐ型の導電型とされ、不純物領域８ａおよび８ｂはｎ型の導電型とされる。不純物領域８ａおよび８ｂをｎ型化するための不純物としては、たとえばＮ、Ｐ、およびＡｓのうち少なくとも１種類のものを用いることができる。   Note that the semiconductor device may include a p-type MOSFET. In this case, SiC layer 4 is of p-type conductivity, and impurity regions 8a and 8b are of n-type conductivity. As an impurity for making the impurity regions 8a and 8b n-type, for example, at least one of N, P, and As can be used.

［その他］   [Others]

半導体装置に形成される半導体素子は任意のものであればよく、たとえばダイオード、トランジスタ、サイリスタ、または半導体レーザーなどであってもよい。半導体素子は横型のもの（ＳｉＯ2層の表面上に形成された層での電気伝導により動作するもの）であることが好ましい。Any semiconductor element may be formed in the semiconductor device, for example, a diode, a transistor, a thyristor, or a semiconductor laser. The semiconductor element is preferably of a lateral type (operated by electrical conduction in a layer formed on the surface of the SiO 2 layer).

上述の実施の形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The above-described embodiment is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

１ Ｓｉ（シリコン）基板
１ａ Ｓｉ基板の裏面
２ ＳｉＯ2（酸化シリコン）層
３ Ｓｉ層
４ ＳｉＣ（炭化シリコン）層
５ ＧａＮ（窒化ガリウム）層
６ ＡｌＧａＮ（窒化アルミニウムガリウム）層
７ 窒化物半導体層
８ａ，８ｂ 不純物領域
１１ ソース電極
１２ ドレイン電極
１３ ゲート電極
１４ オーミック電極
１５ ショットキー電極
１６ ゲート絶縁層1 Si (silicon) substrate 1a Si substrate of the back 2 SiO 2 (silicon oxide) layer 3 Si layer 4 SiC (silicon carbide) layer 5 GaN (gallium nitride) layer 6 AlGaN (aluminum gallium nitride) layer 7 nitride semiconductor layer 8a 8b Impurity region 11 Source electrode 12 Drain electrode 13 Gate electrode 14 Ohmic electrode 15 Schottky electrode 16 Gate insulating layer

Claims (5)

シリコン基板と、
前記シリコン基板の表面に形成された酸化シリコン層と、
前記酸化シリコン層の表面に形成されたシリコン層と、
前記シリコン層の表面上に形成された炭化シリコン層とを備え、
前記酸化シリコン層の厚さは、１μｍ以上２０μｍ以下である、半導体装置。A silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A silicon layer formed on the surface of the silicon oxide layer;
A silicon carbide layer formed on the surface of the silicon layer,
The semiconductor device, wherein the silicon oxide layer has a thickness of 1 μm to 20 μm. 前記炭化シリコン層は、３Ｃ−ＳｉＣであり、
前記炭化シリコン層の厚さは、０．１μｍ以上３μｍ以下である、請求項１に記載の半導体装置。The silicon carbide layer is 3C-SiC;
The semiconductor device according to claim 1, wherein a thickness of the silicon carbide layer is not less than 0.1 μm and not more than 3 μm. 前記シリコン層の厚さは、５ｎｍ以上１０ｎｍ以下である、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thickness of the silicon layer is not less than 5 nm and not more than 10 nm. 前記炭化シリコン層に形成された半導体素子をさらに備えた、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a semiconductor element formed in the silicon carbide layer. 前記炭化シリコン層の表面上に形成された窒化物半導体層と、
前記窒化物半導体層に形成された半導体素子とをさらに備えた、請求項１に記載の半導体装置。A nitride semiconductor layer formed on a surface of the silicon carbide layer;
The semiconductor device according to claim 1, further comprising a semiconductor element formed in the nitride semiconductor layer.
JP2016550139A 2014-09-24 2015-09-16 Semiconductor device provided with SiC layer Pending JPWO2016047534A1 (en)

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