TW201628070A - Semiconductor device equipped with SiC layer - Google Patents

Semiconductor device equipped with SiC layer Download PDF

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TW201628070A
TW201628070A TW104131147A TW104131147A TW201628070A TW 201628070 A TW201628070 A TW 201628070A TW 104131147 A TW104131147 A TW 104131147A TW 104131147 A TW104131147 A TW 104131147A TW 201628070 A TW201628070 A TW 201628070A
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semiconductor device
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TWI680504B (en
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Hidetoshi Asamura
Keisuke Kawamura
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Air Water Inc
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Abstract

The present invention increases pressure resistance in the longitudinal direction of a semiconductor device while ensuring semiconductor device quality. This semiconductor device is equipped with a Si (silicon) substrate, a SiO2 (silicon oxide) layer formed on a surface of the Si substrate, a Si layer formed on a surface of the SiO2 layer, and a SiC (silicon carbide) layer formed atop a surface of the Si layer. The thickness of the SiO2 layer is not less than 1 [mu]m and does not exceed 20 [mu]m.

Description

具備碳化矽層之半導體裝置 Semiconductor device with tantalum carbide layer

本發明係有關具備SiC(碳化矽)層之半導體裝置。 The present invention relates to a semiconductor device having a SiC (tantalum carbide) layer.

SiC係比較於Si(矽)，能帶隙為大，而具有高絕緣破壞電場強度。因此，SiC係作為具有高耐壓之半導體裝置的材料而被加以期待。另外，3C-SiC(具有3C型之結晶構造的SiC)係從與GaN(氮化鎵)的晶格常數接近之情況，可作為為了使GaN之基材基板而使用者。GaN之絕緣破壞電場強度係較3C-SiC之絕緣破壞電場為大之故，由將3C-SiC作為緩衝層者，可實現更高耐壓之GaN之半導體裝置。 Compared with Si (矽), the SiC system has a large band gap and a high dielectric breakdown electric field strength. Therefore, SiC is expected as a material of a semiconductor device having a high withstand voltage. Further, 3C-SiC (SiC having a 3C type crystal structure) can be used as a base substrate for GaN when it is close to the lattice constant of GaN (gallium nitride). The dielectric breakdown strength of GaN is larger than that of 3C-SiC, and a higher breakdown voltage GaN semiconductor device can be realized by using 3C-SiC as a buffer layer.

作為為了使3C-SiC層成長之基材基板，係Si基板或塊狀之SiC基板則被廣泛使用。其中，塊狀的SiC基板係在目前僅存在有4英吋程度的構成，而具有大口徑化困難的問題。對於為了以廉價取得大口徑之寬禁帶半導體，係使用Si基板者為佳。 As a base substrate for growing a 3C-SiC layer, a Si substrate or a bulk SiC substrate is widely used. Among them, the bulk SiC substrate has a structure of only about 4 inches, and has a problem that it is difficult to enlarge the diameter. It is preferable to use a Si substrate for a wide band gap semiconductor which is obtained at a low cost.

對於下記專利文獻1~3係加以揭示有有關以 SiC為始，使用寬禁帶半導體之半導體裝置的技術。對於下記專利文獻1係加以記載有：於將立方晶{001}面作為表面之單結晶基板上，經由磊晶成長而使2種類之元素A、B所成之化合物單結晶(SiC或GaN等)成長之方法。在此方法中，具備：使反相位範圍邊界面以及因元素A及B引起之層積缺陷，於表面各等效地產生於平行之<110>方向同時，使化合物單結晶成長之工程(I)，和使因在工程(I)中產生之元素A引起之層積缺陷，與反相位範圍邊界面會合消滅之工程(II)，和使因在工程(I)中產生之元素B引起之層積缺陷，自我消滅之工程(III)，和完全地使反相位範圍邊界會合消滅之工程(IV)。工程(IV)係與工程(II)及(III)並行，或在工程(II)及(III)之後加以進行。 For the following patent documents 1 to 3, it is disclosed that SiC is a technology that uses a semiconductor device of a wide band gap semiconductor. Patent Document 1 discloses a single crystal (SiC, GaN, etc.) formed by two types of elements A and B on a single crystal substrate having a cubic crystal {001} surface as a surface. ) The method of growth. In this method, the boundary surface of the opposite phase range and the layer defects caused by the elements A and B are simultaneously generated in the parallel <110> direction on the surface, and the single crystal growth of the compound is performed ( I), and the delamination caused by the element A produced in the engineering (I), the elimination of the boundary surface of the inverse phase range (II), and the element B produced in the engineering (I) The resulting layering defects, the self-destruction of the project (III), and the engineering (IV) that completely eliminates the boundary of the anti-phase range. Engineering (IV) is carried out in parallel with Engineering (II) and (III) or after Engineering (II) and (III).

對於下記專利文獻2係加以揭示有：準備具有特定厚度之表面Si層與埋入絕緣層之Si基板，在碳系氣體環境中加熱上述Si基板而使表面Si層變成為單結晶SiC層之單結晶SiC基板的製造方法。在此製造方法中，在使表面Si層變成為單結晶SiC層時，與埋入絕緣層之界面附近的Si層則作為殘存Si層而加以殘留。埋入絕緣層係經由具有1~200nm厚度之SiO2(氧化矽)而成，而SiC層係具有100nm程度的厚度。 Patent Document 2 discloses that a Si substrate having a specific thickness of a surface Si layer and a buried insulating layer is prepared, and the Si substrate is heated in a carbon-based gas atmosphere to change the surface Si layer into a single crystal SiC layer. A method of producing a crystalline SiC substrate. In this manufacturing method, when the surface Si layer is changed to a single crystal SiC layer, the Si layer in the vicinity of the interface with the buried insulating layer remains as a residual Si layer. The buried insulating layer is formed by SiO 2 (yttria) having a thickness of 1 to 200 nm, and the SiC layer has a thickness of about 100 nm.

對於下記專利文獻3係加以揭示有：具備SOI(Silicon On Insulator)基板，和作為加以形成於SOI基板上之緩衝層的AlN(氮化鋁)層，和作為加以形成於 AlN層上之通道層的GaN層，和作為加以形成於GaN層上之阻障層的AlGaN(氮化鋁鎵)層，和加以形成於AlGaN層上之源極電極，汲極電極，及閘極電極的半導體裝置。 The following Patent Document 3 discloses an SOI (Silicon On Insulator) substrate and an AlN (aluminum nitride) layer as a buffer layer formed on the SOI substrate, and is formed as a GaN layer of a channel layer on the AlN layer, and an AlGaN (aluminum gallium nitride) layer as a barrier layer formed on the GaN layer, and a source electrode, a drain electrode, and a gate formed on the AlGaN layer A semiconductor device of a pole electrode.

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1：日本特開2011-84435號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2011-84435

專利文獻2：日本特開2009-302097號公報 Patent Document 2: Japanese Laid-Open Patent Publication No. 2009-302097

專利文獻3：日本特開2008-34411號公報 Patent Document 3: Japanese Patent Laid-Open Publication No. 2008-34411

SiC係比較於Si而具有非常高之絕緣破壞電場強度。具體而言，Si之絕緣破壞電場強度係為0.3MV/cm，而3C-SiC之絕緣破壞電場強度係為1.2MV/cm。隨之，在具有將Si基板作為基材基板而形成SiC層之構造的半導體裝置中，對於為了提升縱方向(Si基板之主面的法線方向)之耐壓提升，如增加SiC層之厚度即可。 The SiC system has a very high dielectric breakdown electric field strength compared to Si. Specifically, the dielectric breakdown electric field strength of Si is 0.3 MV/cm, and the dielectric breakdown electric field strength of 3C-SiC is 1.2 MV/cm. In the semiconductor device having a structure in which a Si substrate is used as a base substrate to form a SiC layer, the thickness of the SiC layer is increased in order to increase the withstand voltage in the vertical direction (the normal direction of the main surface of the Si substrate). Just fine.

但在將Si基板作為基材基板而形成SiC層之半導體裝置中，晶格常數或熱膨脹係數相互不同之Si與SiC則構成異質界面之故，而對於僅增加SiC層之厚度的 情況，係容易引起基板的變形，或對於SiC層之斷裂的發生。其結果，對於經由加厚SiC層而提升半導體裝置之縱方向的耐壓，係有界限。 However, in a semiconductor device in which a Si substrate is used as a base substrate to form a SiC layer, Si and SiC having different lattice constants or thermal expansion coefficients form a hetero interface, and only the thickness of the SiC layer is increased. In this case, it is easy to cause deformation of the substrate or occurrence of cracking of the SiC layer. As a result, there is a limit to increasing the withstand voltage in the longitudinal direction of the semiconductor device by thickening the SiC layer.

然而，對於使用上述專利文獻1之技術而形成SiC層的情況，係可抑止斷裂之發生同時，形成比較厚之SiC層者，但有著工程產生複雜化等之問題。 However, in the case where the SiC layer is formed by the technique of Patent Document 1 described above, it is possible to suppress the occurrence of cracking and form a relatively thick SiC layer, but there is a problem that the engineering is complicated.

本發明係為了解決上述課題之構成，其目的係為確保半導體裝置之品質的同時，提高半導體裝置之縱方向的耐壓者。 The present invention has been made to solve the above-described problems, and an object thereof is to improve the resistance of the semiconductor device in the longitudinal direction while ensuring the quality of the semiconductor device.

依照本發明之一的狀況之半導體裝置係具備：Si基板，和加以形成於Si基板表面之SiO2層，和加以形成於SiO2層表面之Si層，和加以形成於Si層表面上之SiC層，而SiO2層之厚度係1μm以上20μm以下。 Based semiconductor device in accordance with one of the conditions of the present invention includes: Si substrate, and the substrate to be formed on the surface of the Si 2 SiO layer, and the SiO 2 layer to be formed on the surface of the Si layer, and be formed on the surface of the Si layer on the SiC layer, the SiO 2 layer of a thickness of 20μm or less based 1μm or more.

在上述半導體裝置中，理想為SiC層係3C-SiC，而SiC層之厚度係0.1μm以上3μm以下。 In the above semiconductor device, the SiC layer is preferably 3C-SiC, and the thickness of the SiC layer is 0.1 μm or more and 3 μm or less.

在上述半導體裝置中，理想為Si層之厚度係5nm以上10nm以下。 In the above semiconductor device, the thickness of the Si layer is preferably 5 nm or more and 10 nm or less.

在上述半導體裝置中，理想為更具備加以形成於SiC層之半導體元件。 In the above semiconductor device, it is preferable to further include a semiconductor element formed on the SiC layer.

在上述半導體裝置中，理想為更具備加以形成於SiC層表面上之氮化物半導體層，和加以形成於氮化物半導體層之半導體元件。 In the above semiconductor device, it is preferable to further include a nitride semiconductor layer formed on the surface of the SiC layer and a semiconductor element formed on the nitride semiconductor layer.

如根據本發明，在確保半導體裝置之品質的同時，可提高半導體裝置之縱方向的耐壓者。 According to the present invention, while the quality of the semiconductor device is ensured, the withstand voltage in the longitudinal direction of the semiconductor device can be improved.

1‧‧‧Si(矽)基板 1‧‧‧Si (矽) substrate

1a‧‧‧Si基板的背面 1a‧‧‧Si back of the Si substrate

2‧‧‧SiO2(氧化矽)層 2‧‧‧SiO 2 (yttria) layer

3‧‧‧Si層 3‧‧‧Si layer

4‧‧‧SiC(碳化矽)層 4‧‧‧SiC (carbonized tantalum) layer

5‧‧‧GaN(氮化鎵)層 5‧‧‧GaN (GaN) layer

6‧‧‧AlGaN(氮化鋁鎵)層 6‧‧‧AlGaN (aluminum gallium nitride) layer

7‧‧‧氮化物半導體層 7‧‧‧ nitride semiconductor layer

8a，8b‧‧‧不純物範圍 8a, 8b‧‧‧ Impure range

11‧‧‧源極電極 11‧‧‧Source electrode

12‧‧‧汲極電極 12‧‧‧汲electrode

13‧‧‧閘極電極 13‧‧‧gate electrode

14‧‧‧電阻電極 14‧‧‧Resistive electrode

15‧‧‧肖特基電極 15‧‧‧Schottky electrode

16‧‧‧閘極絕緣層 16‧‧‧ gate insulation

圖1係顯示在本發明之第1實施形態的半導體裝置之構成的剖面圖。 Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention.

圖2係顯示SiC層之厚度，和斷裂發生之有無及SiC層之結晶性的關係表。 Fig. 2 is a table showing the relationship between the thickness of the SiC layer, the presence or absence of cracking, and the crystallinity of the SiC layer.

圖3係顯示基板之尺寸及SiO2層之厚度，和基板之彎曲量Wt之關係表。 Fig. 3 is a table showing the relationship between the size of the substrate and the thickness of the SiO 2 layer, and the bending amount Wt of the substrate.

圖4係顯示在本發明之第2實施形態的半導體裝置之構成的剖面圖。 Fig. 4 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention.

圖5係顯示在本發明之第3實施形態的半導體裝置之構成的剖面圖。 Fig. 5 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention.

以下，依據圖面而說明本發明之實施形態。 Hereinafter, embodiments of the present invention will be described based on the drawings.

(第1實施形態) (First embodiment)

圖1係顯示在本發明之第1實施形態的半導體裝置之構成的剖面圖。 Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention.

參照圖1，在本實施形態之半導體裝置係包含GaN-HEMT(High Electron Mobility Transistor)。半導體裝置係具備：Si基板1，和SiO2層(埋入玻璃層)2，和Si層3，和SiC層4，和GaN層5，和AlGaN層6，和源極電極11及汲極電極12，和閘極電極13。GaN層5及AlGaN層6係構成氮化物半導體層7。對於氮化物半導體層7係加以形成HEMT(半導體元件的一例)。 Referring to Fig. 1, the semiconductor device of the present embodiment includes a GaN-HEMT (High Electron Mobility Transistor). The semiconductor device includes: a Si substrate 1, and an SiO 2 layer (buried glass layer) 2, and a Si layer 3, and a SiC layer 4, and a GaN layer 5, and an AlGaN layer 6, and a source electrode 11 and a drain electrode 12, and gate electrode 13. The GaN layer 5 and the AlGaN layer 6 constitute the nitride semiconductor layer 7. A HEMT (an example of a semiconductor element) is formed on the nitride semiconductor layer 7.

Si基板1係具有p型或n型之導電型亦可。 The Si substrate 1 may have a p-type or n-type conductivity type.

SiO2層2係加以形成於Si基板1的表面。SiO2層2之厚度係1μm以上20μm以下。SiO2層2之厚度係1.2μm以上者為佳。SiO2層2之厚度係10μm以下者為佳，而5μm以下者為更佳。 The SiO 2 layer 2 is formed on the surface of the Si substrate 1. The thickness of the SiO 2 layer 2 is 1 μm or more and 20 μm or less. The thickness of the SiO 2 layer 2 is preferably 1.2 μm or more. The thickness of the SiO 2 layer 2 is preferably 10 μm or less, and more preferably 5 μm or less.

Si層3係加以形成於SiO2層2之表面。Si層3之厚度係5nm以上10nm以下者為佳。然而，Si層3係例如，由氧化構成Si層3之Si者而形成SiO2，經由蝕刻此SiO2之時，加以薄膜化至上述之範圍為止亦可。 The Si layer 3 is formed on the surface of the SiO 2 layer 2. The thickness of the Si layer 3 is preferably 5 nm or more and 10 nm or less. However, based e.g. Si layer 3, an oxide of SiO 2 and Si is formed by the Si layer 3, when the 2 SiO etching via this, to be thinned until the above-described range can be.

Si基板1、SiO2層2、及Si層3係構成SOI(Silicon On Insulator)基板。SiO2層2及Si層3係例如，使用貼合法或SIMOX(Separation by IMplanted OXygen)法等而加以形成。 The Si substrate 1, the SiO 2 layer 2, and the Si layer 3 constitute an SOI (Silicon On Insulator) substrate. The SiO 2 layer 2 and the Si layer 3 are formed, for example, by a bonding method or a SIMOX (Separation by IMplanted OXygen) method.

SiC層4係加以形成於Si層3的表面。SiC層4係例如，經由3C-SiC、4H-SiC、或6H-SiC等而成。特別是，SiC層4則為加以磊晶成長於Si基板1者之情況，一般而言，SiC層4係經由3C-SiC而成。此情況，SiC層 4之厚度係0.1μm以上者為佳，而0.5μm以上者更佳。另外，SiC層4之厚度係3μm以下者為佳，而2μm以下者為更佳。 The SiC layer 4 is formed on the surface of the Si layer 3. The SiC layer 4 is formed, for example, by 3C-SiC, 4H-SiC, or 6H-SiC. In particular, the SiC layer 4 is formed by epitaxial growth on the Si substrate 1. Generally, the SiC layer 4 is formed by 3C-SiC. In this case, the SiC layer The thickness of 4 is preferably 0.1 μm or more, and more preferably 0.5 μm or more. Further, the thickness of the SiC layer 4 is preferably 3 μm or less, and more preferably 2 μm or less.

SiC層4係於由碳化Si層3之表面者而加以得到之SiC所成之基材層上，使用MBE(分子束磊晶)法、CVD(化學蒸鍍)法、或LPE(液相磊晶)法等，經由使SiC加以同質磊晶成長之時而加以形成亦可。SiC層4係僅經由碳化Si層3的表面而加以形成亦可。更且，SiC層4係經由夾持緩衝層而於Si層3表面上，使SiC加以異質磊晶成長之時而加以形成亦可。 The SiC layer 4 is formed on a substrate layer made of SiC obtained by the surface of the carbonized Si layer 3, using MBE (molecular beam epitaxy) method, CVD (chemical vapor deposition) method, or LPE (liquid phase Lei The crystal method or the like may be formed by growing SiC by homogenous epitaxial growth. The SiC layer 4 may be formed only by the surface of the carbonized Si layer 3. Further, the SiC layer 4 may be formed on the surface of the Si layer 3 by sandwiching the buffer layer, and SiC may be formed by heteroepitaxial growth.

GaN層5係加以形成於SiC層4的表面。對於GaN層5係未加以導入不純物，而GaN層5係成為HEMT之電子走行層。 The GaN layer 5 is formed on the surface of the SiC layer 4. The impurity is not introduced into the GaN layer 5, and the GaN layer 5 is an electron running layer of the HEMT.

AlGaN層6係加以形成於GaN層5的表面。AlGaN層6係具有n型之導電型，成為HEMT之障壁層。AlGaN層6係例如，經由HVPE(氫化物氣相磊晶)法、或MOCVD(有機金屬氣相成長)法等而加以形成。 The AlGaN layer 6 is formed on the surface of the GaN layer 5. The AlGaN layer 6 has an n-type conductivity type and is a barrier layer of the HEMT. The AlGaN layer 6 is formed, for example, by an HVPE (Hydride Vapor Phase Epitaxy) method or an MOCVD (Organic Metal Vapor Phase Growth) method.

SiC與GaN係晶格常數為近似。因此，SiC層4係達成作為GaN層5之緩衝層(基材層)的作用。然而，GaN層5及AlGaN層6係如加以形成於SiC層4表面上即可，而於SiC層4與GaN層5之間，例如，加以形成有AlN所成之緩衝層亦可。加以形成有HEMT情況之氮化物半導體層係如包含第1氮化物半導體層，和加以形成於第1氮化物半導體層表面，具有較第1氮化物半導 體層之能帶隙為寬的能帶隙之第2氮化物半導體層者即可，而經由GaN與AlGaN之組合外的氮化物半導體材料之組合加以構成亦可。 The lattice constants of SiC and GaN are approximate. Therefore, the SiC layer 4 functions as a buffer layer (base material layer) of the GaN layer 5. However, the GaN layer 5 and the AlGaN layer 6 may be formed on the surface of the SiC layer 4, and a buffer layer made of AlN may be formed between the SiC layer 4 and the GaN layer 5, for example. The nitride semiconductor layer in which the HEMT is formed includes a first nitride semiconductor layer and is formed on the surface of the first nitride semiconductor layer to have a first nitride semiconductor The second nitride semiconductor layer having a wide band gap of the bulk layer may be formed by a combination of nitride semiconductor materials other than the combination of GaN and AlGaN.

各源極電極11及汲極電極12係相互拉開間隔而加以形成於氮化物半導體層7之表面。閘極電極13係在氮化物半導體層7的表面中，加以形成於源極電極11及汲極電極12之間。各源極電極11及汲極電極12係電阻接觸於氮化物半導體層7。閘極電極13係肖特基接觸於氮化物半導體層7。各源極電極11及汲極電極12係例如，具有自氮化物半導體層7側，依序層積Ti(鈦)層及Al(鋁)層之構造。閘極電極13係例如，具有自氮化物半導體層7側依序層積Ni(鎳)層及Au(金)層之構造。各源極電極11，汲極電極12，及閘極電極13係例如，經由蒸鍍法、MOCVD法、或濺鍍法等而加以形成。 Each of the source electrode 11 and the drain electrode 12 is formed on the surface of the nitride semiconductor layer 7 with a space therebetween. The gate electrode 13 is formed on the surface of the nitride semiconductor layer 7 and is formed between the source electrode 11 and the drain electrode 12. Each of the source electrode 11 and the drain electrode 12 is in electrical contact with the nitride semiconductor layer 7. The gate electrode 13 is Schottky contacted with the nitride semiconductor layer 7. Each of the source electrode 11 and the drain electrode 12 has a structure in which a Ti (titanium) layer and an Al (aluminum) layer are sequentially laminated from the nitride semiconductor layer 7 side. The gate electrode 13 has a structure in which a Ni (nickel) layer and an Au (gold) layer are sequentially laminated from the nitride semiconductor layer 7 side. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed, for example, by a vapor deposition method, an MOCVD method, a sputtering method, or the like.

然而，為了固定Si基板1之背面的電位，而加以電性連接Si基板1之背面1a，和源極電極11或汲極電極12。 However, in order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 are electrically connected.

構成半導體裝置之各層的厚度係使用橢圓偏光量測器而加以測定。橢圓偏光量測器係將偏光的入射光照射至測定對象，將來自測定對象的反射光受光。在S偏光與P偏光中有著相位的偏差或反射率的不同之故，反射光之偏光狀態係成為與入射光的偏光狀態不同者。此偏光狀態的變化係依存於入射光的波長，入射角度，膜的光學常數，及膜厚等。橢圓偏光量測器係自所得到之反射光， 依據入射光的波長或入射角而算出膜的光學常數或膜厚。 The thickness of each layer constituting the semiconductor device was measured using an ellipsometer. The ellipsometry measuring device irradiates the incident light of the polarized light to the measurement target, and receives the reflected light from the measurement target. Since there is a phase difference or a reflectance difference between the S polarized light and the P polarized light, the polarization state of the reflected light is different from the polarized state of the incident light. The change in the polarization state depends on the wavelength of the incident light, the angle of incidence, the optical constant of the film, and the film thickness. The ellipsometry is derived from the reflected light, The optical constant or film thickness of the film is calculated from the wavelength or incident angle of the incident light.

本實施形態之半導體裝置的動作係如以下。源極電極11係經常保持為接地電位(成為基準的電位)。在未加以施加電壓於閘極電極13之狀態中，因GaN層5與AlGaN層6之能帶隙的差引起，而在AlGaN層6產生的電子係集中於在GaN層5之與AlGaN層6之異質接合界面，形成二次元電子氣體。伴隨著二次元電子氣體之形成，AlGaN層6內係在自與GaN層5之異質結合界面延伸於圖1中上方向之空乏層，和自與閘極電極13之接合界面延伸於圖1中下方向的空乏層，完全地加以空乏層化。另一方面，當加以施加正的電壓於閘極電極13時，經由電場效果而二次元電子氣體的濃度則變高。其結果，對於加以施加正的電壓於汲極電極12之情況，自汲極電極12流動電流至源極電極11。 The operation of the semiconductor device of the present embodiment is as follows. The source electrode 11 is often maintained at the ground potential (the potential that becomes the reference). In a state where no voltage is applied to the gate electrode 13, the difference in energy band gap between the GaN layer 5 and the AlGaN layer 6 is caused, and electrons generated in the AlGaN layer 6 are concentrated on the GaN layer 5 and the AlGaN layer 6 The heterojunction interface forms a secondary elemental electron gas. With the formation of the secondary electron gas, the AlGaN layer 6 is in the depletion layer extending from the heterojunction interface with the GaN layer 5 in the upper direction of FIG. 1, and extends from the bonding interface with the gate electrode 13 in FIG. The depleted layer in the lower direction is completely vacant. On the other hand, when a positive voltage is applied to the gate electrode 13, the concentration of the secondary electron gas increases due to the electric field effect. As a result, in the case where a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

如根據本實施形態，經由SiO2層2之厚度為1μm以上之時，可將SiC層4之厚度作為不會發生有斷裂程度之厚度之同時，可提高形成HEMT於氮化物半導體層7之半導體裝置之縱方向的耐壓者。另外，經由SiO2層2之厚度為20μm以下之時，可抑止Si基板1之彎曲者。其結果，在確保包含HEMT之半導體裝置之品質的同時，可提高包含HEMT之半導體裝置之縱方向的耐壓者。對於此，於以下，加以詳細說明。 According to the present embodiment, when the thickness of the SiO 2 layer 2 is 1 μm or more, the thickness of the SiC layer 4 can be increased as a thickness at which the degree of fracture does not occur, and the semiconductor in which the HEMT is formed in the nitride semiconductor layer 7 can be improved. The pressure resistance of the device in the longitudinal direction. Further, when the thickness of the SiO 2 layer 2 is 20 μm or less, the bend of the Si substrate 1 can be suppressed. As a result, while ensuring the quality of the semiconductor device including the HEMT, it is possible to improve the withstand voltage in the longitudinal direction of the semiconductor device including the HEMT. This will be described in detail below.

理論上，SiO2之絕緣破壞電場強度係為2~8MV/cm。也就是，隨著SiO2層之厚度增加1μm，而半 導體裝置之縱方向的耐壓係僅增加200~800V。另外，理論上，3C型之SiC之絕緣破壞電場強度係為1.2MV/cm。也就是，隨著SiC層之厚度增加1μm，而半導體裝置之縱方向的耐壓係僅增加120V。 Theoretically, the dielectric breakdown strength of SiO 2 is 2 to 8 MV/cm. That is, as the thickness of the SiO 2 layer is increased by 1 μm, the withstand voltage in the longitudinal direction of the semiconductor device is increased by only 200 to 800 V. In addition, theoretically, the dielectric breakdown electric field strength of the 3C type SiC is 1.2 MV/cm. That is, as the thickness of the SiC layer is increased by 1 μm, the withstand voltage in the longitudinal direction of the semiconductor device is increased by only 120 V.

一般而言，在作為功率裝置之半導體裝置中，在除了在半導體裝置之Si基板以外的部分，被要求560V程度之縱方向的耐壓。但過於增大SiC層之厚度時，成為容易於SiC層發生有斷裂。 In general, in a semiconductor device as a power device, a withstand voltage in the longitudinal direction of about 560 V is required in a portion other than the Si substrate of the semiconductor device. However, when the thickness of the SiC layer is excessively increased, it is easy to cause breakage of the SiC layer.

本申請發明者們係對於SiC層之厚度，和斷裂發生之有無及SiC層之結晶性的關係進行調查。圖2係顯示SiC層之厚度，和斷裂發生之有無及SiC層之結晶性的關係表。 The inventors of the present invention investigated the relationship between the thickness of the SiC layer, the presence or absence of cracking, and the crystallinity of the SiC layer. Fig. 2 is a table showing the relationship between the thickness of the SiC layer, the presence or absence of cracking, and the crystallinity of the SiC layer.

參照圖2，由將SiC層之厚度作為3μm以下、而理想為作為2μm以下者，可抑止斷裂發生。另一方面，由將SiC層4之厚度作為0.1μm以上、理想為作為0.5μm以上者，可確保SiC層4之結晶性。 Referring to Fig. 2, when the thickness of the SiC layer is 3 μm or less, and preferably 2 μm or less, the occurrence of cracking can be suppressed. On the other hand, when the thickness of the SiC layer 4 is 0.1 μm or more, and preferably 0.5 μm or more, the crystallinity of the SiC layer 4 can be ensured.

將SiC層的厚度作為成3μm以下之情況，SiC層之縱方向的耐壓係理論上，成為360V以下。當考慮SiO2之絕緣破壞電場強度時，由將SiO2層之厚度作為1μm以上、理想為作為1.2μm以上者，可確保對於作為功率裝置之半導體裝置所要求之縱方向的耐壓。 When the thickness of the SiC layer is 3 μm or less, the withstand voltage in the longitudinal direction of the SiC layer is theoretically 360 V or less. When considering the SiO 2 dielectric breakdown field strength, the thickness of the SiO 2 layers as 1μm or more, desirably as 1.2μm or more, to ensure a desired pressure to the longitudinal direction of the semiconductor device of the power device.

另外，本申請發明者們係對於Si基板之尺寸及SiO2層之厚度，和Si基板之彎曲量的關係進行調查。圖3係顯示Si基板之尺寸及SiO2層之厚度，和Si基板之 彎曲量Wt之關係表。 Further, the inventors of the present invention investigated the relationship between the size of the Si substrate and the thickness of the SiO 2 layer and the amount of warpage of the Si substrate. Fig. 3 is a table showing the relationship between the size of the Si substrate and the thickness of the SiO 2 layer, and the amount of warpage Wt of the Si substrate.

參照圖3，準備直徑8英吋，厚度725μm之基板(試料1)、直徑8英吋，厚度1500μm之基板(試料2)、及直徑6英吋，厚度1500μm之基板(試料3)之3種類的Si基板。對於各試料1~3而言，各形成較0.5μm為大而5μm以下之厚度的SiO2層，較5μm為大而10μm以下之厚度的SiO2層，較10μm為大而20μm以下之厚度的SiO2層，及較20μm為大之厚度的SiO2層。測定SiO2層形成後之Si基板的彎曲量Wt。 Referring to Fig. 3, three types of substrates (sample 1) having a diameter of 8 inches, a thickness of 725 μm, a substrate having a diameter of 8 inches, a thickness of 1500 μm (sample 2), and a substrate having a diameter of 6 inches and a thickness of 1500 μm (sample 3) were prepared. Si substrate. For each of the samples 1 to 3, an SiO 2 layer having a thickness of 0.5 μm or more and a thickness of 5 μm or less is formed, and a SiO 2 layer having a thickness larger than 5 μm and having a thickness of 10 μm or less is larger than 10 μm and has a thickness of 20 μm or less. The SiO 2 layer and the SiO 2 layer having a thickness greater than 20 μm. The amount of warpage Wt of the Si substrate after the formation of the SiO 2 layer was measured.

其結果，對於形成較20μm為大厚度之SiO2層之情況，在試料1~3任一中，彎曲量的影響均為大。對於形成較10μm為大而20μm以下之厚度之SiO2層情況，在試料1及2中，彎曲量的影響為大之另一方面，在試料3中，幾乎未有彎曲量的影響。對於形成較5μm為大而10μm以下之厚度之SiO2層之情況，在試料1中，彎曲量的影響為大之另一方面，在試料2及3中，幾乎未有彎曲量的影響。對於形成較0.5μm為大而5μm以下之厚度之SiO2層之情況，在試料1~3任一中，幾乎均未有彎曲量的影響。 As a result, in the case where the SiO 2 layer having a large thickness of 20 μm was formed, the influence of the amount of warping was large in any of the samples 1 to 3. In the case of forming the SiO 2 layer having a thickness larger than 10 μm and having a thickness of 20 μm or less, in the samples 1 and 2, the influence of the amount of warpage was large, and in the sample 3, there was almost no influence of the amount of warping. In the case of forming the SiO 2 layer having a thickness larger than 5 μm and having a thickness of 10 μm or less, the influence of the amount of warpage was large in the sample 1, and in the samples 2 and 3, there was almost no influence of the amount of warpage. In the case of forming a SiO 2 layer having a thickness of 0.5 μm or more and a thickness of 5 μm or less, in any of the samples 1 to 3, almost no influence of the amount of bending was observed.

從以上的結果，由將SiO2層2之厚度作為20μm以下、而理想作為10μm以下、更理想作為5μm以下者，可抑止基板之彎曲。 From the above results, the thickness of the SiO 2 layer 2 is preferably 20 μm or less, and preferably 10 μm or less, more preferably 5 μm or less, whereby the bending of the substrate can be suppressed.

加上，如根據本實施形態，因SiC層4則達成作為氮化物半導體層7之緩衝層之作用之故，可形成高 品質之氮化物半導體層7者。 In addition, according to the present embodiment, since the SiC layer 4 functions as a buffer layer of the nitride semiconductor layer 7, it can be formed high. The quality of the nitride semiconductor layer 7 is.

[第2實施形態] [Second Embodiment]

圖4係顯示在本發明之第2實施形態的半導體裝置之構成的剖面圖。 Fig. 4 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention.

參照圖4，在本實施形態之半導體裝置係包含SBD(Schottky Barrier Diode)。半導體裝置係具備：Si基板1，和SiO2層2，和Si層3，和SiC層4，和電阻電極14及肖特基電極15。對於SiC層4係加以形成SBD(半導體元件的一例)。各SiO2層2，Si層3，及SiC層4之厚度係與第1實施形態和情況相同。半導體裝置係未具備氮化物半導體層。 Referring to Fig. 4, the semiconductor device of the present embodiment includes an SBD (Schottky Barrier Diode). The semiconductor device includes a Si substrate 1 and an SiO 2 layer 2, an Si layer 3, and a SiC layer 4, and a resistance electrode 14 and a Schottky electrode 15. SBD (an example of a semiconductor element) is formed on the SiC layer 4 system. The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that of the first embodiment. The semiconductor device does not have a nitride semiconductor layer.

SiC層4係具有n型之導電型。作為將SiC層4作為n型化之不純物，係例如可使用N(氮)、P(磷)、及As(砷)之中至少1種類者。 The SiC layer 4 has an n-type conductivity type. As the impurity in which the SiC layer 4 is made n-type, for example, at least one of N (nitrogen), P (phosphorus), and As (arsenic) can be used.

各電阻電極14及肖特基電極15係相互拉開間隔而加以形成於SiC層4之表面。SiC層4則具有n型之導電型之情況，電阻電極14係例如經由Ni或Al等而成。肖特基電極15係例如，經由Au、Pt(白金)、或Al-Ti合金等而成。電阻電極14及肖特基電極15係例如，經由蒸鍍法、MOCVD法、或濺鍍法等而加以形成。 Each of the resistance electrode 14 and the Schottky electrode 15 is formed on the surface of the SiC layer 4 with a space therebetween. The SiC layer 4 has an n-type conductivity type, and the resistance electrode 14 is made of, for example, Ni or Al. The Schottky electrode 15 is formed, for example, by using Au, Pt (platinum), or an Al-Ti alloy. The resistive electrode 14 and the Schottky electrode 15 are formed, for example, by a vapor deposition method, an MOCVD method, a sputtering method, or the like.

然而，為了固定Si基板1之背面的電位，而加以電性連接Si基板1之背面1a，和電阻電極14或肖特基電極15亦可。 However, in order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 may be electrically connected, and the resistance electrode 14 or the Schottky electrode 15 may be electrically connected.

上述以外之半導體裝置的構成係因與圖1所示之第1實施形態的構成同樣之故，對於同一構件係附上同一符號，而未加以反覆其說明。 The configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in Fig. 1. The same components are denoted by the same reference numerals and will not be described again.

本實施形態之半導體裝置的動作係如以下。電阻電極14係經常保持為接地電位(成為基準的電位)。在未加以施加電壓於肖特基電極15之狀態，或加以施加負的電位於肖特基電極15之狀態中，成為逆方向偏壓，電流係未流動於SBD。另一方面，在加以施加正的電壓於肖特基電極15之狀態中，成為順方向偏壓，自肖特基電極15流動有電流至電阻電極14。 The operation of the semiconductor device of the present embodiment is as follows. The resistance electrode 14 is often maintained at the ground potential (the potential that becomes the reference). In a state where no voltage is applied to the Schottky electrode 15 or a negative electric current is applied to the Schottky electrode 15, the voltage is reversed in the reverse direction, and the current does not flow in the SBD. On the other hand, in a state where a positive voltage is applied to the Schottky electrode 15, a forward bias is applied, and a current flows from the Schottky electrode 15 to the resistance electrode 14.

如根據本實施形態，在確保包含SBD之半導體裝置之品質的同時，可提高包含SBD之半導體裝置之縱方向的耐壓者。 According to the present embodiment, while ensuring the quality of the semiconductor device including the SBD, it is possible to improve the withstand voltage in the longitudinal direction of the semiconductor device including the SBD.

然而，SiC層4係具有p型之導電型亦可。作為將SiC層4作為p型化之不純物，係例如可使用B(硼)、Al、Ga(鎵)、及In(銦)之中至少1種類者。SiC層4則具有p型之導電型之情況，電阻電極14係例如經由Au、Pt、或Al-Ti合金等而加以形成。肖特基電極15係例如，由Ni或Al等而加以形成。 However, the SiC layer 4 may have a p-type conductivity type. As the impurity in which the SiC layer 4 is p-type, for example, at least one of B (boron), Al, Ga (gallium), and In (indium) can be used. The SiC layer 4 has a p-type conductivity type, and the resistance electrode 14 is formed, for example, via Au, Pt, or an Al-Ti alloy. The Schottky electrode 15 is formed, for example, of Ni or Al.

[第3實施形態] [Third embodiment]

圖5係顯示在本發明之第3實施形態的半導體裝置之構成的剖面圖。 Fig. 5 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention.

參照圖5，在本實施形態之半導體裝置係包含 n型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)。半導體裝置係具備：Si基板1，和SiO2層2，和Si層3，和SiC層4，和不純物範圍8a及8b，和源極電極11及汲極電極12，和閘極電極13。對於SiC層4係加以形成n型MOSFET(半導體元件的一例)。各SiO2層2，Si層3，及SiC層4之厚度係與第1實施形態和情況相同。半導體裝置係未具備氮化物半導體層。 Referring to Fig. 5, the semiconductor device of the present embodiment includes an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device includes a Si substrate 1 and an SiO 2 layer 2, and an Si layer 3, and a SiC layer 4, and impurity ranges 8a and 8b, a source electrode 11 and a drain electrode 12, and a gate electrode 13. An n-type MOSFET (an example of a semiconductor element) is formed on the SiC layer 4 . The thickness of each of the SiO 2 layer 2, the Si layer 3, and the SiC layer 4 is the same as that of the first embodiment. The semiconductor device does not have a nitride semiconductor layer.

SiC層4係具有n型之導電型。各不純物範圍8a及8b係具有p型之導電型，相互拉開間隔而加以形成於SiC層4的表面。不純物範圍8a及8b係經由離子注入法或熱擴散法等而加以形成。作為為了將不純物範圍8a及8b作為p型化之不純物，係例如可使用B、Al、Ga、及In之中至少1種類者。 The SiC layer 4 has an n-type conductivity type. Each of the impurity ranges 8a and 8b has a p-type conductivity type, and is formed on the surface of the SiC layer 4 by being spaced apart from each other. The impurity ranges 8a and 8b are formed by an ion implantation method, a thermal diffusion method, or the like. As the impurity for p-type the impurity range 8a and 8b, for example, at least one of B, Al, Ga, and In can be used.

各源極電極11及汲極電極12係加以形成於各不純物範圍8a及8b之表面。閘極電極13係於不純物範圍8a與不純物範圍8b之間的SiC層4表面，夾持閘極絕緣層16而加以形成。閘極電極13及閘極絕緣層16係加以形成於源極電極11及汲極電極12之間。各源極電極11，汲極電極12，及閘極電極13係由Al或Cu(銅)等而成。閘極絕緣層16係例如由SiO2而成。閘極絕緣層16係亦可由Hf(鉿)、Zr(鋯)、Al、或Ti等之各氧化物，或此等之矽酸鹽化合物而成。各源極電極11，汲極電極12，及閘極電極13係例如，經由蒸鍍法、MOCVD法、或濺鍍法等而加以形成。閘極絕緣層16係例如，經 由電漿CVD法等而加以形成。 Each of the source electrode 11 and the drain electrode 12 is formed on the surface of each of the impurity ranges 8a and 8b. The gate electrode 13 is formed on the surface of the SiC layer 4 between the impurity range 8a and the impurity range 8b, and is formed by sandwiching the gate insulating layer 16. The gate electrode 13 and the gate insulating layer 16 are formed between the source electrode 11 and the drain electrode 12. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is made of Al or Cu (copper) or the like. The gate insulating layer 16 is made of, for example, SiO 2 . The gate insulating layer 16 may be made of each oxide such as Hf (yttrium), Zr (zirconium), Al, or Ti, or the like. Each of the source electrode 11, the drain electrode 12, and the gate electrode 13 is formed, for example, by a vapor deposition method, an MOCVD method, a sputtering method, or the like. The gate insulating layer 16 is formed, for example, by a plasma CVD method or the like.

然而，為了固定Si基板1之背面的電位，而加以電性連接Si基板1之背面1a，和源極電極11或汲極電極12。 However, in order to fix the potential of the back surface of the Si substrate 1, the back surface 1a of the Si substrate 1 and the source electrode 11 or the drain electrode 12 are electrically connected.

上述以外之半導體裝置的構成係因與圖1所示之第1實施形態的構成同樣之故，對於同一構件係附上同一符號，而未加以反覆其說明。 The configuration of the semiconductor device other than the above is the same as that of the first embodiment shown in Fig. 1. The same components are denoted by the same reference numerals and will not be described again.

本實施形態之半導體裝置的動作係如以下。源極電極11係經常保持為接地電位(成為基準的電位)。在未加以施加電壓於閘極電極13之狀態，或加以施加負的電壓於閘極電極13之狀態中，對於源極電極11與汲極電極12之間係未流動有電流。另一方面，當加以施加正的電壓於閘極電極13時，存在於SiC層4內之電子則加以吸引至構成與閘極絕緣層16之界面的SiC層4表面，於不純物範圍8a與不純物範圍8a之間形成n型的反轉層。其結果，對於加以施加正的電壓於汲極電極12之情況，自汲極電極12流動電流至源極電極11。 The operation of the semiconductor device of the present embodiment is as follows. The source electrode 11 is often maintained at the ground potential (the potential that becomes the reference). In a state where no voltage is applied to the gate electrode 13 or a negative voltage is applied to the gate electrode 13, a current does not flow between the source electrode 11 and the drain electrode 12. On the other hand, when a positive voltage is applied to the gate electrode 13, electrons existing in the SiC layer 4 are attracted to the surface of the SiC layer 4 constituting the interface with the gate insulating layer 16, in the impurity range 8a and impurities. An n-type inversion layer is formed between the ranges 8a. As a result, in the case where a positive voltage is applied to the drain electrode 12, a current flows from the drain electrode 12 to the source electrode 11.

如根據本實施形態，在確保包含MOSFET之半導體裝置之品質的同時，可提高包含MOSFET之半導體裝置之縱方向的耐壓者。 According to the present embodiment, while ensuring the quality of the semiconductor device including the MOSFET, the withstand voltage in the longitudinal direction of the semiconductor device including the MOSFET can be improved.

然而，半導體裝置係亦可包含p型MOSFET。此情況，SiC層4係作為p型之導電型，而不純物範圍8a及8b係作為n型之導電型。作為為了將不純物範圍8a及8b作為n型化之不純物，係例如可使用N、 P、及As之中至少1種類者。 However, the semiconductor device may also include a p-type MOSFET. In this case, the SiC layer 4 is a p-type conductivity type, and the impure object ranges 8a and 8b are an n-type conductivity type. As the impurity for making the impurity range 8a and 8b as n-type, for example, N, At least one of P and As.

[其他] [other]

加以形成於半導體裝置之半導體元件係如為任意之構成即可，例如，亦可為二極體，電晶體，閘流器，或半導體雷射等。半導體元件係為橫型之構成(經由在加以形成於SiO2層之表面上的層之電性傳導而進行動作之構成)者為佳。 The semiconductor element formed in the semiconductor device may be any configuration, and may be, for example, a diode, a transistor, a thyristor, or a semiconductor laser. It is preferable that the semiconductor element has a horizontal structure (a configuration that operates by electrical conduction of a layer formed on the surface of the SiO 2 layer).

上述之實施形態係認為例示在所有的點，並非限制性的構成。本發明之範圍係並非上述之說明，而經由申請專利範圍所示，特意包含有與申請專利範圍均等意味及在範圍內之所有的變更者。 The above-described embodiments are considered to be exemplified at all points, and are not restrictive. The scope of the present invention is defined by the scope of the claims, and is intended to be

1‧‧‧Si(矽)基板 1‧‧‧Si (矽) substrate

1a‧‧‧Si基板的背面 1a‧‧‧Si back of the Si substrate

2‧‧‧SiO2(氧化矽)層 2‧‧‧SiO 2 (yttria) layer

3‧‧‧Si層 3‧‧‧Si layer

4‧‧‧SiC(碳化矽)層 4‧‧‧SiC (carbonized tantalum) layer

5‧‧‧GaN(氮化鎵)層 5‧‧‧GaN (GaN) layer

6‧‧‧AlGaN(氮化鋁鎵)層 6‧‧‧AlGaN (aluminum gallium nitride) layer

7‧‧‧氮化物半導體層 7‧‧‧ nitride semiconductor layer

11‧‧‧源極電極 11‧‧‧Source electrode

12‧‧‧汲極電極 12‧‧‧汲electrode

13‧‧‧閘極電極 13‧‧‧gate electrode

Claims (5)

一種半導體裝置，其特徵為具備：矽基板，和加以形成於前述矽基板表面之氧化矽層，和加以形成於前述氧化矽層表面之矽層，和加以形成於前述矽層表面上之碳化矽層；前述氧化矽層之厚度係1μm以上20μm以下者。 A semiconductor device comprising: a germanium substrate; and a tantalum oxide layer formed on a surface of the germanium substrate; and a germanium layer formed on a surface of the tantalum oxide layer; and a tantalum carbide formed on a surface of the tantalum layer The layer has a thickness of 1 μm or more and 20 μm or less. 如申請專利範圍第1項記載之半導體裝置，其中，前述碳化矽層係3C-SiC，前述碳化矽層之厚度係0.1μm以上3μm以下者。 The semiconductor device according to claim 1, wherein the thickness of the tantalum carbide layer is 3 μm or less, and the thickness of the tantalum carbide layer is 0.1 μm or more and 3 μm or less. 如申請專利範圍第1項記載之半導體裝置，其中，前述矽層之厚度係5nm以上10nm以下者。 The semiconductor device according to claim 1, wherein the thickness of the tantalum layer is 5 nm or more and 10 nm or less. 如申請專利範圍第1項記載之半導體裝置，其中，更具備加以形成於前述碳化矽層之半導體元件者。 The semiconductor device according to claim 1, further comprising a semiconductor element formed on the tantalum carbide layer. 如申請專利範圍第1項記載之半導體裝置，其中，更具備加以形成於前述碳化矽層表面上之氮化物半導體層，和加以形成於前述氮化物半導體層之半導體元件者。 The semiconductor device according to claim 1, further comprising a nitride semiconductor layer formed on the surface of the tantalum carbide layer and a semiconductor element formed on the nitride semiconductor layer.
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