JPWO2014128990A1 - Phase change channel transistor and driving method thereof - Google Patents

Abstract

A channel layer including a phase change material in which topological phase transition is caused by application of an electric field; a source electrode and a drain electrode connected to the channel layer; an insulating film formed on the first surface of the channel layer; And a second gate electrode formed on the second surface of the channel layer between the source electrode and the drain electrode.

Description

  The present invention relates to a phase change channel transistor and a driving method thereof.

  In addition to the energy required to manipulate and store information, current computer power consumption is increased by Joule heat dissipated in devices and wiring. This energy dissipation occurs in the process in which the electron flow is scattered by lattice defects and phonons. Therefore, in order to meet the recent demand for power saving, it is important how to suppress electron scattering in the device.

  In recent years, as one solution for suppressing electron scattering, it has been proposed to use the conduction characteristics of a crystal system called a Dirac electron system. Electron scattering is suppressed in this new material because the effective carrier equation is the same as the Dirac equation with zero mass, and the topological quantum mechanical phase around the singular point of the band structure is exactly π. This means that the backscattering of electrons is greatly suppressed by quantum mechanical interference, the mobility of the device channel is increased, and the power consumption is reduced.

  Of particular interest in Dirac electron systems are graphene produced in 2004 and topological insulators that were theoretically proposed in 2007.

JP 2009-059902 A JP 2010-109177 A

A. H. Castro Neto et al., Rev. Mod. Phys. 81, 109-162 (2009) M. Z. Hasan et al., Rev. Mod. Phys. 82, 3045-3067 (2010) F. Shcwierz, Nature Nanotechnology 5, 487-496 (2010) M. Kim et al., PNAS January 17, 2012 vol. 109 No. 3, 671-674 J. Tominaga et al. Nature Nanotechnology, 6, 501 (2011). S. Datta, “Quantum Transport-Atom to Transistor”, Cambridge University Press

  As described above, it is theoretically expected that electron scattering can be suppressed by utilizing the quantum effect of the Dirac electron system. It has also been confirmed from both first-principles calculations and experiments that graphene and topological insulators have a band structure as a Dirac electron system.

  However, the quantum effect of the Dirac electron system has not been fully utilized in the device formation. First, the existence of topological insulators was predicted in 2007 relatively recently, and is still in a very basic research stage. Graphene precedes topological insulators in device research, but has not yet reached the stage where electron scattering can be suppressed using the quantum effect in the fabricated devices. On the contrary, it has not been possible to simultaneously achieve the minimum three functions required for use as a transistor, switching (high on / off ratio), drain current saturation, and quick response.

  In addition, graphene transistors currently have the dilemma that channel mobility is sacrificed when the on / off ratio is increased, and the drain current does not saturate in transistor channels where channel mobility is maximized. And did not meet the requirements for practical application.

  An object of the present invention is to provide a phase change channel transistor that can achieve both high channel mobility and high on / off ratio, and a driving method thereof.

  According to one aspect of the embodiment, a channel layer including a phase change material that causes a topological phase transition by application of an electric field, a source electrode and a drain electrode connected to the channel layer, and a first surface of the channel layer There is provided a phase change channel transistor having an insulating film formed on the first insulating film and a first gate electrode formed on the insulating film.

  According to another aspect of the embodiment, a channel layer including a phase change material in which a topological phase transition is caused by application of an electric field, a source electrode and a drain electrode connected to the channel layer, and a first of the channel layer An insulating film formed on the first surface, a first gate electrode formed on the insulating film, and a second surface of the channel layer between the source electrode and the drain electrode. A method of driving a phase change channel transistor having a second gate electrode, wherein the phase change material of the channel layer is applied by an electric field applied between the first gate electrode and the second gate electrode. A phase change channel transistor that switches between a source electrode and a drain electrode by changing between a normal insulator and a topological insulator Driving method is provided.

  According to the disclosed phase change channel transistor and its driving method, both high channel mobility and high on / off ratio can be achieved.

FIG. 1 is a schematic cross-sectional view showing the structure of the phase change channel transistor according to the first embodiment. FIG. 2 is a graph showing the relationship between the Z ₂ invariant and the external electric field in Sb ₂ Te ₃ . FIG. 3 is a schematic diagram showing the structure of Sb ₂ Te ₃ . FIG. 4 is an energy band diagram (part 1) for explaining the operation of the phase change channel transistor according to the first embodiment. FIG. 5 is an energy band diagram (part 2) for explaining the operation of the phase change channel transistor according to the first embodiment. FIG. 6 is a process cross-sectional view (part 1) illustrating the method of manufacturing the phase change channel transistor according to the first embodiment. FIG. 7 is a process cross-sectional view (part 2) illustrating the method of manufacturing the phase change channel transistor according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing the structure of the phase change channel transistor according to the second embodiment. FIG. 9 is an energy band diagram (part 1) for explaining the operation of the phase change channel transistor according to the second embodiment. FIG. 10 is an energy band diagram (part 2) for explaining the operation of the phase change channel transistor according to the second embodiment. FIG. 11 is a process cross-sectional view (part 1) illustrating the method of manufacturing the phase change channel transistor according to the second embodiment. FIG. 12 is a process cross-sectional view (part 2) illustrating the method of manufacturing the phase change channel transistor according to the second embodiment. FIG. 13 is a schematic cross-sectional view showing the structure of the phase change channel transistor according to the third embodiment. FIG. 14 is an energy band diagram (part 1) for explaining the operation of the phase change channel transistor according to the third embodiment. FIG. 15 is an energy band diagram (part 2) for explaining the operation of the phase change channel transistor according to the third embodiment.

[First Embodiment]
The phase change channel transistor and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

FIG. 1 is a schematic cross-sectional view illustrating the structure of the phase change channel transistor according to the present embodiment. FIG. 2 is a graph showing the relationship between the Z ₂ invariant and the external electric field in Sb ₂ Te ₃ . FIG. 3 is a schematic diagram showing the structure of Sb ₂ Te ₃ . 4 and 5 are energy band diagrams illustrating the operation of the phase change channel transistor according to the present embodiment. 6 and 7 are process cross-sectional views illustrating the method of manufacturing the phase change channel transistor according to the present embodiment.

  First, the structure of the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

  A silicon oxide layer 12 is formed on the silicon substrate 10. The silicon oxide layer 12 includes a thick film portion 16A, a thin film portion 16B disposed so as to sandwich the thick film portion 16A, and an inclined portion 16C disposed at a boundary portion between the thick film portion 16A and the thin film portion 16B. A silicon oxide layer 12 is formed.

  A phase change material layer 20 is formed on the silicon oxide layer 12. A gate electrode 22 is formed on the phase change material layer 20 of the thick film portion 16A. A source electrode 24 and a drain electrode 26 are formed on the phase change material layer 20 of the thin film portion 16B disposed so as to sandwich the gate electrode 22 therebetween.

  The silicon substrate 10 is also used as a back gate electrode. Instead of the silicon substrate 10, a conductive layer formed on the silicon substrate 10 via an insulating layer may be formed. In the present specification, a conductive layer used as a back gate electrode may be referred to as a “gate electrode”.

  In the phase change channel transistor according to the present embodiment, the phase change material layer 20 is used as a channel layer, and a current flowing between the source electrode 24 and the drain electrode 26 is applied by an electric field applied between the silicon substrate 10 and the gate electrode 22. It is something to control.

  In the development of graphene transistors so far, an approach using a conventional transistor operation model that has been optimized for non-Dirac electronic systems has been taken.

  However, in the first place, the Dirac electronic system and the non-Dirac electronic system are completely different from the effective equation of carriers. In fact, in graphene, the effective carrier equation is a first-order differential equation of the same shape as the mass-free Dirac equation, similar to the surface state of the topological insulator, whereas in a normal semiconductor that is a non-Dirac electron system, The effective equation is a second-order differential equation that is identical to the Schroedinger equation. If the form of this second-order differential equation is forcibly applied to the band structure of a Dirac electron system with zero mass, the effective mass becomes infinite.

  As described above, the conventional approach of applying the model for the non-Dirac electronic system to the Dirac electronic system not only deteriorates the performance of the graphene transistor but also theoretically fails.

In view of the above, the inventors of the present application focused on the topological phase, which is the source of the conduction characteristics of the Dirac electronic system. The topological phase is a phase change of the wave function when the external parameter of the Hamiltonian changes, and is also called a Berry phase. The Z ₂ invariant calculated from this phase characterizes two topological quantum phases, a topological insulator and a normal insulator, and takes different values for each quantum phase.

  In topological insulators, the special band structure of the zero-mass Dirac electron system results from the relativistic effect of the inner core electrons. This is because, in the heavy elements contained in the topological insulator, the inner core electrons move at such a high speed (˜10% of the speed of light) that the relativistic effect cannot be ignored. Of these relativistic effects, the largest correction to the non-relativistic Schroedinger equation is the interaction between the orbital momentum of electrons and spin. Therefore, in the topological insulator, the energy level that would have been degenerated if there was no spin-orbit interaction was split, and the band structure changed. As a result, there is a special band structure in which the band corresponding to the inside of the material has a gap like an insulator, but the two bands corresponding to the surface level intersect like a conductor (non-conducting). Patent Documents 1 to 3).

  The name topological insulator is derived from topology and topology. This is because the index characterizing the band structure does not change with the continuous deformation of the electronic Hamiltonian, just as the invariant in topology does not change with the continuous deformation of the figure.

  At present, it has been confirmed that topological insulators are not only theoretically possible, but actually exist. However, even if a single crystal produced by a method of cooling molten metal or the like is a topological insulator, it cannot be immediately applied to an electronic device because its conduction state is limited to the interface with vacuum.

  The inventors of the present application have found a superlattice structure in which not only the interface with the vacuum but also the boundaries of all the alloy layers can be in a topological conduction state, and have proposed a device using the superlattice structure (Patent Document 1). And Patent Document 2). By using such a superlattice structure, it is possible to realize a topological conduction state in the device and to realize low power consumption.

  The inventors of the present application have newly found that the dilemma of the graphene transistor performance can be eliminated by using the transition of the topological quantum phase by the external electric field.

  Usually, the transition of the topological quantum phase is known as a change from a normal insulator to a topological insulator depending on the alloy composition, as experimentally shown for bismuth-tellurium and antimony-tellurium alloys. It has been. However, recent theoretical calculations suggest that changes in the external electric field can also cause a quantum phase transition in a solid having a superlattice structure (Non-Patent Document 4).

FIG. 2 is a graph showing changes in the Z ₂ invariant when an external electric field is applied to Sb ₂ Te ₃ (cited from Non-Patent Document 4). In the figure, when the Z ₂ invariant is 0, it represents a normal insulator, and when the Z ₂ invariant is 1, it represents a topological insulator. In the figure, the ● mark plot is 3QLs, and the ▪ mark plot is 4QLs. As shown in FIG. 3, QL is a unit structure layer of Sb ₂ Te ₃ formed of five atomic layers (in the figure, expressed as “ONE QUINTUPLE LAYER”), and “3QLs” Three layers are stacked, and “4QLs” is a stack of four unit structure layers. As shown in FIG. 3, the external electric field is applied in a direction perpendicular to the unit structure layer.

As shown in FIG. 2, in Sb ₂ Te _{3 of} 3QLs, it changes from a normal insulator to a topological insulator by application of an external electric field. On the other hand, in Sb ₂ Te _{3 of} 4QLs, it changes from a topological insulator to a normal insulator by application of an external electric field. In Sb ₂ Te ₃ , when the number of unit structure layers is three or less, the application of an external electric field changes from a normal insulator to a topological insulator, and when the number of unit structure layers is four or more, an external electric field is applied. Is confirmed to change from a topological insulator to a normal insulator.

  The inventors of the present application have confirmed that the above-described superlattice structure is a topological insulator by both the band structure from the first-principles calculation and the change in reflectance of circularly polarized light (Non-Patent Document 5). The superlattice structure that has been verified was formed as a laminated structure in which a crystalline alloy layer composed of germanium and tellurium and a crystalline alloy layer composed of antimony and tellurium are aligned with the <111> plane axis and the c-axis of each. Is. According to the first-principles calculation, it was found that the superlattice structure becomes a topological insulator when the antimony-tellurium alloy layer is one block or more, and becomes a normal insulator when it is thicker than 6 blocks. Then, the inventors of the present application formed the superlattice type phase change film having a different thickness of the antimony-tellurium alloy layer on the silicon wafer, applied an external magnetic field in a direction perpendicular to the surface, and time-reversal symmetry. The spin electron density was changed by breaking and the circularly polarized light was incident on this state, and the change in reflectance was measured. Then, the change of the spin current that should exist at the edge of the sample was confirmed, and it was concluded that the superlattice structure of the present inventors becomes a topological insulator. We also found that when the space reversal symmetry is broken by an electric field, it undergoes a phase transition to a normal insulator with a large Rashba effect.

  Therefore, a transistor that operates in a topological conduction state can be realized by using, for the channel layer, the phase change material layer 20 including a layer of such a material in which transition of a topological quantum phase is caused by application of an external electric field.

  A material that can be applied to the phase change material layer 20 of the phase change channel transistor 20 according to the present embodiment and causes the transition of the topological quantum phase by an external electric field is not particularly limited, but, for example, Ge (germanium), Te (Tellurium) or Bi (bismuth) as a main component layer. Alternatively, the phase change material layer 20 may have Ge, Sb and Te as main components, Ge, Bi and Te as main components, Al, Sb and Te as main components, Al, Bi and Te may be the main components. The “main component” means the component that is contained most.

  As a combination of elements constituting the main component of the phase change material layer 20, a combination of Ge, Sb and Te, a combination of Ge, Bi and Te, a combination of Al, Sb and Te, Al and Bi and The combination with Te etc. is mentioned, Among these, the combination of Ge, Sb, and Te is preferable.

Examples of components of the phase change material layer 20 include GeTe and Sb ₂ Te ₃ when the phase change material layer 20 is mainly composed of Ge, Sb, and Te. Further, when the phase change material layer 20 is mainly composed of Ge, Bi, and Te, GeTe, Bi ₂ Te ₃ , Bi, and the like can be given. Further, when the phase change material layer 20 is mainly composed of Al, Sb, and Te, AlTe, Sb ₂ Te _{3 and the} like can be cited. In the case where the phase change material layer 20 is mainly composed of Al, Bi, and Te, AlTe, Bi ₂ Te ₃ , Bi, and the like can be given.

In the phase change material layer 20 mainly composed of Ge, Sb, and Te, it is desirable that the GeTe layer and the Sb ₂ Te ₃ layer are laminated adjacent to each other. Thereby, a superlattice structure composed of the GeTe layer and the Sb ₂ Te ₃ layer can be formed.

  Next, the operation of the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

Here, the phase change material layer 20 is assumed to change from a normal insulator to a topological insulator by application of an external electric field. For example, in the phase change material layer 20 having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 6QL or more is used.

  First, voltage application conditions for turning off the transistor will be described.

When the transistor is turned off, a negative voltage V _{TG, S} smaller than a threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the gate electrode 22 that is the top gate electrode. A positive voltage V _{BG, S} smaller than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the silicon substrate 10 as the back gate electrode. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In FIG. 4, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, the phase change material layer 20 is in a state where an electric field of a level that does not cause a topological phase transition is applied, and an energy band gap is opened (a state of a normal insulator).

  In the source region and the drain region, since the silicon oxide layer 12 is thin and the phase change material layer 20 is close to the back gate electrode, electrostatic control by the back gate is strong, and the electrostatic potential U is Fermi quasi. It is lowered more than the rank. Note that a technique for controlling the carrier concentration by electrostatically changing the energy difference between the electrostatic potential and the Fermi level in this way is called field effect doping.

In contrast, in the channel region, the silicon oxide layer 12 is thick and the electrostatic control by the back gate is weak. In addition, the electrostatic potential U is affected by the top gate voltages V _{TG and S} , and the electrostatic potential U is Fermi. It becomes a value closer to the level E _F.

As a result, the electrostatic potential U in the channel region becomes higher than the electrostatic potential U in the source region and the drain region, and the energy band bends accordingly. Then, the channel region is higher than the Fermi level E _F of the bottom energy E _C is the source region of the conduction band, the drain current does not flow, the transistor is turned off.

  Next, voltage application conditions for turning on the transistor will be described.

When the transistor is turned on, a positive voltage V _{TG, S} larger than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the gate electrode 22 that is the top gate electrode. Further, a positive voltage V _{BG, S} smaller than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the silicon substrate 10 as the back gate electrode, as in the off state. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 5, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, the phase change material layer 20 in the channel region is in a state where a sufficient electric field is applied to cause the topological phase transition, and the energy band gap is closed (topological insulator state).

In the source region and the drain region, since the silicon oxide layer 12 is thin and the phase change material layer 20 is close to the back gate electrode, electrostatic control by the back gate is strong, and the electrostatic potential U is Fermi quasi. much remains were lowered greater than E _F.

As a result, the energy barrier separating the source region and the drain region is lowered. Then, it is also bend energy E _C at the bottom of the conduction band in accordance with the electrostatic potential U, transmitting the burr and the Fermi level of the electrons of E _F from the drain region to the source region stick (or keeping the quantum coherence) As a result, drain current flows and the transistor is turned on.

As it just increases the drain voltage Vd, the Fermi level E _F of the drain region is depressed below the Fermi level E _F of the source region. As a result, electrons in the conduction band on the source region side can escape to the open energy level on the drain region side.

The channel region of the transistor due to the degeneracy extreme, the drain current is proportional to the difference in the Fermi level E _F the Fermi level E _F and the drain region of the source region. That is, the drain current increases in proportion to the drain voltage ratio. However, the Fermi level E _F of the drain region is smaller than the energy E _C at the bottom of the conduction band of the source region remote from the channel region, eventually, the drain current is more, not increasing (Non-Patent Document 6). That is, the drain current is saturated.

  As described above, the phase change channel transistor according to the present embodiment can saturate the drain current while maximizing the carrier mobility in the channel region without being obstructed by the dilemma of the conventional graphene transistor.

  Next, the method for fabricating the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

  First, the silicon oxide layer 12 having a film thickness of 400 nm is formed on the silicon substrate 10 whose plane orientation is the (100) plane by, for example, thermal oxidation for 400 minutes in an oxygen atmosphere at a temperature of 900 ° C., for example.

  Next, a photoresist film 14 is formed on the silicon oxide layer 12 by photolithography to cover a region (thick film portion 16A) where the gate electrode 22 is to be formed (FIG. 6A).

  Next, using the photoresist 14 as a mask, the silicon oxide layer 12 is etched by wet etching using, for example, a hydrofluoric acid aqueous solution, and the silicon oxide layer 12 film in a region (thin film portion 16B) not covered with the photoresist film 14 is etched. The thickness is reduced to about 10 nm, for example. For example, a thermal oxide film of about 390 nm can be etched by etching for about 10 minutes with an aqueous solution in which hydrofluoric acid, ammonium fluoride aqueous solution, and water are mixed at a composition of 1: 1: 4. In addition to leaving the oxide film having a thickness of about 10 nm, the thermal oxide film having a thickness of about 10 nm may be formed again by thermal oxidation after removing the whole thermal oxide film. (FIG. 6B).

  The film thicknesses of the thick film portion 16A and the thin film portion 16B of the silicon oxide layer 12 are desirably selected as appropriate in consideration of electrostatic influences from the gate electrode 22 and the silicon substrate 10 as the back gate. That is, as the film thickness of the thick film portion 16A is increased, the off state can be realized with a smaller gate voltage. Further, as the film thickness of the thin film portion 16B is reduced, electrostatic control from the back gate in the source region and the drain region becomes stronger.

  The reason why the silicon oxide layer 12 is removed by wet etching is that the inclined portion 16C is formed between the thick film portion 16A and the thin film portion 16B, so that the formation surface of the phase change material layer 20 formed in a later process is removed. This is to smooth the steps. For example, an inclined portion having an angle of about 30 degrees can be produced by etching for about 10 minutes with an aqueous solution in which hydrofluoric acid, an aqueous ammonium fluoride solution, and water are mixed at a composition of 1: 1: 4.

  Next, the photoresist 14 is removed by, for example, ashing (FIG. 6C).

Next, a phase change material layer 20 to be a channel is formed on the silicon oxide layer 12 provided with the thick film portion 12A, the thin film portion 12B, and the inclined portion 12C, for example, by sputtering (FIG. 7A). As the phase change material layer 20, for example, a <111> face axis of a crystal alloy layer (GeTe layer) made of germanium and tellurium and a crystal alloy layer (Sb ₂ Te ₃ layer) made of antimony and tellurium, respectively. It is possible to apply a superlattice structure laminated so that the c-axis and the c-axis are aligned.

For example, an RF sputtering apparatus in which targets made of pure metals of Ge, Sb, and Te are arranged, Ar is used as a sputtering gas under a pressure of 0.5 Pa, a power of 12.5 W is used as a Te target, and an Sb target is used. A 12.8 W power is appropriately applied to the Ge target, and a 45 W power is appropriately applied to the Ge target, and desired crystal alloy layers are sequentially stacked. It is desirable that the substrate temperature is appropriately selected according to the crystallization phase transition temperature of the crystal alloy layer to be formed. For example, since the crystallization phase transition temperature of Sb ₂ Te ₃ is about 100 ° C. and the crystallization phase transition temperature of GeTe is 230 ° C. at the maximum, the substrate temperature for fabricating the superlattice structure is at least 230 ° C. A high temperature is desirable.

For example, a 1 nm film having a 1: 1 composition of GeTe and a 6 nm film having a Sb ₂ Te ₃ composition (1 nm of Sb ₂ Te ₃ corresponds to 1QL) are repeatedly stacked. Thereby, the phase change material layer 20 having a superlattice structure composed of repetition of [(Ge ₂ Te ₂ ) / (Sb ₂ Te ₃ ) ₆ ] is formed.

  Next, the phase change material layer 20 is patterned into a predetermined shape by photolithography and etching (FIG. 7B). This patterning step may be appropriately performed as necessary, for example, when adjacent elements are separated when forming a plurality of transistors.

  Next, a conductive material to be an electrode, for example, a TiN layer having a film thickness of, for example, about 30 nm is formed on the phase change material layer 20 by, eg, sputtering. For example, the TiN layer is formed by performing sputtering at a power of 1 kW in a gas of 0.1 Pa in which Ar and nitrogen are mixed at 1: 1, for example, using an RF sputtering apparatus equipped with a pure metal Ti target.

Next, this TiN layer is patterned by photolithography and etching, and the phase change material layer 20 of the thin film portion 16B is sandwiched between the gate electrode 22 disposed on the phase change material layer 20 of the thick film portion 16A and the gate electrode 22. The source electrode 24 and the drain electrode 26 disposed on the upper side are formed (FIG. 7C). For etching the electrode layer, a dry etching method and a wet etching method can be selected and used as appropriate. For example, in dry etching, 30 nm of TiN can be etched by performing a treatment for about 30 seconds at 1500 W of RF plasma power in a mixed gas of HBr and Ar. Not only this composition but also gas such as Ar or Cl ₂ can be used. In the wet etching method, a mixed solution of HF and H ₂ O ₂ or the like can be used. By performing etching for about 15 minutes with a solution in which hydrofluoric acid, hydrogen peroxide, and water are mixed at a composition of about 1: 1: 10, 30 nm of TiN can be etched. The gate length of the gate electrode 22 is, for example, 100 nm, and the distance between the source electrode 24 and the drain electrode 26 is, for example, 500 nm.

  For example, as shown in FIG. 7C, if the source electrode 24 and the drain electrode 26 are formed in contact with the side surface portion on which the phase change material layer 20 is patterned, the alloy crystal layer having high conductivity is directly applied from the source side. Since carriers can be injected, a larger current can be expected.

  As described above, according to the present embodiment, the channel layer is formed of the phase change material in which the phase transition occurs between the normal insulator and the topological insulator, and the phase between the normal insulator and the topological insulator is formed. Since switching is performed using transition, both high channel mobility and high on / off ratio can be achieved. In addition, the drain current can be saturated.

[Second Embodiment]
A phase change channel transistor and a method of manufacturing the same according to the second embodiment will be described with reference to FIGS. Components similar to those of the phase change channel transistor and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 8 is a schematic cross-sectional view illustrating the structure of the phase change channel transistor according to the present embodiment. 9 and 10 are energy band diagrams illustrating the operation of the phase change channel transistor according to the present embodiment. 11 and 12 are process cross-sectional views illustrating the method of manufacturing the phase change channel transistor according to the present embodiment.

  First, the structure of the phase change channel transistor according to the present embodiment will be explained with reference to FIG.

  A silicon oxide layer 12 is formed on the silicon substrate 10. The silicon oxide layer 12 includes a thin film portion 16B, a thick film portion 16A disposed so as to sandwich the thin film portion 16B, and an inclined portion 16C disposed at a boundary portion between the thick film portion 16A and the thin film portion 16B. A silicon layer 12 is formed.

  A phase change material layer 20 is formed on the silicon oxide layer 12. A gate electrode 22 is formed on the phase change material layer 20 of the thin film portion 16B. In the region from the thin film portion 16B to the thick film portion 16A on the phase change material layer 20, a source electrode 24 and a drain electrode 26 are formed.

  The silicon substrate 10 is also used as a back gate electrode. Instead of the silicon substrate 10, a conductive layer formed on the silicon substrate 10 via an insulating layer may be formed. Providing the thick film portion 16A has an effect of weakening the electrostatic control by the back gate, and is therefore effective when performing element isolation between transistors.

  Next, the operation of the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

Here, the phase change material layer 20 is assumed to change from a normal insulator to a topological insulator by application of an external electric field. For example, in the phase change material layer 20 having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 6QL or more is used.

  First, voltage application conditions for turning off the transistor will be described.

When the transistor is turned off, a negative voltage V _{TG, S} smaller than a threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the gate electrode 22 that is the top gate electrode. Further, a positive voltage V _{BG, S} smaller than a threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the silicon substrate 10 that is the back gate electrode. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 9, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, the phase change material layer 20 is in a state where an electric field of a level that does not cause a topological phase transition is applied, and an energy band gap is opened (a state of a normal insulator).

  Due to the potential difference between the source electrode 24 and the drain electrode 26, the energy band is inclined from the source to the drain region as a whole, although a change in gradient due to the difference occurs due to a change in the thickness of the silicon oxide layer 10.

Band edge E _C and E _V by applying a voltage to the back gate 10 is lowered to a position sandwiching the Fermi level E _F in the band gap. The drain current does not flow due to the shape of this energy band, and the transistor is turned off.

  Next, voltage application conditions for turning on the transistor will be described.

When the transistor is turned on, a positive voltage V _{TG, S} larger than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the gate electrode 22 that is the top gate electrode. Further, a positive voltage V _{BG, S} smaller than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the silicon substrate 10 as the back gate electrode, as in the off state. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 10, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, the phase change material layer 20 in the channel region is in a state where an electric field sufficient to cause a topological phase transition is applied from the top gate and the back gate, and the energy band gap is closed (topological insulator state). It becomes. Further, since the phase change material layer 20 located on the boundary between the thick film portion and the thin film portion of the silicon oxide 10 is also subjected to a strong electric field resulting from a potential difference between the source electrode 24 and the drain electrode 26 and the back gate, A topological phase transition occurs and the band gap is closed.

As a result, the energy E _V energy E _C and the valence band at the bottom of the conduction band match. The source region, the channel region, the Fermi level E _F in the drain region is located on the bottom E _C of the conduction band, so that the inclination of the carrier electron energy band going down from source to drain. That is, a drain current flows and the transistor is turned on.

As in the case of slope off state of the energy band, by just increasing the drain voltage Vd, the Fermi level E _F of the drain region is pushed down below the Fermi level E _F of the source region This is what happened. As a result, electrons in the conduction band on the source region side can escape to energy levels not occupied on the drain region side.

  Since the channel region of this transistor is a degenerate limit, the drain current is proportional to the difference between the Fermi level of the source region and the Fermi level of the drain region. That is, the drain current increases in proportion to the drain voltage ratio.

  Thus, according to the phase change channel transistor according to the present embodiment, the carrier mobility in the channel region can be maximized without being obstructed by the dilemma as in the conventional graphene transistor.

  Next, the method for fabricating the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

  First, the silicon oxide layer 12 having a film thickness of 400 nm is formed on the silicon substrate 10 whose plane orientation is the (100) plane by, for example, thermal oxidation for 400 minutes in an oxygen atmosphere at a temperature of 900 ° C., for example.

  Next, a photoresist film 14 is formed on the silicon oxide layer 12 by photolithography so as to cover a region where the source electrode 24 and the drain electrode 26 are to be formed (thick film portion 16A) (FIG. 11A).

  Next, using the photoresist 14 as a mask, the silicon oxide layer 12 is etched by wet etching using, for example, a hydrofluoric acid aqueous solution, and the film thickness of the silicon oxide layer 12 in a region not covered with the photoresist film 14 (thin film portion 16B). Is thinned to about 10 nm, for example (FIG. 11B). For example, a thermal oxide film of about 390 nm can be etched by etching for about 10 minutes with an aqueous solution in which hydrofluoric acid, ammonium fluoride aqueous solution and water are mixed at a composition of 1: 1: 4. In addition to leaving the oxide film having a thickness of about 10 nm, the thermal oxide film having a thickness of about 10 nm may be formed again by thermal oxidation after removing the whole thermal oxide film.

  Next, the photoresist 14 is removed by, for example, ashing (FIG. 11C).

  Next, a phase change material layer 20 to be a channel is formed on the silicon oxide layer 12 provided with the thick film portion 12A, the thin film portion 12B, and the inclined portion 12C, for example, by sputtering (FIG. 12A).

  Next, the phase change material layer 20 is patterned into a predetermined shape by photolithography and etching (FIG. 12B). This patterning step may be appropriately performed as necessary, for example, when adjacent elements are separated when forming a plurality of transistors.

  Next, a conductive material to be an electrode, for example, a TiN layer having a film thickness of, for example, about 30 nm is formed on the phase change material layer 20 by, eg, sputtering. For example, the TiN layer is formed by performing sputtering at a power of 1 kW in a gas of 0.1 Pa in which Ar and nitrogen are mixed at 1: 1, for example, using an RF sputtering apparatus equipped with a pure metal Ti target.

Next, this TiN layer is patterned by photolithography and etching, and the gate electrode 22 disposed on the phase change material layer 20 of the thin film portion 16B and the phase change material layer 20 in the region extending from the thin film portion 16B to the thick film portion 16A. The source electrode 24 and the drain electrode 26 arranged on the upper side are formed (FIG. 12C). For etching the electrode layer, a dry etching method and a wet etching method can be selected and used as appropriate. For example, in dry etching, 30 nm of TiN can be etched by performing a treatment for about 30 seconds at 1500 W of RF plasma power in a mixed gas of HBr and Ar. Not only this composition but also gas such as Ar or Cl ₂ can be used. In the wet etching method, a mixed solution of HF and H ₂ O ₂ or the like can be used. By performing etching for about 15 minutes with a solution in which hydrofluoric acid, hydrogen peroxide, and water are mixed at a composition of about 1: 1: 10, 30 nm of TiN can be etched. The gate length of the gate electrode 22 is, for example, 100 nm, and the distance between the source electrode 24 and the drain electrode 26 is, for example, 500 nm.

  As described above, according to this embodiment, the drain current cannot be saturated, but the channel layer is formed of the phase change material in which the phase transition occurs between the normal insulator and the topological insulator, and the normal insulation is performed. Since switching is performed using the phase transition between the body and the topological insulator, both high channel mobility and high on / off ratio can be achieved.

[Third Embodiment]
A phase change channel transistor and a method of manufacturing the same according to the third embodiment will be described with reference to FIGS. Components similar to those of the phase change channel transistor and the manufacturing method thereof according to the first and second embodiments illustrated in FIGS. 1 to 12 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 13 is a schematic cross-sectional view illustrating the structure of the phase change channel transistor according to the present embodiment. 14 and 15 are energy band diagrams illustrating the operation of the phase change channel transistor according to the present embodiment.

  First, the structure of the phase change channel transistor according to the present embodiment will be explained with reference to FIG.

  A silicon oxide layer 12 is formed on the silicon substrate 10. The silicon oxide layer 12 includes a thin film portion 16B, a thick film portion 16A disposed so as to sandwich the thin film portion 16B, and an inclined portion 16C disposed at a boundary portion between the thick film portion 16A and the thin film portion 16B. A silicon layer 12 is formed.

  A phase change material layer 20 is formed on the silicon oxide layer 12. In the region from the thin film portion 16B to the thick film portion 16A on the phase change material layer 20, a source electrode 24 and a drain electrode 26 are formed.

  As described above, the phase change channel transistor according to the present embodiment is the second embodiment shown in FIG. 8 except that the gate electrode 22 is not provided between the source electrode 24 and the drain electrode 26 as shown in FIG. This is the same as the phase change channel transistor according to the form.

  In the phase change channel transistor shown in FIG. 13, the thick film portion 16A and the thin film portion 16B are provided in the silicon oxide layer 12. However, the thickness of the silicon oxide layer 12 is constant with the thickness of the thin film portion 16B. Also good.

  Next, the operation of the phase change channel transistor according to the present embodiment will be explained with reference to FIGS.

Here, the phase change material layer 20 is assumed to change from a normal insulator to a topological insulator by application of an external electric field. For example, in the phase change material layer 20 having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 6QLs or more is used.

  First, voltage application conditions for turning off the transistor will be described.

When the transistor is turned off, a positive voltage smaller than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase change is applied to the silicon substrate 10 that is the back gate electrode. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region is as illustrated in FIG. In Figure 14, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, the phase change material layer 20 is in a state where an electric field of a level that does not cause a topological phase transition is applied, and an energy band gap is opened (a state of a normal insulator). Further, due to the potential difference between the source electrode 24 and the drain electrode 26, the energy band is inclined from the source to the drain region as a whole, although the change in the gradient due to the difference occurs due to the change in the thickness of the silicon oxide layer 10. .

Band edge E _C by applying a voltage to the back gate _10, E _V is lowered to a position sandwiching the Fermi level E _F in the band gap. Due to the shape of this energy band, no current flows between the source and the drain, and the transistor is turned off.

  Next, voltage application conditions for turning on the transistor will be described.

When the transistor is turned on, a positive voltage larger than the threshold voltage V _TG ^{C at} which the phase change material layer 20 causes a topological phase transition is applied to the back gate electrode 10. The source electrode 24 is grounded, and a positive voltage is applied to the drain electrode 26 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region is as shown in FIG. In Figure 15, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

  First, since a strong electric field resulting from a potential difference between the source electrode 24 and the drain electrode 26 and the back gate is applied to the phase change material layer 20 in the channel region, a topological phase transition occurs and the energy band gap is closed. (State of topological insulator).

As a result, the energy E _V energy E _C and the valence band at the bottom of the conduction band match. The source region, the channel region, the drain region, the Fermi level E _F is higher than the energy E _C at the bottom of the conduction band. The slope of the carrier electron energy band can then be lowered from the source to the drain. That is, a drain current flows and the transistor is turned on.

As in the case of slope off state of the energy band, by just increasing the drain voltage Vd, the Fermi level E _F of the drain region is pushed down below the Fermi level E _F of the source region This is what happened. As a result, electrons in the conduction band on the source region side can escape to energy levels not occupied on the drain region side.

  Since the channel region of this transistor is a degenerate limit, the drain current is proportional to the difference between the Fermi level of the source region and the Fermi level of the drain region. That is, the drain current increases in proportion to the drain voltage ratio.

  In the phase change channel transistor according to the present embodiment, the drain current cannot be saturated, but the phase change material layer 20 can be operated as a switching element by transitioning between a normal insulator and a topological insulator. it can.

  The manufacturing method of the phase change channel transistor according to the present embodiment is the same as the manufacturing method of the phase change channel transistor according to the second embodiment except that the gate electrode 22 is not formed.

  As described above, according to the present embodiment, the channel layer is formed of the phase change material in which the phase transition occurs between the normal insulator and the topological insulator, and the phase between the normal insulator and the topological insulator is formed. Since switching is performed using transition, both high channel mobility and high on / off ratio can be achieved.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, the phase change material mainly including Ge, Te, or Bi is exemplified as the phase change material in which the transition of the topological phase is caused by the application of the electric field. However, the phase change material applicable to the above embodiment is exemplified. However, the present invention is not limited to this. Research on topological insulators has just begun, and various materials may be found in the future. Any material that undergoes a phase transition between a normal insulator and a topological insulator by application of an electric field can be used instead of a phase change material mainly composed of Ge, Te, or Bi.

  In the first and second embodiments, the thickness of the silicon oxide layer 12 is changed. However, the thickness of the silicon oxide layer 12 is constant, and the gate electrode 22, the source electrode 24, the drain electrode 26, and the back gate are used. A similar effect may be obtained depending on the applied voltage.

In the above embodiment, a normally-off type transistor has been described. However, a normally-on type transistor can be formed in the same manner. For example, instead of using the phase change material layer 20 that changes from a normal insulator to a topological insulator by applying an external electric field, the phase change material layer that changes from a topological insulator to a normal insulator by applying an external electric field. When 20 is used, an on-state transistor can be realized before a large positive top gate voltage is applied. For example, in the phase change material layer 20 having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 1QLs or more and 5QLs or less may be used.

  In addition, the constituent materials, manufacturing conditions, and the like of the respective components of the phase change channel transistor described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art. is there.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Silicon oxide layer 14 ... Photoresist film 16A ... Thick film part 16B ... Thin film part 16C ... Inclined part 20 ... Phase change material layer 22, 22A, 22B, 22C ... Gate electrode 24 ... Source electrode 26 ... Drain electrode

Claims (9)

A channel layer including a phase change material in which a topological phase transition occurs by applying an electric field;
A source electrode and a drain electrode connected to the channel layer;
An insulating film formed on the first surface of the channel layer;
A phase change channel transistor, comprising: a first gate electrode formed on the insulating film. The phase change channel transistor of claim 1.
A phase change channel transistor, further comprising a second gate electrode formed on a second surface of the channel layer between the source electrode and the drain electrode. The phase change channel transistor of claim 2,
The film thickness of the insulating film between the first gate electrode and the second gate electrode is equal to the film thickness of the insulating film between the first gate electrode and the source electrode and the first gate electrode. A phase change channel transistor, wherein the phase change channel transistor is thicker than a thickness of the insulating film between a gate electrode and the drain electrode. The phase change channel transistor of claim 2,
The film thickness of the insulating film between the first gate electrode and the second gate electrode is equal to the film thickness of the insulating film between the first gate electrode and the source electrode and the first gate electrode. A phase change channel transistor characterized by being thinner than the thickness of the insulating film between the gate electrode and the drain electrode. The phase change channel transistor according to any one of claims 1 to 4,
The phase change material is characterized in that the phase change material transitions from a normal insulator to a topological insulator by applying an electric field. The phase change channel transistor according to any one of claims 1 to 4,
The phase change material is characterized in that the phase change material transitions from a topological insulator to a normal insulator by applying an electric field. The phase change channel transistor according to any one of claims 1 to 6,
The channel layer has a stacked structure of a first crystal layer mainly composed of Te or Bi and a second crystal layer composed mainly of Te or Bi and having a composition different from that of the first crystal layer. Phase change channel transistor characterized by. A channel layer including a phase change material in which topological phase transition is caused by application of an electric field; a source electrode and a drain electrode connected to the channel layer; an insulating film formed on a first surface of the channel layer; A phase change channel transistor having a first gate electrode formed on an insulating film and a second gate electrode formed on a second surface of the channel layer between the source electrode and the drain electrode Driving method,
By changing the phase change material of the channel layer between a normal insulator and a topological insulator by an electric field applied between the first gate electrode and the second gate electrode, A method for driving a phase change channel transistor, comprising switching a current flowing between a source electrode and the drain electrode. The method of driving a phase change channel transistor according to claim 8,
A method of driving a phase-change channel transistor, wherein field effect doping is performed on the channel layer by an electric field applied between the source and drain electrodes and the first gate electrode.

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