JPWO2013030865A1 - Thin film transistor array manufacturing method, thin film transistor array, and display device - Google Patents

Abstract

The thin film transistor array manufacturing method of the present invention includes a third step of forming a gate insulating layer (13) on a plurality of gate electrodes (12), and an amorphous silicon layer (14) on the gate insulating layer (13). A fourth step of forming, a fifth step of crystallizing the amorphous silicon layer (14) to produce a crystalline silicon layer (15), and a sixth step of forming the source and drain electrodes (18). In the third step, the thickness of the gate insulating layer (13) on the plurality of gate electrodes (12) is set to the light absorption rate of the amorphous silicon layer (14) on the gate electrode (12) with respect to the laser light. And an equivalent oxide film thickness of the gate insulating layer (13) are formed in a film thickness range in a positive correlation. In the fourth step, the amorphous silicon layers (14) on the plurality of gate electrodes (12) are formed. The film thickness of the amorphous silicon layer (14) Variation of light absorption rate with respect to the thickness change is formed in a thickness range of the area is within a predetermined range from the first reference.

Description

  The present invention relates to a method for manufacturing a thin film transistor array, a thin film transistor array, and a display device.

  For example, there is a thin film transistor (TFT) array used for a liquid crystal panel or an organic EL panel. The channel portion of each thin film transistor constituting the thin film transistor array is formed of a-Si that is amorphous silicon or Poly-Si that is crystalline and polycrystalline silicon. For the crystalline silicon layer (Poly-Si layer) in the channel portion of the thin film transistor, generally, after forming an amorphous silicon layer (a-Si layer), laser light such as excimer is applied to the amorphous silicon layer. It is formed by irradiating and instantaneously raising the temperature to crystallize.

  The structure of the thin film transistor includes a bottom gate structure in which the gate metal is disposed on the substrate side when viewed from the x-Si (x is a or poly) of the channel portion, and the gate metal and the source / drain metal of the channel portion. There is a top gate structure arranged in the direction opposite to the substrate as viewed from x-Si. The bottom gate structure is mainly used in an a-Si TFT having a channel portion formed of an amorphous silicon layer, and the top gate structure is a Poly-Si having a channel portion formed of a crystalline silicon layer. Mainly used in TFT. Note that a bottom gate structure is generally used as a structure of a thin film transistor included in a liquid crystal panel or an organic EL panel used in a large-area display device.

  Furthermore, there is a case where a Poly-Si TFT is used in a bottom gate structure, and in that case, there is an advantage that a manufacturing cost can be suppressed. In such a bottom-gate Poly-Si TFT, the amorphous silicon layer is irradiated with a laser and crystallized to form a crystalline silicon layer. In this method (laser annealing crystallization method), the amorphous silicon layer is crystallized by heat based on laser light irradiation.

  In addition, for example, uniform characteristics are required for each thin film transistor constituting a thin film transistor array used in an organic EL panel. In order to meet this demand, a technique for forming a crystalline silicon layer having uniform crystallinity on the entire surface of the substrate has been developed. However, in the case of manufacturing a bottom gate thin film transistor by the laser annealing crystallization method using the developed formation technique, a disadvantage (problem) occurs. The reason will be described below.

  When a thin film transistor having a bottom gate structure is manufactured, when the amorphous silicon layer is crystallized by laser annealing, the amorphous silicon layer and the gate in a region where the gate electrode is generally present (referred to as a “first region”) are formed. The light absorption rate with respect to the laser beam used for laser annealing differs from the amorphous silicon layer in the region where no electrode exists (referred to as “second region”). This is because the effect of multiple interference of laser light in a multilayer thin film composed of an amorphous silicon layer and a gate insulating layer changes depending on the presence or absence of a gate electrode.

  If there is a difference in the light absorption rate of the amorphous silicon layer in the two regions, a difference in heat generation temperature occurs in the amorphous silicon layer in the two regions immediately after laser irradiation, resulting in uneven temperature distribution. Become. The crystallinity of the crystalline silicon layer obtained by laser annealing crystallization strongly depends on the heat generation temperature of the amorphous silicon layer by laser irradiation. Therefore, the heat generation temperature becomes nonuniform in the amorphous silicon layers in the two regions, and the crystallinity of the obtained crystalline silicon layer becomes nonuniform.

  For example, Patent Document 1 discloses a technique for solving this problem. In Patent Document 1, the thicknesses of the gate insulating layer and the amorphous silicon layer are adjusted so that the light absorption rate of the amorphous silicon layer in the first region is equal to the light absorption rate of the amorphous silicon layer in the second region. A technique for forming such a film thickness structure is disclosed. Thereby, the non-uniformity of the heat generation temperature of the amorphous silicon layer between both regions immediately after laser irradiation is reduced as much as possible, and a crystalline silicon thin film having uniform crystallinity is formed on the entire surface of the substrate.

  However, the technique disclosed in Patent Document 1 has a problem that a crystalline silicon thin film having uniform crystallinity cannot be formed on the entire surface of the substrate in the following cases. The reason will be described below.

  In general, in a manufacturing process of a thin film transistor array used in a display device, an amorphous silicon layer and a gate insulating layer are formed by a process such as plasma-enhanced chemical vapor deposition (PECVD). The The thin film formed by such a process has a certain degree of film thickness variation within the substrate surface, although it depends on the film forming conditions.

  In this case, that is, when a variation in film thickness occurs in the amorphous silicon layer or the gate insulating layer within the substrate surface, the variation in film thickness (target) depends on the wavelength of the laser beam used for laser annealing. It is inevitable that variations in the light absorptance occur corresponding to the amount of film thickness deviation from the film thickness.

  Even if the amorphous silicon layer and the gate insulating layer are formed aiming at a film thickness that makes the light absorption rate of the amorphous silicon layer equal in the first region and the second region, the film is not formed in the substrate plane. Thickness variation occurs. As a result, the light absorption rate of the amorphous silicon layer in the first region and the second region cannot be made equal over the entire surface of the substrate.

  In other words, when the amorphous silicon layer and the gate insulating layer are formed by a process such as plasma-assisted chemical vapor deposition, the first region and the second region are amorphous over the entire surface of the substrate in the laser annealing step. There is a problem that the heat generation temperature of the crystalline silicon layer cannot be made uniform, and the crystallinity of the obtained crystalline silicon layer becomes nonuniform within the substrate surface.

  Therefore, for this reason, at least attention is paid to the region (first region) where the channel of the thin film transistor is formed, and a technique for making the crystallinity of the crystalline silicon layer formed there uniform over the entire surface of the substrate Is disclosed (for example, Patent Document 2).

  In Patent Document 2, first crystallinity of a crystalline silicon layer formed on a first region is reduced with respect to film thickness variations of an amorphous silicon layer and a gate insulating layer so that the entire substrate has uniform crystallinity. A film thickness condition that minimizes the variation in the light absorption rate of the amorphous silicon layer on the region is adopted. By adopting such a film thickness condition, the heat generation in laser annealing of the amorphous silicon layer on the first region and the film thickness variation of the amorphous silicon layer with respect to the crystallinity of the obtained crystalline silicon layer. In addition, the influence of the film thickness variation of the gate insulating layer can be minimized.

JP 2007-220918 A Japanese Patent Application Laid-Open No. 2011-066243

  However, even if the technique disclosed in Patent Document 2 is used, there are the following problems. That is, even if the crystallinity of the crystalline silicon layer formed on the first region can be made uniform over the entire surface of the substrate, the characteristics of the thin film transistor having the channel as a channel, particularly the on-characteristics, can be realized. I can't.

  This is because the on-characteristic of the thin film transistor depends not only on the crystallinity of the crystalline silicon layer serving as the channel of the thin film transistor but also on the gate capacitance of the gate insulating layer. That is, fluctuations in the film thickness of the gate insulating layer in the substrate surface cause variations in the gate capacitance of the gate insulating layer, so that even if the crystalline silicon layer serving as a channel has a uniform crystallinity in each thin film transistor, When the gate capacitance fluctuates, the on characteristics of each thin film transistor vary.

  FIG. 1 is a diagram illustrating an example of an in-plane distribution of on-current of each thin film transistor in a thin film transistor array. Here, the thin film transistor array shown in FIG. 1 is constituted by a bottom gate TFT using a crystalline silicon layer formed by a laser annealing crystallization method, and the substrate surface (in the drawing) of the thin film transistor array has 224 × 224. The thin film transistor is used. In FIG. 1, the distribution of the on-current in the substrate surface is visualized by expressing the magnitude of the on-current of each thin film transistor in the thin film transistor array in shades. The unit of the on-current is standardized and shown in an arbitrary unit.

  As can be seen from FIG. 1, the on-current of the thin film transistor is non-uniform in the substrate surface and has uneven characteristics. As described above, the unevenness of the ON characteristics is caused by the fact that the thickness of the gate insulating layer varies depending on the position in the substrate surface of the thin film transistor array, and the capacitance of the gate insulating layer on the gate electrode changes accordingly. Yes.

  In FIG. 1, since the thickness of the gate insulating layer in the central portion in the substrate surface of the thin film transistor array is thicker than that in the peripheral portion, the capacity of the gate insulating layer is reduced. Therefore, the on-characteristics are degraded in the central region. That is, in FIG. 1, the central region where the on-characteristics are reduced appears as unevenness.

  Further, the film thickness variation of the channel constituent layer of the thin film transistor becomes increasingly difficult to control as the substrate used for panel fabrication becomes larger. Therefore, with an increase in the size of the display device, variation in gate insulating capacitance of each thin film transistor in the thin film transistor array used in the display device increases. Even if a crystalline silicon layer with uniform crystallinity can be formed over the entire surface of the substrate, the variation in on-state characteristics of the thin film transistor due to the variation in gate capacitance becomes more conspicuous as the display device becomes larger. That is, when a display device having a larger area is manufactured, unevenness in image quality due to variation in on-state characteristics of thin film transistors becomes a more serious problem.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a thin film transistor array, a thin film transistor array, and a display device using the thin film transistor array, which can be configured with thin film transistors having uniform on characteristics. And

  In order to achieve the above object, a thin film transistor array manufacturing method according to an aspect of the present invention includes a first step of preparing a substrate, a second step of forming a plurality of gate electrodes on the substrate, and the plurality of the plurality of gate electrodes. A third step of forming a gate insulating layer on the gate electrode; a fourth step of forming an amorphous silicon layer on the gate insulating layer; and the amorphousness using laser light emitted from a laser. A fifth step of crystallizing the silicon layer to form a crystalline silicon layer; and a sixth step of forming a source electrode and a drain electrode in a region on the crystalline silicon layer in each of the plurality of gate electrodes. And in the third step, the film thickness of the gate insulating layer on the plurality of gate electrodes is determined based on the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser light and the gate insulation. In the fourth step, the thickness of the amorphous silicon layer on the plurality of gate electrodes in the fourth step is changed to the amorphous thickness of the amorphous oxide layer. The variation of the light absorptance with respect to the change in film thickness of the conductive silicon layer is formed in a film thickness range in a region within a predetermined range from the first reference.

  According to the present invention, it is possible to realize a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array that can be configured with thin film transistors having uniform on characteristics.

  Specifically, an amorphous silicon layer on the gate electrode region corresponding to each thin film transistor constituting the array on the substrate and a gate insulating layer are formed so that each film thickness satisfies a predetermined condition. By using a laser with a wavelength in the visible light region, a crystal whose crystallinity has fluctuated so as to offset the influence of the increase or decrease of the gate capacitance corresponding to the increase or decrease of the gate capacitance of the gate insulating layer on the first region A thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array can be realized in which a thin silicon layer is formed and the thin film transistor array formed on the entire surface of the substrate has uniform thin film transistor ON characteristics.

FIG. 1 is a diagram illustrating an example of an in-plane distribution of on-current of each thin film transistor in a thin film transistor array. FIG. 2 is a cross-sectional view showing the structure of the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 3 is a diagram showing an equivalent circuit of a unit cell of the thin film transistor array according to the embodiment of the present invention. FIG. 4 is a flowchart showing a manufacturing process of a thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5A is a cross-sectional view for explaining a method of manufacturing a thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5B is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5C is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5D is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5E is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5F is a cross-sectional view for explaining the method of manufacturing the thin film transistor that constitutes the thin film transistor array according to the embodiment of the present invention. FIG. 5G is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5H is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5I is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 5J is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention. FIG. 6 is a diagram schematically showing laser annealing in S14 of FIG. FIG. 7 is a diagram showing an example of a cross section of an equivalent circuit of a unit repeating cell of the thin film transistor array according to the embodiment of the present invention. FIG. 8 is a diagram for explaining the amplitude transmittance and the calculation method of the amplitude transmittance. FIG. 9 is a diagram for explaining that there is a film thickness range suitable for the film thickness of the amorphous silicon layer when the crystalline silicon layer is formed by the laser annealing crystallization method. FIG. 10A is a diagram showing that there is a preferable film thickness range for the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method. FIG. 10B is a diagram for illustrating that there is a preferable thickness range for the thickness of the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method. FIG. 11 is a diagram showing a specific example of a film thickness range suitable for the film thickness of the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method. FIG. 12A is a diagram showing the relationship between the capacitance formed by the varying thickness of the gate insulating layer and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under condition 1. FIG. 12B is a diagram showing the relationship between the capacitance formed by the varying gate insulating film thickness and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under condition 2. FIG. 12C is a diagram showing the relationship between the capacitance formed by the varying thickness of the gate insulating layer and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under Condition 3. FIG. 13A is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under Condition 1. FIG. FIG. 13B is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under condition 2. FIG. 13C is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under condition 3. FIG. 14A is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under condition 1. FIG. 14B is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under condition 2. FIG. 14C is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under Condition 3. FIG. 15 is a diagram showing an example of a display device including the thin film transistor array of the present invention.

  The thin film transistor array manufacturing method according to the first aspect includes a first step of preparing a substrate, a second step of forming a plurality of gate electrodes on the substrate, and forming a gate insulating layer on the plurality of gate electrodes. A third step, a fourth step of forming an amorphous silicon layer on the gate insulating layer, and crystallizing the amorphous silicon layer using laser light emitted from a laser to form crystalline silicon A fifth step of generating a layer, and a sixth step of forming a source electrode and a drain electrode in a region on the crystalline silicon layer in each of the plurality of gate electrodes, and in the third step, the plurality of steps The film thickness of the gate insulating layer on the gate electrode is positively correlated with the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser beam and the equivalent oxide thickness of the gate insulating layer. is there In the fourth step, the film thickness of the amorphous silicon layer on the plurality of gate electrodes is changed to the light absorption rate with respect to the film thickness change of the amorphous silicon layer. Is formed in a film thickness range in a region where the fluctuation is within a predetermined range from the first reference.

Here, the equivalent oxide film thickness is a value obtained by converting the physical thickness of the gate insulating layer into an electrical film thickness equivalent to the SiO ₂ film.

  According to this aspect, the light absorptance with respect to the laser beam used for laser annealing of the amorphous silicon layer corresponding to the region on the gate electrode of each thin film transistor constituting the thin film transistor array, and similarly on each gate electrode. Even if the correlation with the gate insulating layer capacitance corresponding to this region fluctuates with respect to the target film thickness, the negative relationship is obtained. Due to this relationship, even if the film thickness of the gate insulating layer constituting the thin film transistor array fluctuates with respect to the target film thickness, it corresponds to the distribution of the corresponding gate insulating layer capacitance on each gate electrode in the substrate surface. Specifically, it is possible to form a crystalline silicon layer having such a distribution that the crystallinity of the crystalline silicon layer formed on the gate electrode is lowered by laser annealing crystallization as the gate insulating layer capacity increases. It becomes. In addition, a thin film transistor array is formed using a crystalline silicon layer in which the distribution of crystallinity is changed so as to have a certain relationship with the gate insulating layer capacitance in the substrate surface. As a result, the variation in the on-characteristics of the thin film transistor caused by the variation in the gate insulating layer capacitance due to the variation in the thickness of the gate insulating layer of each thin film transistor is reduced by the crystalline silicon layer of the channel layer of the thin film transistor in which the crystallinity is controlled. It is possible to achieve an effect that is offset by.

  In the method of manufacturing the thin film transistor array according to the second aspect, the laser is constituted by a solid-state laser device.

  As a method of manufacturing the thin film transistor array according to the third aspect, the laser is constituted by a laser device using a semiconductor laser element.

  As a method of manufacturing the thin film transistor array according to the fourth aspect, in the fifth step, the fluctuation of the irradiation energy density of the laser light on the amorphous silicon layer is less than about 5%.

  In the method of manufacturing the thin film transistor array according to the fifth aspect, the wavelength range of the laser is 400 nm or more and 600 nm or less.

  As a method of manufacturing a thin film transistor array according to a sixth aspect, in the fourth step, the film thickness of the amorphous silicon layer is set as a film thickness range of a region within a predetermined range from the first reference. The absorptance of the laser light wavelength λ of the amorphous silicon layer normalized by the optical film thickness of the gate insulating layer normalized by the laser light wavelength λ was normalized by the laser light wavelength λ, The amorphous silicon layer is formed in a film thickness range in which the differential coefficient when differentiated by the optical film thickness is −5 or more and +5 or less.

  As a method of manufacturing a thin film transistor array according to a seventh aspect, in the fourth step, the amorphous silicon layer has an average film thickness of the amorphous silicon layer on the plurality of gate electrodes expressed by the following formula: It is formed so as to be included in the range represented by 1).

Formula 1) 0.426 ≦ n _a-Si × d _a-Si / λ _Si ≦ 0.641, where d _a-Si represents the average thickness of the amorphous silicon layer, and λ _Si represents the laser beam. The wavelength represents the wavelength, and na _-Si represents the refractive index of the amorphous silicon layer with respect to the laser beam having the wavelength λ.

  In the method of manufacturing the thin film transistor array according to the eighth aspect, in the third step, the gate insulating layer is formed such that the extinction coefficient of the gate insulating layer with respect to the wavelength of the laser light is 0.01 or less.

  In the thin film transistor array manufacturing method according to the ninth aspect, the gate insulating layer is a silicon oxide film.

  In the method of manufacturing the thin film transistor array according to the tenth aspect, the gate insulating layer is a silicon nitride film.

  In the manufacturing method of the thin film transistor array according to the eleventh aspect, the gate insulating layer is composed of a laminated film of a silicon oxide film and a silicon nitride film.

  As a method of manufacturing a thin film transistor array according to a twelfth aspect, in the third step, the gate insulating layer has an average film thickness of the gate insulating layer on the plurality of gate electrodes expressed by the following formula 2): Or a range represented by the following formula 3).

Formula 2) 0.44 ≦ n _GI × d _GI /λ≦0.74, Formula 3) 0.96 ≦ n _GI × d _GI /λ≦1.20, where d _GI is the average of the gate insulating layer The film thickness is represented, λ represents the wavelength of the laser beam, and n _GI represents the refractive index of the gate insulating layer with respect to the laser beam having the wavelength λ.

  According to a thirteenth aspect of the thin film transistor array manufacturing method, in the third step, the gate insulating layer has an average film thickness of the gate insulating layer on the plurality of gate electrodes expressed by the following formula 4): Or a range represented by the following formula 5).

Formula 4) 0.47 ≦ n _GI × d _GI /λ≦0.62, Formula 5) 1.04 ≦ n _GI × d _GI /λ≦1.13, where d _GI is the average of the gate insulating layer The film thickness is represented, λ represents the wavelength of the laser beam, and n _GI represents the refractive index of the insulating layer with respect to the laser beam having the wavelength λ.

  As a method of manufacturing a thin film transistor array according to a fourteenth aspect, an average film thickness of the silicon oxide film on the plurality of gate electrodes and an average film thickness of the silicon nitride film on the plurality of gate electrodes are expressed by the following formula: It is formed so as to be included in the region represented by 6) and 7) or the region represented by 8) and 9).

Formula 6) Y ≧ −1070X ⁶ + 1400X ⁵ −688X ⁴ + 153X ³ −12.90X ² −1.02X + 0.439, Formula 7) Y ≦ 49.9X ⁶ −131X ⁵ + 127X ⁴ −56.8X ³ + 11.8X ² −2.01X + 0.736, Formula 8) Y ≧ −7.34X ⁶ + 8.48X ⁵ + 8.65X ⁴ −16.0X ³ + 7.24X ² −2.04X + 0.961, Formula 9) Y ≦ −3.75X ^{6 + 11.8X 5 -13.1X 4 + 6.09X} 3 -1.12X 2 -0.87X + 1.20, _{where, X = d SiO × n SiO} / λ, _{and, Y = d SiN × n SiN} / λ in and, d _SiO represents an average film thickness of the silicon oxide film, d _SiN represents the average thickness of the silicon nitride film, lambda represents the wavelength of laser light, the wavelength of the n _SiO is the silicon oxide film lambda It represents a refractive index with respect to the laser beam, n _SiN represents the refractive index with respect to laser light having a wavelength λ of the silicon nitride film.

  According to a fifteenth aspect of the thin film transistor array manufacturing method, in the third step, the gate insulating layer is formed by forming an average film thickness of the silicon oxide film on the plurality of gate electrodes and the nitriding on the plurality of gate electrodes. The average film thickness of the silicon film is formed so as to be included in the region represented by the following formula 10) and formula 11) or the region represented by formula 12) and formula 13).

Formula 10) Y ≧ −132.6X ⁶ + 181X ⁵ −93.8X ⁴ + 21.3X ³ −1.33X ² −1.04X + 0.473, Formula 11) Y ≦ 23.7X ⁶ −4.56X ⁵ −35. 4X ⁴ + 27.2X ³ −5.75X ² −0.973X + 0.619, Formula 12) Y ≧ 7.46X ⁶ −32.4X ⁵ + 50.8X ⁴ −35.7X ³ + 11.0X ² −2.20X + 1. 04, formula 13) Y ≦ −5.34X ⁶ + 16.7X ⁵ −18.7X ⁴ + 9.18X ³ −1.96X ² −0.821X + 1.13, where X = d _SiO × n _{SiO 2} / λ, and a _{Y = d SiN × n SiN /} λ, d SiO represents an average film thickness of the silicon oxide _{film, d SiN} represents the average thickness of the silicon nitride film, lambda represents the wavelength of laser light , N _SiO is the oxidation The refractive index of the silicon film with respect to the laser beam having the wavelength λ is represented, and n _SiN represents the refractive index of the silicon nitride film with respect to the laser beam having the wavelength λ.

  As a method of manufacturing a thin film transistor array according to a sixteenth aspect, the second step includes a step of forming an undercoat layer made of a transparent insulating film on the substrate and a step of forming a plurality of gate electrodes on the undercoat layer. Including.

  A thin film transistor array according to a seventeenth aspect is formed on a substrate, a plurality of gate electrodes formed on the substrate, a gate insulating layer commonly formed on the plurality of gate electrodes, and the gate insulating layer. A crystalline silicon layer; and a source electrode and a drain electrode formed in a region on the crystalline silicon layer of each of the plurality of gate electrodes, and the crystalline silicon layer is formed on the gate insulating layer. The amorphous silicon layer is formed by crystallization using laser light emitted from a laser, and the film thickness of the gate insulating layer on the plurality of gate electrodes is set to be amorphous on the gate electrodes. The amorphous silicon on the plurality of gate electrodes is formed in a film thickness range in a region where the light absorption rate of the crystalline silicon layer with respect to the laser beam and the equivalent oxide film thickness are positively correlated. The thickness variation of the light absorption rate with respect to the thickness change of the amorphous silicon layer is formed in a thickness range of a region of the first reference within a predetermined range.

  In the thin film transistor array of the eighteenth aspect, the average crystal grain size of the crystalline silicon layer on the gate electrode has a negative correlation with the gate capacitance of the gate insulating layer on the gate electrode. .

In the thin film transistor array of the nineteenth aspect, the half-value width of the Raman scattering spectrum peak near 520 cm ⁻¹ in the crystalline silicon layer on the gate electrode is equal to the gate capacitance of the gate insulating layer on the gate electrode. It has a positive correlation.

  A display device according to a twentieth aspect is a display device including a liquid crystal panel or an EL panel, comprising the thin film transistor array according to any of the seventeenth to nineteenth aspects, wherein the thin film transistor array is the liquid crystal panel or the EL panel. Drive.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a cross-sectional view showing a thin film transistor constituting a thin film transistor array used in the display device according to the embodiment of the present invention.

  A thin film transistor 100 illustrated in FIG. 2 is a bottom gate thin film transistor, and includes a substrate 10, an undercoat layer 11, a gate electrode 12, a gate insulating layer 13, a crystalline silicon layer 15, and an amorphous silicon layer 16. And an n + silicon layer 17 and source / drain electrodes 18.

  The substrate 10 is an insulating substrate made of, for example, transparent glass or quartz.

  The undercoat layer 11 is formed on the substrate 10 and includes, for example, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, and a stacked layer thereof. Here, the undercoat layer 11 is preferably made of silicon oxide (SiOx) of 1.5 <x <2.0 and having a thickness of 300 nm to 1500 nm. A more preferable thickness range of the undercoat layer 11 is 500 nm or more and 1000 nm or less. This is because if the thickness of the undercoat layer 11 is increased, the thermal load on the substrate 10 can be reduced, but if it is too thick, film peeling or cracking occurs.

  The gate electrode 12 is formed on the undercoat layer 11 and is typically made of a metal such as molybdenum (Mo) or a metal such as Mo alloy (for example, MoW (molybdenum / tungsten alloy)). The gate electrode 12 only needs to be a metal that can withstand the melting point temperature of silicon. Therefore, those containing W (tungsten), Ta (tantalum), Nb (niobium), Ni (nickel), Cr (chromium), and Mo. It may be made of an alloy of The film thickness of the gate electrode 12 is preferably 30 nm or more and 300 nm or less, and more preferably 50 nm or more and 100 nm or less. This is because if the thickness of the gate electrode 12 is small, the transmittance of the gate electrode 12 increases, and the reflection of laser light described below tends to decrease. Further, when the thickness of the gate electrode 12 is large, the coverage of the gate insulating layer 13 described below is lowered. In particular, the gate insulating film is disconnected at the end of the gate electrode, so that the gate electrode 12 and the n + silicon are separated. This is because the characteristics of the thin film transistor 100 are likely to deteriorate, for example, the layer 17 is electrically connected.

The gate insulating layer 13 is formed so as to cover the gate electrode 12 and has, for example, a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer. The gate insulating layer is typically formed by a CVD apparatus. Due to the characteristics of the CVD apparatus, the distribution in the substrate surface of the film thickness of the gate insulating layer 13 corresponding to each gate electrode 12 on the substrate 10 may vary by about ± 15% with respect to the target film thickness. Regardless of the configuration of the gate insulating layer 13, the equivalent oxide thickness of the gate insulating layer 13 on each gate electrode 12 is equal to the laser beam of the amorphous silicon layer 14 on the gate electrode 12. The film thickness is in the film thickness range having a positive correlation with the light absorption rate. Here, the equivalent oxide film thickness is a value obtained by converting the physical thickness of the gate insulating layer into an electrical film thickness equivalent to the SiO ₂ film.

  In other words, the gate capacitance of the gate insulating layer 13 on each gate electrode 12 is within a film thickness range in which the amorphous silicon layer 14 on the gate electrode 12 has a negative correlation with the optical absorptance with respect to laser light. The gate insulating layer 13 is formed with a thickness of. That is, the thickness distribution (or the center value of the film thickness distribution) of the gate insulating layer 13 has a suitable range when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. The details of this preferable range will be described later, but are expressed by a certain relational expression according to the structure of the gate insulating layer 13 and the type of the constituent layers.

  The crystalline silicon layer 15 is formed on the gate insulating layer 13 and is made of a polycrystalline silicon layer (Poly-Si layer). The crystalline silicon layer 15 is polycrystalline by irradiating the amorphous silicon layer 14 with a laser after an amorphous silicon layer 14 (not shown) made of a-Si is formed on the gate insulating layer 13. It is formed by crystallization (including microcrystallization).

  Here, the term “polycrystal” has a broad meaning including not only a polycrystal in a narrow sense consisting of crystals of 50 nm or more but also a microcrystal in a narrow sense consisting of crystals of 50 nm or less. Hereinafter, polycrystal is described in a broad sense.

  The laser light source used for laser irradiation is a laser having a wavelength in the visible light region. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a laser having a wavelength of 400 nm to 600 nm. The reason why this range is preferable is that when the wavelength of the laser light is less than 400 nm, the effect of multiple interference is reduced, and the laser light of the amorphous silicon layer with respect to the change in the film thickness of the gate insulating layer 13 is reduced. This is because there is almost no change in the absorption rate, and the effect expected in the present invention cannot be obtained. On the other hand, if the wavelength of the laser light is larger than 600 nm, the absorption of the laser light with respect to the amorphous silicon layer 14 is remarkably lowered, and the crystallization efficiency is lowered in laser crystallization. It is.

  In addition, the laser having a wavelength in the visible light region may be in any one of a pulse oscillation mode, a continuous oscillation mode, and a pseudo continuous oscillation mode.

  The amorphous silicon layer 14 is made of amorphous silicon, that is, a-Si, and is formed on the gate insulating layer 13. The amorphous silicon layer 14 is formed with a film thickness within a film thickness range in which the optical absorptance of the amorphous silicon on the gate electrode 12 with respect to the laser beam changes little with respect to variations in the film thickness of the amorphous silicon layer 14. Has been. That is, the film thickness distribution of the amorphous silicon layer 14 (the center value of the film thickness distribution) has a suitable range when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. Although details of this preferable range will be described later, it is expressed by a certain relational expression according to the refractive index of the amorphous silicon layer 14 and the wavelength of the laser beam used for laser crystallization.

  The amorphous silicon layer 16 is formed on the crystalline silicon layer 15. Thus, the thin film transistor 100 has a channel layer having a structure in which the amorphous silicon layer 16 is stacked on the crystalline silicon layer 15.

  The n + silicon layer 17 is formed so as to cover the amorphous silicon layer 16, the side surfaces of the crystalline silicon layer 15, and the gate insulating layer 13.

  The source / drain electrodes 18 are formed on the n + silicon layer 17 and, for example, a metal such as Mo or Mo alloy, a metal such as titanium (Ti), aluminum (Al) or Al alloy, copper (Cu) or Cu alloy, etc. Or a metal material such as silver (Ag), chromium (Cr), tantalum (Ta), or tungsten (W).

  As described above, the thin film transistor 100 is configured.

  FIG. 3 is a diagram showing an example of an equivalent circuit of a unit repeating cell of the thin film transistor array used in the display device according to the embodiment of the present invention. The equivalent circuit shown in FIG. 3 includes a switching transistor 1, a drive transistor 2, a data line 3, a scanning line 4, a current supply line 5, a capacitance 6, and a light emitting element 7.

  The switching transistor 1 is connected to the data line 3, the scanning line 4, and the capacitance 6.

  The drive transistor 2 corresponds to, for example, the thin film transistor 100 illustrated in FIG. 2 and is connected to the current supply line 5, the capacitance 6, and the light emitting element 7.

  The data line 3 is a wiring through which data (the magnitude of the voltage value) that determines the brightness of the pixel of the light emitting element 7 is transmitted to the pixel of the light emitting element 7.

  The scanning line 4 is a wiring through which data for determining the switch (ON / OFF) of the pixel of the light emitting element 7 is transmitted to the pixel of the light emitting element 7.

  The current supply line 5 is a wiring for supplying a large current to the drive transistor 2.

  The capacitance 6 holds a voltage value (charge) for a certain time.

  The display device is configured as described above.

  Next, a manufacturing method of the thin film transistor 100 constituting the above-described thin film transistor array will be described.

  FIG. 4 is a flowchart showing a manufacturing process of a thin film transistor constituting the thin film transistor array used in the display device according to the embodiment of the present invention. A plurality of the thin film transistors 100 are manufactured on the substrate at the same time, but in the following description, a method of manufacturing one thin film transistor will be described in order to simplify the description. 5A to 5J are diagrams for explaining a method of manufacturing a thin film transistor array used in the display device according to the embodiment of the present invention. FIG. 6 is a diagram schematically showing laser annealing in S14 of FIG.

  First, the substrate 10 is prepared, the undercoat layer 11 is formed on the substrate 10 (S10), and then the gate electrode is formed on the undercoat layer 11 (S11).

  Specifically, an undercoat layer 11 is formed on the substrate 10 by plasma CVD, and then a metal film to be a gate electrode is deposited by sputtering, and the gate electrode 12 in the thin film transistor 100 is formed by photolithography and etching. (FIG. 5A). Here, the gate electrode 12 is typically formed of a metal material such as Mo or an Mo alloy (for example, MoW (molybdenum / tungsten alloy)).

  Subsequently, a gate insulating layer 13 is formed on the gate electrode 12 (S12). Then, an amorphous silicon layer 14 is formed on the gate insulating layer 13 (S13).

  Specifically, a silicon oxide film or a silicon nitride film, or a stack of a silicon oxide film and a silicon nitride film is formed by plasma CVD so as to cover the undercoat layer 11 and the gate electrode 12 on the gate electrode 12. A gate insulating layer 13 is formed by forming a film (FIG. 5B), and an amorphous silicon layer 14 is continuously formed on the formed gate insulating layer 13 (FIG. 5C).

  Next, the amorphous silicon layer 14 is turned into a crystalline silicon layer 15 by laser annealing (S14). Specifically, the amorphous silicon layer 14 is crystallized using laser light emitted from a predetermined laser to generate the crystalline silicon layer 15. More specifically, first, a dehydrogenation process is performed on the formed amorphous silicon layer 14. As the dehydrogenation treatment, a method of heating at a temperature of 450 ° C. or higher in an annealing furnace in a nitrogen atmosphere is common. Thereafter, the amorphous silicon layer 14 is made polycrystalline (including microcrystals) by laser annealing to form a crystalline silicon layer 15 (FIG. 5D).

  Here, in this laser annealing method, the laser light source used for laser irradiation is a laser having a wavelength in the visible light region as described above. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a laser having a wavelength of 400 nm to 600 m. The laser having a wavelength in the visible light region may be in a pulse oscillation mode, a continuous oscillation mode, or a pseudo continuous oscillation mode. The laser having a wavelength in the visible light region may be constituted by a solid-state laser device or a laser device using a semiconductor laser element. Further, the laser having a wavelength in the visible light region has a variation in irradiation energy density of less than about 5% when irradiated on the amorphous silicon layer 14.

  In the step of S14, that is, the steps of FIGS. 5C to 5D, as shown in FIG. 6, the crystalline silicon layer 15 is irradiated by irradiating the amorphous silicon layer 14 with a laser beam condensed in a linear shape. Is generated. There are two specific methods for irradiating laser light. That is, one is a method in which the irradiation position of the laser beam condensed linearly is fixed, the substrate 10 on which the amorphous silicon layer 14 is formed is placed on the stage, and the stage moves. The other is a method in which the stage is fixed and the irradiation position of the laser beam moves. In either method, the laser beam is irradiated while moving relative to the amorphous silicon layer 14. As described above, the amorphous silicon layer 14 irradiated with the laser light is crystallized by absorbing the energy of the laser light and rising in temperature to become the crystalline silicon layer 15.

  In addition, the laser beam may be other than the laser beam focused in a linear shape, or a spot-like (including circular or elliptical) laser beam may be used. In that case, it is preferable to perform laser light irradiation by a scanning method suitable for crystallization.

  Next, a second amorphous silicon layer 16 is formed (S15), and the silicon layer in the channel region of the thin film transistor 100 is patterned (S16).

  Specifically, a second amorphous silicon layer 16 is formed on the gate insulating layer 13 by plasma CVD (FIG. 5E). Then, the silicon layer film layer (the crystalline silicon layer 15 and the amorphous silicon layer 16) is patterned so that the channel region of the thin film transistor 100 remains, and the amorphous silicon layer 16 and the crystalline silicon layer 15 to be removed are patterned. Are removed by etching (FIG. 5F). Accordingly, a desired channel layer can be formed in the thin film transistor 100.

  Next, the n + silicon layer 17 and the source / drain electrodes 18 are formed (S17).

  Specifically, an n + silicon layer 17 is formed by plasma CVD so as to cover the amorphous silicon layer 16, the side surfaces of the crystalline silicon layer 15, and the gate insulating layer 13 (FIG. 5G). Then, a metal to be the source / drain electrode 18 is deposited on the deposited n + silicon layer 17 by sputtering (FIG. 5H). Here, the source / drain electrodes are a metal such as Mo or Mo alloy, a metal such as titanium (Ti), aluminum (Al) or Al alloy, a metal such as copper (Cu) or Cu alloy, or silver (Ag). , Chromium (Cr), tantalum (Ta), or tungsten (W).

  Next, the source / drain electrode 18 is patterned (S18). Then, the n + silicon layer 17 is etched, and in the process, the second amorphous silicon layer 16 is partially etched (S19).

  Specifically, the source / drain electrodes 18 are formed by photolithography and wet etching (FIG. 5I). Further, the n + silicon layer 17 is etched, and the amorphous silicon layer 16 in the channel region of the thin film transistor 100 is partially etched (FIG. 5J). In other words, the amorphous silicon layer 16 is channel etched so as to leave a part of the amorphous silicon layer 16 in the channel region of the thin film transistor 100.

  In this way, the thin film transistor 100 is manufactured.

  Finally, a process of electrically connecting the thin film transistors 100 constituting the thin film transistor array will be briefly described. Here, FIG. 7 is a diagram showing an example of a cross section of an equivalent circuit of the unit repeating cell of the thin film transistor array according to the embodiment of the present invention. 3 and FIGS. 5A to 5J are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 7, a silicon nitride film is formed as an interlayer insulating film by plasma CVD on the entire surface of the substrate 10 in order to protect and passivate the thin film transistor 100. Subsequently, contact holes are opened on the source / drain electrodes 18. This is performed by photolithography and dry etching. Thereafter, a metal thin film mainly made of Al or Cu is formed on the entire surface of the substrate 10 by sputtering, and the data lines 3 and the current supply lines 5 are formed by photolithography and wet etching.

As described above, the thin film transistor 100 in this embodiment is formed as a Poly-Si TFT having a bottom gate structure. When the thin film transistor 100 is manufactured, the gate insulating layer 13 and the amorphous silicon layer 14 are formed in a thickness range that satisfies the above-described relationship. Then, the amorphous silicon layer 14 is crystallized by laser annealing with a laser beam having a wavelength in the visible light region, more preferably 400 nm to 600 nm, so that the amorphous silicon layer 14 is crystallized. Set to 15. At this time, the crystallinity of the crystalline silicon layer 15 in the channel region where the thin film transistor is formed can be changed according to the gate capacitance of the gate insulating layer 13. Specifically, the crystalline silicon layer 15 can be formed on the entire surface of the substrate so that the crystallinity of the crystalline silicon layer 15 has a negative correlation with the gate capacitance of the gate insulating layer 13. In other words, the crystalline silicon layer 15 is formed on the entire surface of the substrate so that the average crystal grain size of the crystalline silicon layer 15 on the gate electrode has a negative correlation with the gate capacitance of the gate insulating layer 13. Can do. In other words, the crystalline silicon has a positive correlation with the gate capacitance of the gate insulating layer 13 so that the half width of the peak near 520 cm ⁻¹ in the Raman scattering spectrum of the crystalline silicon layer 15 on the gate electrode has a positive correlation. Layer 15 can be formed over the entire surface of the substrate.

  The thin film transistor 100 provided with the crystalline silicon layer 15 formed in this way in the channel has a driving capacity corresponding to the gate capacity corresponding to the film thickness of the gate insulating layer 13. Since it can be canceled by the conduction capability, it is possible to reduce variations in on characteristics between thin film transistors including the gate insulating layer 13 having different capacities with different film thicknesses. Therefore, a thin film transistor array including such thin film transistors 100 has a uniform in-plane distribution of on characteristics.

  As described above, the film thicknesses of the gate insulating layer 13 and the amorphous silicon layer 14 are formed so as to satisfy the above-described conditions, and the amorphous silicon layer 14 is crystallized using the laser beam described above. The crystalline silicon layer 15 is used as a channel layer of the thin film transistor. As a result, even if the display device including the thin film transistor array including the thin film transistor is increased in size, the display quality is improved without causing display unevenness due to uneven ON characteristics due to variations in the thickness of the thin film transistors. There is an effect that can be.

  In the following examples, the derivation of the film thickness ranges of the gate insulating layer 13 and the amorphous silicon layer 14 that can provide the effects of the present invention will be specifically described.

(Example)
First, when forming a gate insulating layer and an amorphous silicon layer, each film thickness fluctuates from the target film thickness (target film thickness).

Specifically, for example, it is assumed that the gate insulating layer 13 and the amorphous silicon layer 14 are continuously formed on the gate electrodes 12 formed in large numbers on the substrate 10. Here, the target film thickness of the gate insulating layer 13 is d _GI and the target film thickness of the amorphous silicon layer 14 is da _-Si . In other words, for example, the gate insulating layer 13 and the amorphous silicon layer 14 are formed on the substrate 10 with respective target film thicknesses by a CVD apparatus, for example. In that case, the gate insulating layer 13 and the amorphous silicon layer 14 vary from the target film thickness within the plane.

  This fluctuation depends on the fluctuation of the gas flow in the film forming chamber of the CVD apparatus and how the plasma standing wave is formed. Can be

  In the present embodiment, description will be made on the assumption that a film thickness deviation of a maximum of ± 15% occurs with respect to the target film thickness. Assuming that the variation in the film thickness in the substrate surface forms a normal distribution with respect to the target film thickness, the target film thickness of the gate insulating layer 13 and the target film thickness of the amorphous silicon layer 14 are in-plane. It can be considered that the average film thickness is as follows.

Here, it is assumed that the fluctuation amount of 15% of d _GI is Δd _GI and the fluctuation amount of 15% of d _a-Si is Δd _a-Si . Then, in the gate insulating layer 13 and the amorphous silicon layer 14, a set (d _GI ± Δd _GI ) of the film thickness that fluctuates to the maximum corresponding to the target set of film thicknesses (d _GI , d _a-Si ). , D _a-Si ± Δd _a-Si ) (decoding arbitrary) can be considered to be formed on the substrate with a probability that it is not zero.

Next, the absorptance A of the amorphous silicon layer 14 corresponding to the variable film thickness group including the target film thickness group (d _GI , d _a-Si ) will be considered. Here, the absorption rate A is the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to laser light having a wavelength λ. Since the absorption rate A is a function of the film thickness of the gate insulating layer 13 and the film thickness of the amorphous silicon layer 14, the absorption rate A is set for each set of target film thicknesses (a set of variable film thicknesses). Can be calculated uniquely. For example, when the gate insulating layer 13 is composed of a plurality of types of films (for example, the film 131 and the film 132), the film 131 has a thickness d _GI1 and the film 132 has a film thickness d _GI2 . Consider a 15% variation Δd _GI1 and Δd _GI2 for the membrane. The same can be considered when there are more types of membranes.

Now, the absorptance A of the amorphous silicon layer on the gate electrode 12 in the variable film thickness set (including the target film thickness set) corresponding to the target film thickness set (d _GI , d _a-Si ) is calculated. In this case, the correlation between the absorption rate A and the fluctuation film thickness (d _GI ± Δd _GI , d _a-Si ± Δd _a-Si ) can be defined. The gate combination of the variation of the insulating layer 13 may be replaced by a set of variations in the gate capacitance of the gate insulating layer 13 (defined as C _GI ± ΔC _GI). That is, (d _GI ± Δd _GI , d _a-Si ± Δd _a-Si ) can be considered to be replaced with (C _GI ± ΔC _GI , d _a-Si ± Δd _a-Si ). The correlation between A and the gate capacitance variation set can be defined. In other words, 1) the thickness of the gate insulating layer 13 corresponding to each of the plurality of gate electrodes 12 (specifically, the equivalent oxide thickness of the gate insulating layer 13), and the amorphous silicon layer on the gate electrode 12 The film thickness range of the region in which the absorptance with respect to 14 laser beams has a positive correlation is defined by a set of laser light wavelength λ and variable film thickness (d _GI ± Δd _GI , d _a-Si ± Δd _a-Si ). The target of the gate insulating layer 13 in which the correlation between the absorption rate A and the gate capacitance (C _GI ± ΔC _GI ) is a negative correlation (for example, when the approximate straight line is drawn, the slope takes a negative value) This is equivalent to the possible range of film thickness.

Further, 2) the amorphous silicon layer 14 corresponding to each of the plurality of gate electrodes 12 is formed in a film thickness range in which the light absorptance is small with respect to the film thickness change of the amorphous silicon layer 14. This film thickness range has a good correlation between the absorption rate A and the gate capacitance (C _GI ± ΔC _GI ) defined at this time (for example, when an approximate straight line is drawn, the R-square value is larger than 0 and the lowest) However, it is equivalent to the range of the target film thickness of the amorphous silicon layer 14 that gives the state.

  Based on the above concept, the film thickness ranges of the gate insulating layer 13 and the amorphous silicon layer 14 that can obtain the effects of the present invention can be calculated as follows.

That is, first, a set of hypothetical variable film thickness corresponding to the target film thickness (d _GI , d _a-Si ) and the amorphous silicon layer 14 on the gate electrode corresponding to each of the set of variable film thickness. The absorptance A with respect to the laser beam having the wavelength λ is calculated. Then, the correlation between the absorption rate A and the fluctuation capacity obtained from the imaginary fluctuation film thickness is examined, and the approximate straight line of the correlation has a negative inclination, and the R square value of the film thickness is a value greater than zero. Can be calculated as the range of the film thickness (the range of values that the target film thickness can take).

  Hereinafter, as an example, it is assumed that the gate insulating layer 13 is configured by a laminated film of an insulating film 1301 and an insulating film 1302. Specifically, description will be made on the assumption that an insulating film 1301 is formed on the gate electrode 12 and an insulating film 1302 is formed on the insulating film 1301 to form the gate insulating layer 13. In this structure, the calculation procedure of the absorptance of the amorphous silicon layer 14 on the gate electrode 12 with respect to the laser beam having the wavelength λ will be described below.

  The light absorptance of the multilayer thin film constituting the thin film transistor 100 is obtained by calculating the amplitude reflectance and the amplitude transmittance for each constituent film. FIG. 8 is a diagram for explaining a method of calculating the amplitude reflectance and the amplitude transmittance.

FIG. 8 is a diagram showing a model structure of a multilayer structure in which the structure of the thin film transistor 100 shown in FIG. 2 is modeled. In the model structure shown in FIG. 8, a layer 401 composed of a complex refractive index N1, a layer 402 composed of a complex refractive index N2, a layer 403 composed of a complex refractive index N3, a layer 404 composed of a complex refractive index N4, and a complex refractive index. And a substrate layer 405 (not shown) made of N5. In this model structure, a layer 404, a layer 403, a layer 402, and a layer 401 are stacked on the substrate layer 405 in this order. Further, the region of the complex refractive index N0 shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. This region is, for example, air or N ₂ gas.

  The substrate layer 405 is an insulating substrate made of, for example, transparent glass or quartz, and corresponds to the substrate 10 shown in FIG. 5A. The layer 404 is made of a metal thin film having a film thickness of 1% or less with respect to the laser beam. For example, the layer 404 is made of a refractory metal such as Mo, Cr, or W, and the gate electrode 12 shown in FIG. 5A. Corresponding to The layer 403 is composed of an insulating film 1301, and the layer 402 is composed of an insulating film 1302. Here, the insulating film 1301 and the insulating film 1302 are, for example, dielectric thin films such as silicon nitride and silicon oxide. A stacked film of these two layers (layer 403 and layer 404) corresponds to the gate insulating layer 13 shown in FIG. 5A. The layer 401 corresponds to the amorphous silicon layer 14. In order to ignore the light transmission through the gate electrode 12, the layer corresponding to the undercoat layer 11 is omitted in the model structure shown in FIG.

  Here, as shown in FIG. 8, the amplitude reflection coefficient for light incident on the layer 401 from the outside is r01, the amplitude reflection coefficient for light incident on the layer 402 from the layer 401 is r12, and the amplitude reflection coefficient is incident on the layer 401 from the layer 402. The amplitude reflection coefficient for the incident light is r23, and the amplitude reflection coefficient for the light incident on the layer 404 from the layer 403 is r34. Further, the amplitude transmission coefficient of light incident on the layer 401 from the outside is t01, the amplitude transmission coefficient of light incident on the layer 402 from the layer 401 is t12, and the amplitude transmission coefficient of light incident on the layer 402 from the layer 402 is t23, the amplitude transmission coefficient of light incident on the layer 404 from the layer 403 is t34.

  Further, the amplitude reflection coefficients of the entire layers above the region where the layer 404 corresponding to the gate electrode 12 is formed are r01234 (R1), r1234 (R2), and r234 (R3), respectively. Specifically, the amplitude reflection coefficient when the layers 404 and 403 are regarded as one layer is r234 (R3). Similarly, the amplitude reflection coefficient when the layers 404, 403, and 402 are regarded as one layer is r1234 (R2), and the amplitude reflection when the layers 404, 403, 402, and 401 are regarded as one layer. The coefficient is r01234 (R1). Further, the amplitude transmission coefficients of the entire layers shown in FIG. 8 are t01234 (T1), t1234 (T2), and t234 (T3), respectively. Specifically, the amplitude transmission coefficient when the layers 404 and 403 are regarded as one layer is t234 (T3). Similarly, the amplitude transmission coefficient when the layers 404, 403, and 402 are regarded as one layer is t1234 (T2), and the amplitude transmission when the layers 404, 403, 402, and 401 are regarded as one layer. The coefficient is t01234 (T1).

  The amplitude reflection coefficient and amplitude transmission coefficient of the entire layer above the region where the layer 404 corresponding to the gate electrode 12 is formed can be expressed by the following (Expression 1) to (Expression 6).

であり、ｄ_ｎは各層の膜厚、θ_ｎは各層での入射角・透過角、λはレーザー光の波長である。here,

In and, d _n is the film thickness of each layer, theta _n the angle of incidence and transmission angles of each layer, lambda is the wavelength of the laser beam.

  Further, θ can be calculated as shown in the following (Expression 7) from Snell's law of the following expression.

  Further, the amplitude reflection coefficients r01, r12, r23, and r34 and the amplitude transmission coefficients t01, t12, t12, and t34 of each layer can be calculated using the following (Expression 8) to (Expression 15).

  Here, the light is monochromatic laser light, and its polarization is assumed to be P-polarized light.

  Next, using the above equations, the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer above the region where the layer 404 corresponding to the gate electrode 12 is formed are calculated as follows. That is, first, r234 is calculated by substituting (Equation 10) and (Equation 11) into (Equation 3). Next, r1234 is calculated by substituting (Equation 9) and r234 into (Equation 2). Next, r01234 is calculated by substituting (Equation 8) and r1234 into (Equation 3). Next, t234 is calculated by substituting (Expression 10), (Expression 11), (Expression 14), and (Expression 15) into (Expression 6). Next, t1234 is calculated by substituting (Equation 9), (Equation 13), r234, and t234 into (Equation 5). Next, t01234 is calculated by substituting (Equation 8), (Equation 12), r1234, and t1234 into (Equation 4).

  Next, the reflectances R1, R2 and R3 and the transmittances T1, T2 and T3 in the respective layers above the region where the layer 404 corresponding to the gate electrode 12 is formed are calculated by (Expression 16) to (Expression 21). To do.

  Finally, the light absorption rate A to the amorphous silicon layer on the gate electrode can be calculated by (Equation 22).

Using the above-described calculation method, laser light having a wavelength λ is incident on the model structure shown in FIG. 8 at an incident angle θ ₀ that is perpendicular to the model structure, that is, in a range in which θ ₀ = 0 or sin θ ₀ = 0 approximately holds. In this case, the light absorption rate of the amorphous silicon layer on the gate electrode can be calculated. In this case, the calculation result is the same even if the polarization of the laser beam is S polarization.

By the above method, the amorphous silicon layer 14 has a thickness of da _-Si . For example, the insulating film 1301 constituting the gate insulating layer 13 is a silicon nitride film and the insulating film 1302 is a silicon oxide film. Using the respective film thicknesses (silicon nitride film thickness: d _SiN , silicon oxide film thickness: d _{SiO 2} ), the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to the laser light is calculated. be able to. Further, when the above method is used, it is assumed that the insulating film 1301 and the insulating film 1302 are made of the same material, for example, so that the gate insulating layer 13 is formed of a single-layer insulating film. The absorption rate of the amorphous silicon layer 14 on the electrode 12 with respect to the laser beam can be calculated.

  Next, it will be described that the film thickness of the amorphous silicon layer 14 for obtaining the effects of the present invention has a suitable range.

  FIG. 9 is a diagram for explaining that there is a film thickness range suitable for the film thickness of the amorphous silicon layer when the crystalline silicon layer is formed by the laser annealing crystallization method.

Specifically, FIG. 9 is definitive when the gate insulating layer 13 is formed of a silicon oxide film monolayer, standardized by the laser beam wavelength lambda, the optical thickness of the amorphous silicon layer 14 (n _{a -Si} × _{da -Si} / λ) and the absorption rate (A / A) of the laser light wavelength λ of the amorphous silicon layer 14 normalized by the optical film thickness of the silicon oxide film normalized by the laser light wavelength λ. (N _SiO xd _{SiO 2} / λ)). Each curve shown in FIG. 9 corresponds to the value of the optical film thickness (n _SiO × d _SiO / λ) of the silicon oxide film normalized by the laser light wavelength λ. Further, the relationship shown in FIG. 9 is derived by the above-described method for calculating the absorptance of the amorphous silicon layer 14 on the gate electrode 12 with respect to the laser light when the wavelength range of the laser light is 400 nm to 600 nm.

As shown in FIG. _9, in accordance with the _{n SiO} × _{d SiO} / _λ gives a maximum of the curve _{n a-Si × d a-} Si / λ is shifted.

  Here, in the thin film transistor array, in order for each thin film transistor 100 to have a uniform on characteristic, a change in the film thickness of the amorphous silicon layer 14 causes a change in the absorption rate of the amorphous silicon layer 14 on the gate electrode. It is necessary not to affect. Therefore, in this embodiment, the amorphous silicon layer 14 is a film in which the influence of the variation in the thickness of the amorphous silicon layer 14 on the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode is reduced. It is necessary to form in the thickness range.

In FIG. 9, the range of the film thickness where the influence of the variation in the thickness of the amorphous silicon layer 14 on the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode is any n _SiO xd _{SiO 2.} The / λ curve also corresponds to the film thickness range of the amorphous silicon layer 14 in the vicinity of n _a-Si × d _a-Si / λ giving the maximum. That is, the preferable film thickness range of the amorphous silicon layer 14 is a film corresponding to a region within a predetermined range with respect to the maximum value for any curve of n _SiO xd _SiO / λ. It is in the thickness range. In other words, the differential coefficient is, for example, −5 with respect to the differential coefficient 0 (maximum value) obtained by differentiating the curve of A / (n _SiO × d _SiO / λ) by na _−Si × d _a−Si / λ. This corresponds to the formation of the amorphous silicon layer 14 in a film thickness range corresponding to the range of +5 to +5.

  Specifically, the range of the film thickness corresponding to the range where the differential coefficient is −5 to +5 can be given by (Equation 23).

_{0.426 ≦ n a-Si × d} a-Si /λ≦0.641 ( Formula 23)

  As long as the insulating film constituting the gate insulating layer 13 is transparent to laser light, that is, the extinction coefficient of the insulating film constituting the gate insulating layer 13 is small enough not to affect multiple interference ( 0.01 or less), the gate insulating layer 13 does not absorb laser light. Therefore, a preferable range of the film thickness of the amorphous silicon layer 14 is established regardless of its configuration.

  In the present embodiment, the gate insulating layer 13 is described as being composed of a single silicon oxide layer for the sake of simplicity, but the present invention is not limited to this. As long as the gate insulating layer 13 is composed of a transparent insulating film, the optical film thickness (sum of the product of the refractive index and the film thickness of the insulating layer) is replaced with the optical film thickness of the silicon oxide layer described above. This is true.

Hereinafter, a preferable range of the film thickness of the amorphous silicon layer 14 for obtaining the effects of the present invention will be described more specifically. In the following, it is assumed that the wavelength range of the laser light is 400 nm to 600 nm, and the range of na _-Si x da _-Si / λ is 0.426 to 0.641. Further, the insulating film 1301 constituting the gate insulating layer 13 described above is described as a silicon nitride film, for example, and the insulating film 1302 is described as a silicon oxide film, for example.

In this case, the gate capacitance _CGI of the gate insulating layer 13 is a combined capacitance of the capacitance of the silicon oxide film and the capacitance of the silicon nitride film, and can be calculated by (Equation 24). Here, the relative dielectric constant of the silicon oxide film is ε _{SiO 2} , the relative dielectric constant of the silicon nitride film is ε _SiN , and the dielectric constant of vacuum is ε ₀ .

In the following, the gate capacitance C _GI ± ΔC _GI representing the capacitance variation (variable capacitance) of the gate insulating layer 13 is used as the gate capacitance used when examining the correlation with the absorption rate A. using the gate capacitance _{C GI '= (C GI ±} ΔC GI) / C GI normalized by the gate capacitance _{C GI} with respect to the film thickness.

Then, using the formula described above, first, thickness variation of the set _{(d a-Si ± Δd a} -Si, d SiO ± Δd SiO, d SiN ± Δd SiN) corresponding gate electrode in each of the (decoded arbitrary) The correlation between the absorption rate A of the upper amorphous silicon layer 14 and the normalized gate capacitance _CGI ′ was examined. Here, thickness variation of the set _{(d a-Si ± Δd a} -Si, d SiO ± Δd SiO, d SiN ± Δd SiN) ( decoding optional), as described above, when the laser beam wavelength is lambda, This is a set of film thicknesses when the film thickness fluctuates 15% from the target film thickness (da _-Si , _dSiO , _dSiN ).

  Next, the coefficient and R square value of the approximate line in the examined correlation (plot) were calculated for each target film thickness.

  FIG. 10A is a diagram showing that there is a preferable film thickness range for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method.

Specifically, FIG. 10A plots the coefficients of the approximate line in the correlation between the absorption rate A and the normalized gate capacitance _CGI ′ as a contour map. FIG. 10B is a diagram showing that there is a preferable film thickness range for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. Specifically, FIG. 10B, the R2 squared value of the approximation straight line in the correlation between the absorption factor A and the normalized gate capacitance C _{GI ',} which is a plot as a contour plot. 10A and 10B, the horizontal axis X represents the optical film thickness of the silicon oxide layer, that is, the value obtained by multiplying the refractive index n _SiO of the silicon oxide layer by the film thickness d _{SiO of the} silicon oxide layer, and the wavelength λ of the laser beam. A value obtained by dividing by X, that is, X = (n _SiO × d _SiO ) / λ. The vertical axis Y represents the optical film thickness of the silicon nitride layer, that is, the value obtained by multiplying the refractive index n _SiN of the silicon nitride layer by the film thickness d _{SiN of the} silicon nitride layer by the wavelength λ of the laser beam, that is, Y = (N _SiN × d _SiN ) / λ. In other words, the values shown in FIGS. 10A and 10B are generalized with respect to the laser light wavelength and the optical constant of the gate insulating layer 13. The optical constants of the material of the gate electrode 12, specifically the refractive index n and the extinction coefficient k, affect the absolute value of the absorption rate A of the amorphous silicon layer 14 on the gate electrode 12. The correlation with the normalized gate capacitance C _GI 'is not affected. In other words, the values shown in FIGS. 10A and 10B are generalized for the material of the gate electrode 12.

Region A and region B shown in FIG. 10A are regions where the coefficient of the approximate straight line in the correlation between the absorption rate A and the normalized gate capacitance C _GI ′ is negative. Specifically, the region A is a region expressed by (Expression 25) and (Expression 26), and the region B is a region expressed by (Expression 27) and (Expression 28).

Y ≧ −1070X ⁶ + 1400X ⁵ −688X ⁴ + 153X ³ −12.90X ² −1.02X + 0.439 (Formula 25)
Y ≦ 49.9X ⁶ −131X ⁵ + 127X ⁴ −56.8X ³ + 11.8X ² −2.01X + 0.736 (Formula 26)
Y ≧ −7.34X ⁶ + 8.48X ⁵ + 8.65X ⁴ −16.0X ³ + 7.24X ² −2.04X + 0.961 (Formula 27)
Y ≦ −3.75X ⁶ + 11.8X ⁵ −13.1X ⁴ + 6.09X ³ −1.12X ² −0.87X + 1.20 (Formula 28)

  Therefore, by adopting the film thicknesses of the silicon oxide film and the silicon nitride film satisfying the mathematical formulas represented by (Formula 25) and (Formula 26) or (Formula 27) and (Formula 28) as the target film thickness, Even if the film thickness varies in the substrate plane, the absorption rate A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 have a negative correlation. The gate insulating layer 13 can be formed.

Further, region 1 and region 2 shown in FIG. 10B are regions in which the R-square value of the approximate line in the correlation between the absorption rate A and the normalized gate capacitance C _GI ′ is 0.3 or more. Specifically, the region 1 is a region represented by (Equation 29) and (Equation 30), and the region 2 is a region represented by (Equation 31) and (Equation 32).

Y ≧ −132.6X ⁶ + 181X ⁵ −93.8X ⁴ + 21.3X ³ −1.33X ² −1.04X + 0.473 (formula 29)
Y ≦ 23.7X ⁶ −4.56X ⁵ −35.4X ⁴ + 27.2X ³ −5.75X ² −0.973X + 0.619 (Equation 30)
Y ≧ 7.46X ⁶ −32.4X ⁵ + 50.8X ⁴ −35.7X ³ + 11.0X ² −2.20X + 1.04 (Formula 31)
Y ≦ −5.34X ⁶ + 16.7X ⁵ −18.7X ⁴ + 9.18X ³ −1.96X ² −0.821X + 1.13 (Formula 32)

  Therefore, by adopting the film thicknesses of the silicon oxide film and the silicon nitride film satisfying the mathematical formulas represented by (Formula 29) and (Formula 30) or (Formula 31) and (Formula 32) as the target film thickness, Even if the film thickness of the amorphous silicon layer 14 varies within the substrate surface, the influence on the variation in the absorption rate A of the amorphous silicon layer 14 on each gate electrode 12 can be minimized.

  Further, FIG. 10B shows the region A and the region B calculated in FIG. 10A. Therefore, as shown in FIG. 10B, it can be seen that region 1 and region 2 are included in region A and region B.

  That is, if the film thicknesses of the silicon oxide film and the silicon nitride film that satisfy the mathematical expressions representing the regions 1 and 2 are adopted as the target film thicknesses, they automatically belong to the film thickness ranges of the regions A and B. . Therefore, even if the film thickness of the silicon nitride film, the silicon oxide film, and the amorphous silicon film varies within the substrate surface, the absorption rate A of the amorphous silicon layer 14 on each gate electrode and each gate electrode Thus, the gate insulating layer 13 can be formed so that the gate capacitance at 12 has a negative correlation.

  As described above, the region 1 and the region 2 are the most preferable thickness ranges of the gate insulating layer 13 and the amorphous silicon layer 14 in which the effects of the present invention can be obtained.

  In the above description, the gate insulating layer 13 is not limited to the case where the silicon oxide film and the silicon nitride film are stacked in this order. For example, when the order of the silicon nitride film and the silicon oxide film constituting the gate insulating layer 13 is reversed, the above-described film thickness range may be derived again after exchanging X and Y described above.

  For example, the gate insulating layer 13 may be a single layer. In that case, the absorption rate A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 have a negative correlation by the same calculation method as described above. Thus, the target film thickness range of the gate insulating layer 13 can be derived.

  Specifically, X = 0 is substituted in (Expression 25) and (Expression 26) or (Expression 27) and (Expression 28). Then, when the gate insulating layer 13 is formed of a single insulating film, the range of possible target film thicknesses of the gate insulating layer 13 generalized with respect to the wavelength λ is as follows (Formula 33) Alternatively, it is derived as (Equation 34).

0.44 ≦ n _GI × d _GI /λ≦0.74 (Formula 33)
0.96 ≦ n _GI × d _GI /λ≦1.20 (Formula 34)

Here, d _GI represents the average film thickness of the gate insulating layer, λ represents the laser beam wavelength, and n _GI represents the refractive index of the gate insulating layer 13 with respect to the laser beam having the wavelength λ.

  Further, X = 0 is substituted in (Expression 29) and (Expression 30), or (Expression 31) and (Expression 32). Then, when the gate insulating layer 13 is formed of a single insulating film, the range of possible target film thicknesses of the gate insulating layer 13 generalized with respect to the wavelength λ is as follows (Formula 35) Or, it is derived as (Equation 36).

  By forming the gate insulating layer 13 within this range, when the gate insulating layer 13 is formed of a single layer insulating film, the film thicknesses of the gate insulating layer 13 and the amorphous silicon layer 14 are within the substrate plane. Even if it fluctuates, the absorptivity A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 can have a negative correlation. That is, the range of the film thickness represented by (Expression 35) or (Expression 36) is the most preferable range of the target film thickness of the gate insulating layer 13 in which the effect of the present invention is obtained.

0.47 ≦ n _GI × d _GI /λ≦0.62 (Formula 35)
1.04 ≦ n _GI × d _GI /λ≦1.13 (Formula 36)

  As described above, even when the gate insulating layer 13 of the thin film transistor 100 has a stacked structure or a single layer structure, the film thicknesses of the amorphous silicon layer 14 and the gate insulating layer 13 that can obtain the effects of the present invention are derived. I was able to. However, this derivation method can be used regardless of whether the gate insulating layer 13 has a laminated structure or a single layer structure. That is, by using this derivation method, it is possible to derive the film thicknesses of the amorphous silicon layer 14 and the gate insulating layer 13 that can obtain the effects of the present invention regardless of the configuration of the gate insulating layer 13.

  Hereinafter, as a specific example, a thin film transistor array in which the gate insulating layer 13 includes a silicon nitride film and a silicon oxide film will be described. In this thin film transistor array, the gate insulating layer 13 has a structure in which a silicon nitride film and a silicon oxide film are laminated in order from the gate electrode 12. In the following description, it is assumed that the crystalline silicon layer 15 is formed by laser annealing the amorphous silicon layer 14 using a laser beam having a wavelength λ = 532 nm.

  FIG. 11 is a diagram showing a specific example of a film thickness range suitable for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. Specifically, in FIG. 11, the range from 0 to 0.8 in X and Y shown in FIG. 10B is expanded, and X and Y are converted into actual silicon oxide film and silicon nitride film thicknesses. It is shown as Here, the refractive index of the silicon oxide film is 1.467, and the refractive index of the silicon nitride film is 1.947. The refractive index of the amorphous silicon layer 14 is 5.07, and the extinction coefficient is 0.61. The target film thickness range of the amorphous silicon layer 14 is assumed to be 44.7 nm to 67.3 nm. This film thickness range is derived from the above (Expression 23) to (Expression 32).

Here, as the structure of the thin film transistor 100 constituting the thin film transistor array, the structural conditions (conditions 1 to 3) of the gate insulating layer 13 were examined. As shown in FIG. 11, the condition 1 is that the silicon oxide film thickness d _SiO = 80 nm and the silicon nitride film thickness d _SiN = 75 nm (hereinafter, d _SiO / d _SiN = 80/75 nm). Write). Condition 2 is _dSiO / _dSiN = 30/160 (nm). Condition 3 is d _SiO / d _SiN = _90/55 (nm).

  Note that conditions 1 to 3, that is, the configuration conditions of the three gate insulating layers 13 are set so that the equivalent oxide film thickness is approximately 120 nm.

  As can be seen from FIG. 11, Condition 1 is included in the most preferable region 1, and Condition 2 is included in at least the region A. On the other hand, the condition 3 is not included in either the region 1 or the region A. Therefore, in conditions 1 to 3, condition 1 is the most preferable condition, and condition 2 is the preferable condition. Condition 3 is an unfavorable conventional condition.

  12A to 12C are diagrams showing the relationship between the capacitance formed by the varying film thickness and the absorption rate of the amorphous silicon layer 14.

  Specifically, in FIG. 12A, when the target film thickness of the gate insulating layer 13 is configured under the condition 1, the film thickness on the gate electrode 12 is the film thickness when the film thickness varies ± 15% from the target film thickness. 3 shows the correlation between the absorption rate of the laser beam of the amorphous silicon layer 14 and the gate capacity of the gate insulating layer 13. Here, the horizontal axis of FIG. 12A indicates the normalized gate capacitance that is a value normalized by the gate capacitance of the gate insulating layer 13 having the target film thickness, and the vertical axis indicates the absorption rate. The target film thickness of the amorphous silicon layer 14 was set to 60 nm.

  Similarly, FIG. 12B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2, and FIG. 12C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .

  12A to 12C, under the condition 1 where the target film thickness is included in the region 1, a strong negative correlation is shown between the gate capacitance and the absorption rate of the amorphous silicon layer 14 on the gate electrode. The multiplier value is also close to 0.5, and it can be seen that the influence of the change in the thickness of the amorphous silicon layer 14 on the change in the absorptance is small. On the other hand, the relationship between the gate capacitance and the absorptance of the amorphous silicon layer 14 on the gate electrode 12 is weak at least under the condition of the film thickness 2 of the condition 2 that is not included in the region 1 but included in the region A. Although a negative correlation is shown, the R square value is also as small as 0.1 or less, and it can be seen that the film thickness variation of the amorphous silicon layer 14 has a great influence on the absorption rate variation.

  On the other hand, under the condition of the film thickness condition 3 that is not included in either the region 1 or the region A, the relationship between the gate capacitance and the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 is an approximate straight line. Is almost zero. This indicates that the film thickness condition does not change the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to the film thickness fluctuation of the gate insulating layer 13. It means that it is one mode of the film thickness condition as disclosed in Document 2. Further, the R-square value is almost 0, and it can be seen that the film thickness variation of the amorphous silicon layer 14 has a great influence on the absorption rate variation.

  13A to 13C are diagrams illustrating the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer 14.

  Specifically, in FIG. 13A, when the target film thickness of the gate insulating layer 13 is configured under the condition 1, the film thickness on the gate electrode 12 is the film thickness when the film thickness varies ± 15% from the target film thickness. 6 shows the correlation between the half-width of the peak of the Raman shift spectrum around 520 cm −1 when the region of the amorphous silicon layer 14 is measured by Raman scattering spectroscopy and the gate capacitance of the gate insulating layer 13. . Here, the horizontal axis of FIG. 12 indicates the normalized gate capacitance that is a value normalized by the gate capacitance of the gate insulating layer 13 having the target film thickness, and the vertical axis indicates the crystalline silicon obtained when the target film thickness is obtained. It is normalized by the half width of the layer 15.

  Similarly, FIG. 13B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2, and FIG. 13C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .

  Here, an increase in the half width indicates that the crystallinity of the crystalline silicon layer 15 is deteriorated, and conversely, a decrease in the half width indicates that the crystallinity of the crystalline silicon layer 15 is improved. .

  Therefore, from FIG. 13A, when the target film thickness of the gate insulating layer 13 is configured under the condition 1, when the gate capacitance increases, the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 deteriorates. It can be seen that when the capacitance decreases, the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 is improved. Therefore, by setting the target film thickness conditions so as to be included in the most preferable region 1, as confirmed in FIG. 12A, as the gate capacitance increases, the amorphous silicon layer 14 on the gate electrode 12 increases. It is possible to reduce the absorption rate. Thereby, the correlation between the gate capacitance and the crystallinity of the crystalline silicon layer 15 formed on the gate electrode 12 by laser light irradiation can be made negative (the correlation between the gate capacitance and the Raman half width is positive). .

  On the other hand, from FIG. 13B and FIG. 13C, the clear correlation between the gate capacitance and the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 decreases as the target film thickness deviates from the preferred range. I understand.

  14A to 14C are diagrams showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor 100 using the crystalline silicon layer 15 as a channel.

  Specifically, FIG. 14A shows the crystalline silicon obtained by crystallizing the amorphous silicon layer 14 with the capacitance formed by the varying thickness when the target thickness of the gate insulating layer 13 is configured under the condition 1. It is a figure which shows the relationship with the ON current of the thin-film transistor 100 which used the layer 15 as the channel. Here, the thin film transistor array used for the evaluation is formed on the glass substrate using the crystalline silicon layer 15 obtained by crystallizing the amorphous silicon layer 14 under the laser annealing conditions described above. The on-current was evaluated for one thin film transistor 100 of each thin film transistor array. Further, the capacitance formed by the varying film thickness was evaluated by a gate capacitance evaluation TEG (Test Element Group) formed in the vicinity of the corresponding thin film transistor 100. Here, in FIG. 14A, the gate capacitance and the on-current are aimed at and standardized by the characteristics of the thin film transistor 100 under the film thickness condition.

  Similarly, FIG. 14B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2, and FIG. 14C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .

  As shown in FIG. 14A, in condition 1, the maximum and minimum of the on-current are within ± 20% of the center value, and the variation in on-current is the smallest compared to other conditions. Further, as shown in FIG. 14B, in condition 2, the maximum and minimum of the on-current are slightly over ± 20% with respect to the center value.

  On the other hand, as shown in FIG. 14C, in the condition 3, the maximum and minimum of the on-current are ± 30% or more with respect to the center value, and the on-current is reduced with respect to the variation of the film thickness constituting the channel region of the thin film transistor. The variation is large. Therefore, in the prior art, when using a film thickness condition that minimizes the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode 12, when the layer thickness of the channel layer of the thin film transistor 100 varies, The variation in crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be reduced to some extent. However, it can be seen that when a plurality of thin film transistors 100 are formed in the substrate surface, it is difficult to reduce the variation in their on-currents.

  According to the above embodiment, the aim is to satisfy the region A (and the region B) derived as the film thickness region in which the effect of the present invention is obtained, and the region 1 (and the region 2) which is a further preferable range. By setting the film thickness, the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be reduced with respect to the increased increase in gate capacitance. As a result, even if the film thickness varies from the target film thickness, the ON characteristics of the plurality of thin film transistors 100 can be kept uniform.

  In summary, when a thin film transistor array is formed on a substrate, the target film thicknesses of the gate insulating layer 13 of the thin film transistor 100 and the amorphous silicon layer 14 before laser annealing crystallization are calculated as described above. Thus, even if each film thickness varies on the substrate 10, the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 and the gate formed by the gate insulating layer 13 are formed. Correlation with capacity can be negative. Thereby, the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to the variation in the film thickness of the amorphous silicon layer 14 can be reduced. That is, by adopting such a target film thickness, even when the film thickness varies on the substrate 10, when the amorphous silicon layer 14 is laser-annealed and the crystalline silicon layer 15 is formed, It becomes possible to have a negative correlation between the crystallinity of the crystalline silicon layer 15 corresponding to the gate electrode 12 and the gate capacitance. As a result, fluctuations in driving ability caused by fluctuations in the gate capacitance of each thin film transistor 100 constituting the thin film transistor array formed on the substrate 10 can be offset by the crystallinity of the crystalline silicon layer 15. The uniformity of the on-characteristics of each thin film transistor 100 that constitutes the entire surface of the substrate can be maintained, which is an effect that could not be realized by the conventional technology.

  As described above, according to the present invention, it is possible to realize a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array that can be configured with thin film transistors having uniform on characteristics.

  Specifically, the crystalline silicon layer 15 whose crystallinity is intentionally changed according to the change in the gate capacitance of the thin film transistor 100 can be formed using a laser having a wavelength in the visible light region. As a result, a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the same can be realized in which the ON characteristics of the respective thin film transistors 100 constituting the thin film transistor array thus manufactured are made uniform.

  More specifically, by forming the amorphous silicon layer 14 and the gate insulating layer 13 so that each film thickness satisfies a predetermined condition, a gate capacitance is obtained using a laser having a wavelength in the visible light region. Thus, the crystalline silicon layer 15 having a negative correlation with the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be formed. Accordingly, a thin film transistor array manufacturing method, a thin film transistor array, which has the effect of canceling the driving capability of the thin film transistor 100 due to the gate capacitance and uniformizing the on characteristics of the thin film transistor 100 constituting the thin film transistor array formed on the substrate 10, A display device using can be realized.

  Here, in the case where the thin film transistor array of the present invention is used for the display device shown in FIG. 15, a high-quality display device having uniform transistor characteristics can be realized. Further, the yield can be improved and the cost can be reduced by improving the display quality.

  According to the present invention, for example, the effect can be realized by taking the film thickness condition within the above range without changing the pattern shape of the gate electrode 12 and the like, in particular, the structure of the thin film transistor and the circuit configuration. Therefore, for example, even when a higher-definition display device is manufactured, it can be said that the design flexibility can be maintained over the conventional technology.

  As described above, the manufacturing method of the thin film transistor device array, the thin film transistor array, and the display device using the same according to the present invention have been described based on the embodiment. However, the present invention is not limited to this embodiment. Unless it deviates from the meaning of this invention, the form which carried out the various deformation | transformation which those skilled in the art can think to this embodiment, and the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  INDUSTRIAL APPLICABILITY The present invention can be used for a method of manufacturing a thin film transistor array, a thin film transistor array, a liquid crystal panel using the thin film transistor array, or a display device including an EL panel such as an organic EL panel. Even if the film thickness of the channel constituent layer (amorphous silicon layer, gate insulating layer) varies, the on-state characteristics of each thin film transistor constituting the thin film transistor array are uniform, high-quality liquid crystal panel, organic EL panel, etc. It can be used for manufacturing a display device including an EL panel.

DESCRIPTION OF SYMBOLS 1 Switching transistor 2 Drive transistor 3 Data line 4 Scan line 5 Current supply line 6 Capacitance 7 Light emitting element 10 Substrate 11 Undercoat layer 12 Gate electrode 13 Gate insulating layer 14, 16 Amorphous silicon layer 15 Crystalline silicon layer 17 n + silicon Layer 18 Source / drain electrode 100 Thin film transistor 401, 402, 403, 404 Layer 405 Substrate layer
1301 and 1302 insulating films

Claims (20)

A first step of preparing a substrate;
A second step of forming a plurality of gate electrodes on the substrate;
A third step of forming a gate insulating layer on the plurality of gate electrodes;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
A fifth step of generating a crystalline silicon layer by crystallizing the amorphous silicon layer using laser light emitted from a laser;
A sixth step of forming a source electrode and a drain electrode in a region on the crystalline silicon layer in each of the plurality of gate electrodes,
In the third step, the film thickness of the gate insulating layer on the plurality of gate electrodes is set so that the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser light and the equivalent oxidation of the gate insulating layer. Form in the film thickness range of the area where the film thickness is positively correlated,
In the fourth step, the thickness of the amorphous silicon layer on the plurality of gate electrodes is set so that a change in the light absorptance with respect to a change in the thickness of the amorphous silicon layer is predetermined from a first reference. Formed in the film thickness range of the region within the range,
A method of manufacturing a thin film transistor array. The laser is composed of a solid-state laser device,
A method of manufacturing the thin film transistor array according to claim 1. The laser is composed of a laser device using a semiconductor laser element,
A method of manufacturing the thin film transistor array according to claim 1. In the fifth step, the fluctuation of the irradiation energy density of the laser beam on the amorphous silicon layer is less than about 5%.
The manufacturing method of the thin-film transistor array of any one of Claims 1-3. The wavelength range of the laser is 400 nm or more and 600 nm or less.
The manufacturing method of the thin-film transistor array of any one of Claims 1-4. In the fourth step,
Depending on the optical film thickness of the gate insulating layer normalized by the wavelength λ of the laser beam, the film thickness range of the amorphous silicon layer is set as a film thickness range of a region within a predetermined range from the first reference. The differential coefficient when the absorptance of the laser light wavelength λ of the normalized amorphous silicon layer is differentiated by the optical film thickness of the amorphous silicon layer normalized by the wavelength λ of the laser light is − Formed in a film thickness range of 5 or more and +5 or less,
The manufacturing method of the thin-film transistor array of any one of Claims 1-5. In the fourth step, the amorphous silicon layer is
The average film thickness of the amorphous silicon layer on the plurality of gate electrodes is formed so as to be included in the range represented by the following formula 1).
The manufacturing method of the thin-film transistor array of any one of Claims 1-6.
Formula 1) 0.426 ≦ n _a-Si × d _a-Si / λ _Si ≦ 0.641, where d _a-Si represents the average film thickness of the amorphous silicon layer, and λ _Si represents the laser. It represents a light wavelength, and na _-Si represents a refractive index of the amorphous silicon layer with respect to laser light having a wavelength λ. In the third step, the gate insulating layer is formed with an extinction coefficient of the gate insulating layer with respect to the wavelength of the laser light being 0.01 or less.
The manufacturing method of the thin-film transistor array of any one of Claims 1-7. The gate insulating layer is a silicon oxide film;
The manufacturing method of the thin-film transistor array of any one of Claims 1-8. The gate insulating layer is a silicon nitride film;
The manufacturing method of the thin-film transistor array of any one of Claims 1-8. The gate insulating layer is composed of a laminated film of a silicon oxide film and a silicon nitride film.
The manufacturing method of the thin-film transistor array of any one of Claims 1-8. In the third step, the gate insulating layer comprises:
An average film thickness of the gate insulating layer on the plurality of gate electrodes is formed so as to be included in a range represented by the following formula 2) or a range represented by the following formula 3).
The manufacturing method of the thin-film transistor array of any one of Claims 1-10.
Formula 2) 0.44 ≦ n _GI × d _GI /λ≦0.74,
Formula 3) 0.96 ≦ n _GI × d _GI /λ≦1.20,
Here, d _GI represents the average film thickness of the gate insulating layer, λ represents the laser beam wavelength, and n _GI represents the refractive index of the gate insulating layer with respect to the laser beam having the wavelength λ. In the third step, the gate insulating layer comprises:
An average film thickness of the gate insulating layer on the plurality of gate electrodes is formed so as to be included in a range represented by the following formula 4) or a range represented by the following formula 5).
The manufacturing method of the thin-film transistor array of any one of Claims 1-12.
Formula 4) 0.47 ≦ n _GI × d _GI /λ≦0.62.
Formula 5) 1.04 ≦ n _GI × d _GI /λ≦1.13,
Here, d _GI represents the average film thickness of the gate insulating layer, λ represents the wavelength of the laser beam, and n _GI represents the refractive index of the insulating layer with respect to the laser beam having the wavelength λ. In the third step, the gate insulating layer comprises:
A region in which an average film thickness of the silicon oxide film on the plurality of gate electrodes and an average film thickness of the silicon nitride film on the plurality of gate electrodes are represented by the following expressions 6) and 7): Formed so as to be included in the region represented by Formula 8) and Formula 9).
The manufacturing method of the thin-film transistor array of any one of Claims 1-11.
Formula 6) Y ≧ −1070X ⁶ + 1400X ⁵ −688X ⁴ + 153X ³ −12.90X ² −1.02X + 0.439,
Formula 7) Y ≦ 49.9X ⁶ −131X ⁵ + 127X ⁴ −56.8X ³ + 11.8X ² −2.01X + 0.736,
Formula 8) Y ≧ −7.34X ⁶ + 8.48X ⁵ + 8.65X ⁴ −16.0X ³ + 7.24X ² −2.04X + 0.961,
Formula 9) Y ≦ −3.75X ⁶ + 11.8X ⁵ −13.1X ⁴ + 6.09X ³ −1.12X ² −0.87X + 1.20,
_{Here, X = d SiO × n SiO} / λ, and a _{Y = d SiN × n SiN /} λ, d SiO represents an average film thickness of the silicon oxide _{film, d SiN} average of the silicon nitride film Λ represents the laser light wavelength, n _SiO represents the refractive index of the silicon oxide film with respect to the laser light with the wavelength λ, and n _SiN represents the refractive index of the silicon nitride film with respect to the laser light with the wavelength λ. Represent. In the third step, the gate insulating layer comprises:
A region in which an average film thickness of the silicon oxide film on the plurality of gate electrodes and an average film thickness of the silicon nitride film on the plurality of gate electrodes are represented by the following formulas 10) and 11): , And are formed so as to be included in the region represented by Formula 12) and Formula 13).
The manufacturing method of the thin-film transistor array of any one of Claims 1-14.
Formula 10) Y ≧ −132.6X ⁶ + 181X ⁵ −93.8X ⁴ + 21.3X ³ −1.33X ² −1.04X + 0.473,
Equation ^{11) Y ≦ 23.7X 6 -4.56X 5} -35.4X 4 + 27.2X 3 -5.75X 2 -0.973X + 0.619,
Formula 12) Y ≧ 7.46X ⁶ −32.4X ⁵ + 50.8X ⁴ −35.7X ³ + 11.0X ² −2.20X + 1.04,
Formula 13) Y ≦ −5.34X ⁶ + 16.7X ⁵ −18.7X ⁴ + 9.18X ³ −1.96X ² −0.821X + 1.13,
_{Here, X = d SiO × n SiO} / λ, and a _{Y = d SiN × n SiN /} λ, d SiO represents an average film thickness of the silicon oxide _{film, d SiN} average of the silicon nitride film Λ represents the laser light wavelength, n _SiO represents the refractive index of the silicon oxide film with respect to the laser light with the wavelength λ, and n _SiN represents the refractive index of the silicon nitride film with respect to the laser light with the wavelength λ. Represent. The second step includes
Forming an undercoat layer made of a transparent insulating film on the substrate; and forming a plurality of gate electrodes on the undercoat layer.
The manufacturing method of the thin-film transistor device of any one of Claims 1-15. A substrate,
A plurality of gate electrodes formed on the substrate;
A gate insulating layer formed in common on the plurality of gate electrodes;
A crystalline silicon layer formed on the gate insulating layer;
A source electrode and a drain electrode formed in a region on the crystalline silicon layer of each of the plurality of gate electrodes,
The crystalline silicon layer is formed by crystallizing an amorphous silicon layer formed on the gate insulating layer using laser light emitted from a laser,
The thickness of the gate insulating layer on the plurality of gate electrodes is a region in which the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser light and the equivalent oxide thickness are positively correlated. Formed with a film thickness range of
The film thickness of the amorphous silicon layer on the plurality of gate electrodes is a region where the variation of the light absorption rate with respect to the film thickness change of the amorphous silicon layer is within a predetermined range from the first reference. Formed in the film thickness range,
Thin film transistor array. The average crystal grain size of the crystalline silicon layer on the gate electrode has a negative correlation with the gate capacitance of the gate insulating layer on the gate electrode.
The thin film transistor array according to claim 17. The half width of the Raman scattering spectrum peak near 520 cm ⁻¹ in the crystalline silicon layer on the gate electrode has a positive correlation with the gate capacitance of the gate insulating layer on the gate electrode.
The thin film transistor array according to claim 17. A display device including a liquid crystal panel or an EL panel,
A thin film transistor array according to any one of claims 17 to 19, comprising:
The thin film transistor array drives the liquid crystal panel or the EL panel.
Display device.

Images