JPWO2012117960A1 - Semiconductor element and display panel - Google Patents

Semiconductor element and display panel Download PDF

Info

Publication number
JPWO2012117960A1
JPWO2012117960A1 JP2013502285A JP2013502285A JPWO2012117960A1 JP WO2012117960 A1 JPWO2012117960 A1 JP WO2012117960A1 JP 2013502285 A JP2013502285 A JP 2013502285A JP 2013502285 A JP2013502285 A JP 2013502285A JP WO2012117960 A1 JPWO2012117960 A1 JP WO2012117960A1
Authority
JP
Japan
Prior art keywords
electrodes
electrode
sub
semiconductor element
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013502285A
Other languages
Japanese (ja)
Inventor
松井　隆司
隆司 松井
塩田　素二
素二 塩田
元 長岡
元 長岡
康生 森
康生 森
裕喜 中濱
裕喜 中濱
弘規 宮崎
弘規 宮崎
圭司 青田
圭司 青田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of JPWO2012117960A1 publication Critical patent/JPWO2012117960A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14152—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

接続信頼性が低下するのを抑制することが可能な半導体素子を提供する。この半導体素子（１０）は、辺に沿って配列される複数の出力バンプ電極（１２、１４および１５）と、複数の出力バンプ電極（１２、１４および１５）に沿ってそれぞれ配列される複数のサブ電極（３２、３４および３５）と、を備える。サブ電極（３２、３４および３５）はそれぞれ出力バンプ電極（１２、１４および１５）に比べて小さい面積を有する。A semiconductor element capable of suppressing a decrease in connection reliability is provided. The semiconductor element (10) includes a plurality of output bump electrodes (12, 14 and 15) arranged along the side and a plurality of output bump electrodes (12, 14 and 15) arranged along the sides. Sub-electrodes (32, 34 and 35). The sub-electrodes (32, 34 and 35) each have a smaller area than the output bump electrodes (12, 14 and 15).

Description

この発明は、半導体素子および表示パネルに関し、特に、列状に配置される複数の電極を備えた半導体素子および表示パネルに関する。   The present invention relates to a semiconductor element and a display panel, and more particularly to a semiconductor element and a display panel provided with a plurality of electrodes arranged in a row.

従来、列状に配置される複数の電極を有する半導体素子を備えた表示パネルが知られている。図１２は、従来の一例による半導体素子を備えた表示パネルの構造を示した断面図である。図１３は、図１２の半導体素子の構造を示した平面図である。   Conventionally, a display panel including a semiconductor element having a plurality of electrodes arranged in a row is known. FIG. 12 is a cross-sectional view illustrating a structure of a display panel including a semiconductor element according to a conventional example. FIG. 13 is a plan view showing the structure of the semiconductor device of FIG.

従来の一例による表示パネル１０１は図１２に示すように、半導体素子１１０と、半導体素子１１０が実装された透明基板からなるパネル（素子実装部材）１２０とを備えている。この半導体素子１１０は図１３に示すように、２つの長辺１１１ａおよび１１１ｂと、２つの短辺１１１ｃおよび１１１ｄとを有する長方形状の主表面１１１を含んでいる。主表面１１１上には、長辺１１１ａおよび１１１ｂに沿って複数（例えば数百個）のバンプ電極１１２および複数のバンプ電極１１３がそれぞれ配列されている。複数のバンプ電極１１２は狭ピッチで配置されており、バンプ電極１１２同士の間の距離は例えば１５μｍ程度である。   As shown in FIG. 12, a display panel 101 according to a conventional example includes a semiconductor element 110 and a panel (element mounting member) 120 made of a transparent substrate on which the semiconductor element 110 is mounted. As shown in FIG. 13, the semiconductor element 110 includes a rectangular main surface 111 having two long sides 111a and 111b and two short sides 111c and 111d. On the main surface 111, a plurality (for example, several hundreds) of bump electrodes 112 and a plurality of bump electrodes 113 are arranged along the long sides 111a and 111b. The plurality of bump electrodes 112 are arranged at a narrow pitch, and the distance between the bump electrodes 112 is, for example, about 15 μm.

また、半導体素子１１０とパネル１２０との間にはＡＣＦ（異方性導電フィルム）（図示せず）が配置されており、熱圧着により半導体素子１１０がパネル１２０に実装されている。   An ACF (anisotropic conductive film) (not shown) is arranged between the semiconductor element 110 and the panel 120, and the semiconductor element 110 is mounted on the panel 120 by thermocompression bonding.

しかしながら、半導体素子１１０には図１２に示すように、熱圧着後の熱収縮により反りが発生する。この反りは半導体素子１１０のコーナー部（特に短辺部分）で最も大きくなり、導電粒子に対する押圧力が小さくなるとともに導電粒子の変形（圧縮）率が不足する。このため、半導体素子１１０とパネル１２０との間で十分な接続が得られない場合があるという不都合がある。   However, as shown in FIG. 12, the semiconductor element 110 is warped due to thermal contraction after thermocompression bonding. This warpage becomes the largest at the corner portion (particularly, the short side portion) of the semiconductor element 110, the pressing force against the conductive particles becomes small, and the deformation (compression) rate of the conductive particles becomes insufficient. For this reason, there is a disadvantage that sufficient connection may not be obtained between the semiconductor element 110 and the panel 120.

この不都合を解消するためにはバンプ電極の面積を大きくすることが効果的であり、例えば以下のような構造にすることが考えられる。具体的には図１４に示すように、半導体素子１１０のバンプ電極１１２の外側に、隣接するバンプ電極１１２に電気的に接続されたバンプ電極１１４を追加する。このように構成すれば、半導体素子１１０のバンプ電極１１２および１１４とパネル１２０の電極（図示せず）との間の接着面積が大きくなるので、半導体素子１１０とパネル１２０との間の接続信頼性が低下するのをある程度抑制することが可能である。   In order to eliminate this inconvenience, it is effective to increase the area of the bump electrode. For example, the following structure can be considered. Specifically, as shown in FIG. 14, a bump electrode 114 electrically connected to the adjacent bump electrode 112 is added outside the bump electrode 112 of the semiconductor element 110. With this configuration, since the bonding area between the bump electrodes 112 and 114 of the semiconductor element 110 and the electrode (not shown) of the panel 120 is increased, the connection reliability between the semiconductor element 110 and the panel 120 is increased. Can be suppressed to some extent.

なお、半導体素子のバンプ電極の外側にバンプ電極を追加した構造は、例えば特許文献１に開示されている。   In addition, the structure which added the bump electrode outside the bump electrode of a semiconductor element is disclosed by patent document 1, for example.

特開２００３−３０３８５２号公報JP 2003-303852 A

しかしながら、半導体素子１１０を図１４に示した構造にすると、ＡＣＦを介して半導体素子１１０をパネル１２０に熱圧着する際に、ＡＣＦに含有された導電粒子の流動性が低下する。すなわち、複数のバンプ電極１１２は狭ピッチで配置されており、もともと導電粒子はバンプ電極１１２同士の間を通過しにくい（導電粒子の流動性が低下しやすい）。この上、図１４の構造にすると、バンプ電極１１２の外側にバンプ電極１１４が配置されるので、導電粒子が通過しにくい領域（バンプ電極１１２同士の間およびバンプ電極１１４同士の間）が長くなる。このため、図１５に示すように導電粒子１３０が凝集しやすくなり、バンプ電極１１２同士の間やバンプ電極１１４同士の間で短絡が発生する場合があるという問題点がある。   However, when the semiconductor element 110 has the structure shown in FIG. 14, the fluidity of the conductive particles contained in the ACF is reduced when the semiconductor element 110 is thermocompression bonded to the panel 120 via the ACF. That is, the plurality of bump electrodes 112 are arranged at a narrow pitch, and originally the conductive particles hardly pass between the bump electrodes 112 (the fluidity of the conductive particles tends to decrease). In addition, in the structure shown in FIG. 14, since the bump electrode 114 is disposed outside the bump electrode 112, the region where the conductive particles are difficult to pass through (between the bump electrodes 112 and between the bump electrodes 114) becomes long. . For this reason, as shown in FIG. 15, the conductive particles 130 easily aggregate, and there is a problem that a short circuit may occur between the bump electrodes 112 or between the bump electrodes 114.

この発明は、上記のような課題を解決するためになされたものであり、この発明の目的は、接続信頼性が低下するのを抑制することが可能な半導体素子および表示パネルを提供することである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor element and a display panel capable of suppressing a decrease in connection reliability. is there.

上記目的を達成するために、この発明の半導体素子は、４辺を有する主表面と、４辺のうちの少なくとも対向する２辺に沿って配列される複数の機能電極と、複数の機能電極よりも外側または内側に配置され、複数の機能電極の少なくとも一部に沿って配列される複数のサブ電極と、を備え、サブ電極は機能電極に電気的に接続され、または、ダミー電極により形成されているとともに、機能電極に比べて小さい面積を有する。   To achieve the above object, a semiconductor device of the present invention comprises a main surface having four sides, a plurality of functional electrodes arranged along at least two opposing sides of the four sides, and a plurality of functional electrodes. A plurality of sub-electrodes arranged outside or inside and arranged along at least a part of the plurality of functional electrodes, the sub-electrodes being electrically connected to the functional electrodes or formed by dummy electrodes And has a smaller area than the functional electrode.

この半導体素子では、複数の機能電極に沿って複数のサブ電極を配列することによって、機能電極の周辺における電極（機能電極およびサブ電極）と素子実装部材の電極との間の接着面積が大きくなる。   In this semiconductor element, by arranging a plurality of sub-electrodes along a plurality of functional electrodes, the adhesion area between the electrodes (functional electrodes and sub-electrodes) around the functional electrodes and the electrodes of the element mounting member is increased. .

また、サブ電極は機能電極に比べて小さい面積を有するので、異方性導電層に含有される導電粒子が通過する領域（サブ電極同士の間）が狭くなるのを抑制することができる。   In addition, since the sub-electrode has a smaller area than the functional electrode, it is possible to suppress the narrowing of the region (between the sub-electrodes) through which the conductive particles contained in the anisotropic conductive layer pass.

上記半導体素子において、好ましくは、複数のサブ電極は複数の機能電極よりも外側に配置されている。このように構成すれば、サブ電極と素子実装部材との間の接続が劣化する前に、機能電極と素子実装部材との間の接続が劣化するのを抑制することができる。   In the semiconductor element, preferably, the plurality of sub-electrodes are disposed outside the plurality of functional electrodes. If comprised in this way, before the connection between a sub electrode and an element mounting member deteriorates, it can suppress that the connection between a functional electrode and an element mounting member deteriorates.

上記半導体素子において、好ましくは、サブ電極の配列方向の幅は機能電極の配列方向の幅よりも小さい。このように構成すれば、サブ電極同士の間の距離が小さくなるのを抑制することができる。   In the semiconductor element, preferably, the width in the arrangement direction of the sub-electrodes is smaller than the width in the arrangement direction of the functional electrodes. If comprised in this way, it can suppress that the distance between sub-electrodes becomes small.

上記半導体素子において、好ましくは、サブ電極の配列方向と交差する方向の長さは機能電極の配列方向と交差する方向の長さよりも小さい。このように構成すれば、導電粒子が通過する領域（機能電極同士の間およびサブ電極同士の間）が長くなるのを容易に抑制することができる。   In the semiconductor element, preferably, the length in the direction intersecting with the arrangement direction of the sub-electrodes is smaller than the length in the direction intersecting with the arrangement direction of the functional electrodes. If comprised in this way, it can suppress easily that the area | region (between functional electrodes and between sub-electrodes) which a conductive particle passes becomes long.

上記半導体素子において、好ましくは、主表面は２つの長辺および２つの短辺を有する長方形状に形成されており、複数の機能電極は長辺に沿って配列される長辺側電極列と、短辺に沿って配列される短辺側電極列とを含み、複数のサブ電極は短辺側電極列に沿って配列されている。このように構成すれば、短辺部分（短辺側電極列）の接続の劣化が抑制される。   In the semiconductor element, preferably, the main surface is formed in a rectangular shape having two long sides and two short sides, and the plurality of functional electrodes are arranged along the long sides, A plurality of sub-electrodes arranged along the short-side electrode row, including a short-side electrode row arranged along the short side. If comprised in this way, the degradation of the connection of a short side part (short side electrode row | line | column) will be suppressed.

上記複数のサブ電極が短辺側電極列に沿って配列されている半導体素子において、好ましくは、複数のサブ電極は短辺側電極列の少なくとも端部に沿って配列されている。このように構成すれば、短辺部分（短辺側電極列）の端部の接続の劣化が抑制される。   In the semiconductor element in which the plurality of sub-electrodes are arranged along the short-side electrode row, the plurality of sub-electrodes are preferably arranged along at least the end portion of the short-side electrode row. If comprised in this way, the deterioration of the connection of the edge part of a short side part (short side electrode row | line | column) will be suppressed.

上記半導体素子において、主表面は２つの長辺および２つの短辺とを有する長方形状に形成されており、複数の機能電極は長辺に沿って配列される長辺側電極列を含み、複数のサブ電極は長辺側電極列に沿って配列されていてもよい。   In the semiconductor element, the main surface is formed in a rectangular shape having two long sides and two short sides, and the plurality of functional electrodes includes a long side electrode array arranged along the long side, The sub-electrodes may be arranged along the long-side electrode row.

上記複数のサブ電極が長辺側電極列に沿って配列されている半導体素子において、好ましくは、複数のサブ電極は長辺側電極列の少なくとも端部に沿って配列されている。このように構成すれば、長辺側電極列の端部の接続の劣化が抑制される。   In the semiconductor element in which the plurality of sub-electrodes are arranged along the long-side electrode row, preferably, the plurality of sub-electrodes are arranged along at least the end portion of the long-side electrode row. If comprised in this way, the deterioration of the connection of the edge part of a long side electrode row | line | column will be suppressed.

上記半導体素子において、好ましくは、複数の機能電極は第１の面積を有する複数の第１面積電極と、第１の面積よりも小さい第２の面積を有する複数の第２面積電極とを含み、サブ電極は第１面積電極に沿って配列されておらず、第２面積電極に沿って配列されている。このように構成すれば、第２面積電極の周辺における電極（第２面積電極およびサブ電極）と素子実装部材の電極との間の接続面積が大きくなる。   In the semiconductor element, preferably, the plurality of functional electrodes include a plurality of first area electrodes having a first area, and a plurality of second area electrodes having a second area smaller than the first area, The sub-electrodes are not arranged along the first area electrode, but are arranged along the second area electrode. If comprised in this way, the connection area between the electrode (2nd area electrode and subelectrode) in the periphery of a 2nd area electrode and the electrode of an element mounting member will become large.

上記半導体素子において、好ましくは、複数の機能電極は第１のピッチで配列された複数の第１ピッチ電極と、第１のピッチよりも小さい第２のピッチで配列された複数の第２ピッチ電極とを含み、サブ電極は第１ピッチ電極に沿って配列されておらず、第２ピッチ電極に沿って配列されている。このように構成すれば、第２ピッチ電極の周辺における電極（第２ピッチ電極およびサブ電極）と素子実装部材の電極との間の接続面積が大きくなる。   In the semiconductor element, preferably, the plurality of functional electrodes are a plurality of first pitch electrodes arranged at a first pitch, and a plurality of second pitch electrodes arranged at a second pitch smaller than the first pitch. The sub-electrodes are not arranged along the first pitch electrodes, but are arranged along the second pitch electrodes. If comprised in this way, the connection area between the electrode (2nd pitch electrode and subelectrode) in the periphery of a 2nd pitch electrode and the electrode of an element mounting member will become large.

上記半導体素子において、複数の機能電極は４辺のうちの少なくとも１辺に沿って２列状に配列された外側電極列および内側電極列を含み、サブ電極は外側電極列に沿って外側電極列の外側に配列されていてもよい。   In the semiconductor element, the plurality of functional electrodes include an outer electrode row and an inner electrode row arranged in two rows along at least one of the four sides, and the sub-electrode is an outer electrode row along the outer electrode row. It may be arranged outside.

上記半導体素子において、好ましくは、サブ電極は機能電極に電気的に接続されている。   In the semiconductor element, preferably, the sub electrode is electrically connected to the functional electrode.

上記半導体素子において、好ましくは、機能電極およびサブ電極は主表面から突出したバンプ電極を含む。   In the semiconductor element, the functional electrode and the sub electrode preferably include a bump electrode protruding from the main surface.

上記半導体素子において、好ましくは、機能電極およびサブ電極は素子実装部材に異方性導電層を介して接続される。   In the semiconductor element, the functional electrode and the sub electrode are preferably connected to the element mounting member via an anisotropic conductive layer.

この発明の表示パネルは、上記の構成の半導体素子を備える。   A display panel according to the present invention includes the semiconductor element having the above-described configuration.

以上のように、本発明によれば、複数の機能電極に沿って複数のサブ電極を配列させることによって、機能電極の周辺における電極（機能電極およびサブ電極）と素子実装部材の電極との間の接着面積が大きくなる。これにより、機能電極の周辺における電極と素子実装部材の電極との間の接着強度を大きくすることができるので、半導体素子と素子実装部材との間の接続信頼性が低下するのを抑制することができる。   As described above, according to the present invention, by arranging a plurality of sub-electrodes along a plurality of functional electrodes, between the electrodes (functional electrodes and sub-electrodes) around the functional electrodes and the electrodes of the element mounting member The adhesion area of becomes larger. Thereby, since the adhesive strength between the electrode around the functional electrode and the electrode of the element mounting member can be increased, it is possible to suppress a decrease in connection reliability between the semiconductor element and the element mounting member. Can do.

また、サブ電極は機能電極に比べて小さい面積を有するので、導電粒子が通過する領域（サブ電極同士の間）が狭くなるのを抑制することができる。これにより、異方性導電層を介して半導体素子を素子実装部材に熱圧着する際に、機能電極同士の間やサブ電極同士の間で導電粒子の流動性が低下して凝集するのを抑制することができる。その結果、機能電極同士の間やサブ電極同士の間で短絡が発生するのを抑制することができるので、半導体素子の接続信頼性が低下するのを抑制することができる。   In addition, since the sub-electrode has a smaller area than the functional electrode, it is possible to suppress the narrowing of the region through which the conductive particles pass (between the sub-electrodes). As a result, when the semiconductor element is thermocompression bonded to the element mounting member via the anisotropic conductive layer, the fluidity of the conductive particles between the functional electrodes and between the sub-electrodes is prevented from being reduced and aggregated. can do. As a result, it is possible to suppress the occurrence of a short circuit between the functional electrodes or between the sub electrodes, and thus it is possible to suppress a decrease in connection reliability of the semiconductor element.

本発明の第１実施形態による半導体素子を備えた液晶表示パネルの構造を示した側面図である。1 is a side view illustrating a structure of a liquid crystal display panel including a semiconductor device according to a first embodiment of the present invention. 図１の半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element of FIG. 図１の半導体素子の出力バンプ電極およびサブ電極の構造を示した拡大平面図である。FIG. 2 is an enlarged plan view showing structures of output bump electrodes and sub-electrodes of the semiconductor element of FIG. 1. 図１のパネルの構造を示した平面図である。It is the top view which showed the structure of the panel of FIG. 本発明の第２実施形態による半導体素子の構造を示した平面図である。FIG. 6 is a plan view illustrating a structure of a semiconductor device according to a second embodiment of the present invention. 本発明の第３実施形態による半導体素子の構造を示した平面図である。FIG. 6 is a plan view illustrating a structure of a semiconductor device according to a third embodiment of the present invention. 本発明の第１変形例による半導体素子の出力バンプ電極およびサブ電極の構造を示した拡大平面図である。It is the enlarged plan view which showed the structure of the output bump electrode and subelectrode of the semiconductor element by the 1st modification of this invention. 本発明の第２変形例による半導体素子の出力バンプ電極およびサブ電極の構造を示した拡大平面図である。It is the enlarged plan view which showed the structure of the output bump electrode and subelectrode of the semiconductor element by the 2nd modification of this invention. 本発明の第３変形例による半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element by the 3rd modification of this invention. 本発明の第４変形例による半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element by the 4th modification of this invention. 本発明の第５変形例による半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element by the 5th modification of this invention. 従来の一例による半導体素子を備えた表示パネルの構造を示した断面図である。It is sectional drawing which showed the structure of the display panel provided with the semiconductor element by a conventional example. 図１２の半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element of FIG. バンプ電極の外側にバンプ電極を追加した半導体素子の構造を示した平面図である。It is the top view which showed the structure of the semiconductor element which added the bump electrode to the outer side of the bump electrode. 図１４のバンプ電極の構造を示した拡大平面図である。FIG. 15 is an enlarged plan view showing the structure of the bump electrode of FIG. 14.

以下、本発明の実施形態について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第１実施形態）
図１〜図４を参照して、本発明の第１実施形態による半導体素子１０を備えた液晶表示パネル１の構造について説明する。(First embodiment)
The structure of the liquid crystal display panel 1 including the semiconductor element 10 according to the first embodiment of the present invention will be described with reference to FIGS.

本発明の第１実施形態による液晶表示パネル（表示パネル）１は液晶表示装置（図示せず）に用いられるものである。また、液晶表示パネル１は図１に示すように、半導体素子１０と、半導体素子１０が実装されたガラス基板からなるパネル（素子実装部材）４０と、半導体素子１０およびパネル４０の間に配置されるＡＣＦ（異方性導電フィルム（異方性導電層））７０とを備えている。パネル４０は、半導体素子１０が実装されるＡＭ基板（アクティブマトリックス基板）４１と、ＡＭ基板４１に対向配置される対向基板４２とを含んでいる。また、ＡＭ基板４１と対向基板４２との間には、図示しない液晶が封入されている。   A liquid crystal display panel (display panel) 1 according to a first embodiment of the present invention is used for a liquid crystal display device (not shown). As shown in FIG. 1, the liquid crystal display panel 1 is disposed between the semiconductor element 10, a panel (element mounting member) 40 made of a glass substrate on which the semiconductor element 10 is mounted, and the semiconductor element 10 and the panel 40. ACF (anisotropic conductive film (anisotropic conductive layer)) 70. The panel 40 includes an AM substrate (active matrix substrate) 41 on which the semiconductor element 10 is mounted, and a counter substrate 42 disposed to face the AM substrate 41. Further, liquid crystal (not shown) is sealed between the AM substrate 41 and the counter substrate 42.

半導体素子１０は図２に示すように、２つの長辺１１ａおよび１１ｂと２つの短辺１１ｃおよび１１ｄとを有する長方形状の主表面１１を含んでいる。主表面１１上には、長辺１１ａおよび１１ｂに沿って（隣接して）それぞれ配列された複数（例えば数百個）の出力バンプ電極１２および複数の入力バンプ電極１３が設けられている。また、主表面１１上には、短辺１１ｃおよび１１ｄに沿ってそれぞれ配列された複数の出力バンプ電極１４および複数の出力バンプ電極１５が設けられている。すなわち、出力バンプ電極１２、入力バンプ電極１３、出力バンプ電極１４および出力バンプ電極１５は、主表面１１の周縁部に配置されている。バンプ電極（１２〜１５）は主表面１１から突出するように形成されている。なお、出力バンプ電極１２、１４、１５および入力バンプ電極１３は本発明の「機能電極」および「バンプ電極」の一例である。   As shown in FIG. 2, the semiconductor element 10 includes a rectangular main surface 11 having two long sides 11a and 11b and two short sides 11c and 11d. On the main surface 11, a plurality (for example, several hundreds) of output bump electrodes 12 and a plurality of input bump electrodes 13 arranged along (adjacent to) the long sides 11a and 11b are provided. On the main surface 11, a plurality of output bump electrodes 14 and a plurality of output bump electrodes 15 arranged along the short sides 11 c and 11 d are provided. That is, the output bump electrode 12, the input bump electrode 13, the output bump electrode 14, and the output bump electrode 15 are disposed on the peripheral edge of the main surface 11. The bump electrodes (12 to 15) are formed so as to protrude from the main surface 11. The output bump electrodes 12, 14, 15 and the input bump electrode 13 are examples of the “functional electrode” and “bump electrode” of the present invention.

そして、複数の出力バンプ電極１２により長辺側電極列２２が構成されており、複数の入力バンプ電極１３により長辺側電極列２３が構成されている。また、複数の出力バンプ電極１４により短辺側電極列２４が構成されており、複数の出力バンプ電極１５により短辺側電極列２５が構成されている。   A plurality of output bump electrodes 12 form a long side electrode array 22, and a plurality of input bump electrodes 13 form a long side electrode array 23. A plurality of output bump electrodes 14 constitute a short side electrode array 24, and a plurality of output bump electrodes 15 constitute a short side electrode array 25.

出力バンプ電極（第２面積電極）１２、１４および１５は、入力バンプ電極（第１面積電極）１３の面積（第１の面積）よりも小さい面積（第２の面積）を有する。また、出力バンプ電極（第２ピッチ電極）１２、１４および１５は、入力バンプ電極（第１ピッチ電極）１３のピッチ（第１のピッチ）よりも小さいピッチ（第２のピッチ）で配列されている。なお、出力バンプ電極１２、１４および１５は狭ピッチで配置されており、出力バンプ電極同士の間の距離は例えば１５μｍ程度である。   The output bump electrodes (second area electrodes) 12, 14 and 15 have an area (second area) smaller than the area (first area) of the input bump electrode (first area electrode) 13. The output bump electrodes (second pitch electrodes) 12, 14 and 15 are arranged at a pitch (second pitch) smaller than the pitch (first pitch) of the input bump electrodes (first pitch electrodes) 13. Yes. The output bump electrodes 12, 14 and 15 are arranged at a narrow pitch, and the distance between the output bump electrodes is, for example, about 15 μm.

ここで、主表面１１上には、出力バンプ電極１２、１４および１５に沿って複数のサブ電極３２、３４および３５がそれぞれ配列されている。具体的には、複数の出力バンプ電極１２の外側（長辺１１ａ側）に複数のサブ電極３２が配列されている。また、複数の出力バンプ電極１４の外側（短辺１１ｃ側）に複数のサブ電極３４が配列されており、複数の出力バンプ電極１５の外側（短辺１１ｄ側）に複数のサブ電極３５が配列されている。なお、サブ電極３２、３４および３５も、主表面１１から突出したバンプ電極により形成されている。   Here, on the main surface 11, a plurality of sub-electrodes 32, 34 and 35 are arranged along the output bump electrodes 12, 14 and 15, respectively. Specifically, a plurality of sub-electrodes 32 are arranged outside the plurality of output bump electrodes 12 (on the long side 11a side). A plurality of sub-electrodes 34 are arranged outside the plurality of output bump electrodes 14 (short side 11c side), and a plurality of sub-electrodes 35 are arranged outside the plurality of output bump electrodes 15 (short side 11d side). Has been. The sub electrodes 32, 34 and 35 are also formed by bump electrodes protruding from the main surface 11.

サブ電極３２は隣接する出力バンプ電極１２に電気的に接続されている。サブ電極３４は隣接する出力バンプ電極１４に電気的に接続されており、サブ電極３５は隣接する出力バンプ電極１５に電気的に接続されている。これにより、例えばサブ電極３２および出力バンプ電極１２の一方の、パネル４０に対する接続が劣化したとしても、他方がパネル４０に電気的に接続されていれば、液晶表示パネル１が誤動作するのを抑制することが可能である。なお、サブ電極３２、３４および３５はダミー電極（液晶表示パネル１の駆動に寄与しない電極）であってもよい。   The sub electrode 32 is electrically connected to the adjacent output bump electrode 12. The sub electrode 34 is electrically connected to the adjacent output bump electrode 14, and the sub electrode 35 is electrically connected to the adjacent output bump electrode 15. Thereby, for example, even if one of the sub electrode 32 and the output bump electrode 12 is deteriorated in connection with the panel 40, the liquid crystal display panel 1 is prevented from malfunctioning as long as the other is electrically connected to the panel 40. Is possible. The sub-electrodes 32, 34, and 35 may be dummy electrodes (electrodes that do not contribute to driving the liquid crystal display panel 1).

サブ電極３２は出力バンプ電極１２と同じピッチで配列されている。サブ電極３４は出力バンプ電極１４と同じピッチで配列されており、サブ電極３５は出力バンプ電極１５と同じピッチで配列されている。   The sub electrodes 32 are arranged at the same pitch as the output bump electrodes 12. The sub electrodes 34 are arranged at the same pitch as the output bump electrodes 14, and the sub electrodes 35 are arranged at the same pitch as the output bump electrodes 15.

また、図３に示すように、サブ電極３４の配列方向（Ａ方向）の幅Ｗ３４は出力バンプ電極１４の配列方向（Ａ方向）の幅Ｗ１４よりも小さく、サブ電極３４の配列方向と交差する方向（Ｂ方向）の長さＬ３４は出力バンプ電極１４の配列方向と交差する方向（Ｂ方向）の長さＬ１４よりも小さい。同様に、図２に示すように、サブ電極３２の配列方向（Ｂ方向）の幅は出力バンプ電極１２の配列方向の幅（Ｂ方向）よりも小さく、サブ電極３２の配列方向と交差する方向（Ａ方向）の長さは出力バンプ電極１２の配列方向と交差する方向（Ａ方向）の長さよりも小さい。また、サブ電極３５の配列方向（Ａ方向）の幅は出力バンプ電極１５の配列方向（Ａ方向）の幅よりも小さく、サブ電極３５の配列方向と交差する方向（Ｂ方向）の長さは出力バンプ電極１５の配列方向と交差する方向（Ｂ方向）の長さよりも小さい。このため、サブ電極３２、３４および３５はそれぞれ出力バンプ電極１２、１４および１５よりも小さい面積を有する。   Further, as shown in FIG. 3, the width W34 in the arrangement direction (A direction) of the sub electrodes 34 is smaller than the width W14 in the arrangement direction (A direction) of the output bump electrodes 14 and intersects the arrangement direction of the sub electrodes 34. The length L34 in the direction (B direction) is smaller than the length L14 in the direction (B direction) intersecting the arrangement direction of the output bump electrodes 14. Similarly, as shown in FIG. 2, the width in the arrangement direction (B direction) of the sub electrodes 32 is smaller than the width in the arrangement direction (B direction) of the output bump electrodes 12, and the direction intersecting the arrangement direction of the sub electrodes 32. The length in the (A direction) is smaller than the length in the direction (A direction) intersecting the arrangement direction of the output bump electrodes 12. Further, the width in the arrangement direction (A direction) of the sub electrodes 35 is smaller than the width in the arrangement direction (A direction) of the output bump electrodes 15, and the length in the direction (B direction) intersecting the arrangement direction of the sub electrodes 35 is The length is smaller than the length in the direction (B direction) intersecting the arrangement direction of the output bump electrodes 15. For this reason, the sub-electrodes 32, 34, and 35 have areas smaller than the output bump electrodes 12, 14, and 15, respectively.

このように、図３に示すようにサブ電極３４の幅Ｗ３４を出力バンプ電極１４の幅Ｗ１４よりも小さくすることによって、サブ電極３４同士の間の距離が小さくなるのを抑制することが可能である。これにより、ＡＣＦ７０を介して半導体素子１０をパネル４０に熱圧着する際に、ＡＣＦ７０に含有される導電粒子がサブ電極３４同士の間を通過しにくくなるのを抑制することが可能である。また、サブ電極３４の長さＬ３４を出力バンプ電極１４の長さＬ１４よりも小さくすることによって、導電粒子が通過する領域（出力バンプ電極１４同士の間およびサブ電極３４同士の間）が長くなるのを抑制することが可能である。これにより、出力バンプ電極１４同士の間やサブ電極３４同士の間で導電粒子の流動性が低下して凝集するのを抑制することが可能である。このことは、サブ電極３２および３５も同様である。なお、図３の矢印はＡＣＦ７０に含有される導電粒子の、熱圧着時の動きを示している。   As described above, by making the width W34 of the sub-electrode 34 smaller than the width W14 of the output bump electrode 14 as shown in FIG. 3, it is possible to suppress the distance between the sub-electrodes 34 from being reduced. is there. Thereby, when the semiconductor element 10 is thermocompression bonded to the panel 40 via the ACF 70, it is possible to prevent the conductive particles contained in the ACF 70 from easily passing between the sub-electrodes 34. Further, by making the length L34 of the sub electrode 34 smaller than the length L14 of the output bump electrode 14, the region through which the conductive particles pass (between the output bump electrodes 14 and between the sub electrodes 34) becomes longer. Can be suppressed. Thereby, it is possible to suppress the fluidity of the conductive particles from being reduced and aggregating between the output bump electrodes 14 and between the sub electrodes 34. The same applies to the sub-electrodes 32 and 35. In addition, the arrow of FIG. 3 has shown the motion at the time of the thermocompression bonding of the electrically-conductive particle contained in ACF70.

パネル４０のＡＭ基板４１には図４に示すように、半導体素子１０の電極に対応する複数のパッド電極が設けられている。具体的には、ＡＭ基板４１には、出力バンプ電極１２、入力バンプ電極１３、出力バンプ電極１４、１５、サブ電極３２、３４および３５にそれぞれ対応する位置に、パッド電極５２、５３、５４、５５、６２、６４および６５が設けられている。パッド電極５２は出力バンプ電極１２と例えば同じピッチ、同じ幅、同じ面積で形成されている。パッド電極５３〜５５、６２、６４および６５も同様である。なお、半導体素子１０はフェイスダウンでＡＭ基板４１に実装されるので、パッド電極５２〜５５、６２、６４および６５は半導体素子１０の電極（１２〜１５、３２、３４および３５）を反転した位置に形成されている。   The AM substrate 41 of the panel 40 is provided with a plurality of pad electrodes corresponding to the electrodes of the semiconductor element 10 as shown in FIG. Specifically, the AM substrate 41 has pad electrodes 52, 53, 54, at positions corresponding to the output bump electrode 12, the input bump electrode 13, the output bump electrodes 14, 15, and the sub electrodes 32, 34, and 35, respectively. 55, 62, 64 and 65 are provided. The pad electrode 52 is formed with the same pitch, the same width, and the same area as the output bump electrode 12, for example. The same applies to the pad electrodes 53 to 55, 62, 64 and 65. Since the semiconductor element 10 is mounted face-down on the AM substrate 41, the pad electrodes 52 to 55, 62, 64 and 65 are positions where the electrodes (12 to 15, 32, 34 and 35) of the semiconductor element 10 are inverted. Is formed.

このＡＭ基板４１（パネル４０）に半導体素子１０を実装する場合、半導体素子１０とＡＭ基板４１との間にＡＣＦ７０を挟み込んで熱圧着する。このとき、ＡＣＦ７０に含有される導電粒子の一部は、半導体素子１０に押圧されることにより、バンプ電極（１２〜１５）同士の間やサブ電極（３２、３４および３５）同士の間を通過して外側に押し出される。   When the semiconductor element 10 is mounted on the AM substrate 41 (panel 40), the ACF 70 is sandwiched between the semiconductor element 10 and the AM substrate 41 and thermocompression bonded. At this time, some of the conductive particles contained in the ACF 70 pass between the bump electrodes (12 to 15) and between the sub electrodes (32, 34 and 35) by being pressed by the semiconductor element 10. And then pushed out.

本実施形態では、上記のように、出力バンプ電極１２に沿ってサブ電極３２を配列する。これにより、出力バンプ電極１２の周辺における電極（出力バンプ電極１２およびサブ電極３２）とパネル４０の電極（パッド電極５２および６２）との間の接着面積を大きくすることができるとともに接着強度を大きくすることができる。その結果、半導体素子１０とパネル４０との間の接続信頼性が低下するのを抑制することができる。同様に、出力バンプ電極１４および１５に沿ってサブ電極３４および３５をそれぞれ配列することによって、半導体素子１０とパネル４０との間の接続信頼性が低下するのをより抑制することができる。   In the present embodiment, the sub-electrodes 32 are arranged along the output bump electrode 12 as described above. As a result, the adhesion area between the electrodes (output bump electrode 12 and sub-electrode 32) around the output bump electrode 12 and the electrodes (pad electrodes 52 and 62) of the panel 40 can be increased and the adhesive strength can be increased. can do. As a result, it is possible to suppress a decrease in connection reliability between the semiconductor element 10 and the panel 40. Similarly, by arranging the sub-electrodes 34 and 35 along the output bump electrodes 14 and 15, respectively, it is possible to further suppress a decrease in connection reliability between the semiconductor element 10 and the panel 40.

また、サブ電極３２を出力バンプ電極１２に比べて小さい面積にすることによって、ＡＣＦ７０に含有される導電粒子が通過する領域（サブ電極３２同士の間）が狭くなるのを抑制することができる。これにより、ＡＣＦ７０を介して半導体素子１０をパネル４０に熱圧着する際に、出力バンプ電極１２同士やサブ電極３２同士の間で導電粒子の流動性が低下して凝集するのを抑制することができる。その結果、出力バンプ電極１２同士の間やサブ電極３２同士の間で短絡が発生するのを抑制することができるので、半導体素子１０の接続信頼性が低下するのを抑制することができる。同様に、サブ電極３４および３５をそれぞれ出力バンプ電極１４および１５に比べて小さい面積にすることによって、半導体素子１０の接続信頼性が低下するのをより抑制することができる。   Further, by making the sub electrode 32 smaller in area than the output bump electrode 12, it is possible to suppress a narrowing of the region (between the sub electrodes 32) through which the conductive particles contained in the ACF 70 pass. Thereby, when the semiconductor element 10 is thermocompression bonded to the panel 40 via the ACF 70, the fluidity of the conductive particles is prevented from being reduced and aggregated between the output bump electrodes 12 and between the sub electrodes 32. it can. As a result, it is possible to suppress the occurrence of a short circuit between the output bump electrodes 12 and between the sub-electrodes 32, and thus it is possible to suppress the connection reliability of the semiconductor element 10 from being lowered. Similarly, by making the sub-electrodes 34 and 35 smaller in area than the output bump electrodes 14 and 15, respectively, it is possible to further suppress the connection reliability of the semiconductor element 10 from being lowered.

また、サブ電極３２（３４および３５）を出力バンプ電極１２（１４および１５）に電気的に接続することによって、導電粒子により出力バンプ電極１２（１４および１５）とサブ電極３２（３４および３５）とが電気的につながったとしても、半導体素子１０が誤動作することがない。これにより、サブ電極３２（３４および３５）を出力バンプ電極１２（１４および１５）に近づけて形成することができるので、電極の形成領域が広くなるのを抑制することができる。この効果は、サブ電極３２（３４および３５）をダミー電極により形成した場合も同様に得られる。   Further, by electrically connecting the sub electrode 32 (34 and 35) to the output bump electrode 12 (14 and 15), the output bump electrode 12 (14 and 15) and the sub electrode 32 (34 and 35) are formed by conductive particles. Are electrically connected, the semiconductor element 10 does not malfunction. Thereby, since the sub electrode 32 (34 and 35) can be formed close to the output bump electrode 12 (14 and 15), it is possible to prevent the electrode formation region from being widened. This effect can be similarly obtained when the sub electrode 32 (34 and 35) is formed of a dummy electrode.

また、サブ電極３２（３４および３５）を出力バンプ電極１２（１４および１５）よりも外側に配置している。これにより、サブ電極３２（３４および３５）とパネル４０との間の接続が劣化する前に、出力バンプ電極１２（１４および１５）とパネル４０との間の接続が劣化するのを抑制することができる。なお、出力バンプ電極１２（１４および１５）とパネル４０との間の接続が劣化しなければ、サブ電極３２（３４および３５）とパネル４０との間の接続が劣化しても問題ない。このため、サブ電極３２（３４および３５）の一部が例えば欠けてもよいので、サブ電極３２（３４および３５）を主表面１１の長辺１１ａ（短辺１１ｃおよび１１ｄ）に近づけることができる。その結果、半導体素子１０が大型化するのを抑制することができる。   Further, the sub-electrodes 32 (34 and 35) are arranged outside the output bump electrodes 12 (14 and 15). This suppresses the deterioration of the connection between the output bump electrode 12 (14 and 15) and the panel 40 before the connection between the sub electrode 32 (34 and 35) and the panel 40 deteriorates. Can do. If the connection between the output bump electrode 12 (14 and 15) and the panel 40 does not deteriorate, there is no problem even if the connection between the sub electrode 32 (34 and 35) and the panel 40 deteriorates. For this reason, a part of the sub-electrode 32 (34 and 35) may be missing, for example, so that the sub-electrode 32 (34 and 35) can be brought close to the long side 11a (short side 11c and 11d) of the main surface 11. . As a result, it is possible to suppress the semiconductor element 10 from becoming large.

また、サブ電極３２を出力バンプ電極１２の外側に配置することによって、サブ電極３２と出力バンプ電極１２との間に隙間を形成することができる。これにより、サブ電極３２の接続部分に剥がれや亀裂が生じた場合に、その剥がれや亀裂が出力バンプ電極１２の接続部分に伝わるのを抑制することができる。このため、単に出力バンプ電極１２を大きくするよりも出力バンプ電極１２の外側にサブ電極３２を配置した方が、出力バンプ電極１２の接続が劣化するのを抑制することができる。また、サブ電極３２と出力バンプ電極１２との間に樹脂（ＡＣＦ７０）が存在することにより、アンカー効果が働きそれぞれの電極での接続部の密着性が向上し、信頼性低下を抑制することができる。また、サブ電極３４および３５をそれぞれ出力バンプ電極１４および１５よりも外側に配置することによって、同様の効果が得られる。   Further, by disposing the sub electrode 32 outside the output bump electrode 12, a gap can be formed between the sub electrode 32 and the output bump electrode 12. Thereby, when peeling or a crack arises in the connection part of sub electrode 32, it can control that the peeling or crack is transmitted to the connection part of output bump electrode 12. For this reason, the connection of the output bump electrode 12 can be prevented from being deteriorated by arranging the sub electrode 32 outside the output bump electrode 12 rather than simply increasing the output bump electrode 12. In addition, the presence of the resin (ACF 70) between the sub electrode 32 and the output bump electrode 12 causes an anchor effect to improve the adhesiveness of the connecting portion at each electrode, thereby suppressing a decrease in reliability. it can. Similar effects can be obtained by disposing the sub-electrodes 34 and 35 outside the output bump electrodes 14 and 15, respectively.

また、サブ電極３２（３４および３５）の配列方向の幅を出力バンプ電極１２（１４および１５）の配列方向の幅よりも小さくすることによって、サブ電極３２（３４および３５）同士の間の距離が小さくなるのを抑制することができる。これにより、サブ電極３２（３４および３５）同士の間を導電粒子が通過しにくくなるのを抑制することができる。   Further, the distance between the sub electrodes 32 (34 and 35) is made smaller by making the width of the sub electrodes 32 (34 and 35) in the arrangement direction smaller than the width of the output bump electrodes 12 (14 and 15) in the arrangement direction. Can be suppressed. Thereby, it can suppress that it becomes difficult for a conductive particle to pass between sub-electrodes 32 (34 and 35).

また、サブ電極３２（３４および３５）の配列方向と交差する方向の長さを出力バンプ電極１２（１４および１５）の配列方向と交差する方向の長さよりも小さくする。これにより、導電粒子が通過する領域（出力バンプ電極１２（１４および１５）同士の間およびサブ電極３２（３４および３５）同士の間）が長くなるのを容易に抑制することができる。その結果、導電粒子の流動性が低下するのを抑制することができる。   Further, the length in the direction intersecting with the arrangement direction of the sub-electrodes 32 (34 and 35) is made smaller than the length in the direction intersecting with the arrangement direction of the output bump electrodes 12 (14 and 15). Thereby, it can suppress easily that the area | region (Between output bump electrodes 12 (14 and 15) and between sub-electrodes 32 (34 and 35)) through which an electroconductive particle passes becomes long. As a result, it can suppress that the fluidity | liquidity of electroconductive particle falls.

また、半導体素子１０とパネル４０との間の接続は短辺１１ｃおよび１１ｄ部分から劣化しやすい。このため、サブ電極３４および３５を短辺側電極列２４および２５（出力バンプ電極１４および１５）に沿ってそれぞれ配列することによって、短辺１１ｃおよび１１ｄ部分（短辺側電極列２４および２５）の接続の劣化を抑制することができ、特に効果的である。   In addition, the connection between the semiconductor element 10 and the panel 40 tends to deteriorate from the short sides 11c and 11d. Therefore, by arranging the sub-electrodes 34 and 35 along the short-side electrode rows 24 and 25 (output bump electrodes 14 and 15), respectively, the short-side 11c and 11d portions (short-side electrode rows 24 and 25) It is possible to suppress the deterioration of the connection, which is particularly effective.

また、半導体素子１０とパネル４０との間の接続は特に短辺側電極列２４および２５の端部（半導体素子１０のコーナー部）から劣化しやすい。このため、サブ電極３４および３５を短辺側電極列２４および２５の少なくとも端部に沿ってそれぞれ配列することによって、短辺側電極列２４および２５の端部の接続の劣化を抑制することができ、より効果的である。   Further, the connection between the semiconductor element 10 and the panel 40 tends to deteriorate particularly from the end portions (corner portions of the semiconductor element 10) of the short side electrode rows 24 and 25. For this reason, by arranging the sub-electrodes 34 and 35 along at least the end portions of the short-side electrode rows 24 and 25, respectively, it is possible to suppress the deterioration of the connection of the end portions of the short-side electrode rows 24 and 25. Can be more effective.

同様に、サブ電極３２を長辺側電極列２２の少なくとも端部に沿って配列することによって、長辺側電極列２２の端部の接続の劣化を抑制することができ、より効果的である。   Similarly, by arranging the sub-electrodes 32 along at least the end portions of the long-side electrode row 22, it is possible to suppress deterioration in connection at the end portions of the long-side electrode row 22, which is more effective. .

（第２実施形態）
この第２実施形態では図５を参照して、上記第１実施形態に比べて電極の形成領域を狭くする（回路形成領域を広くする）場合について説明する。(Second Embodiment)
In the second embodiment, referring to FIG. 5, the case where the electrode formation region is narrowed (the circuit formation region is widened) as compared with the first embodiment will be described.

本発明の第２実施形態による半導体素子１０では図５に示すように、長辺１１ａに沿って複数の出力バンプ電極１２および複数の出力バンプ電極１６が配列されている。また、短辺１１ｄに沿って複数の出力バンプ電極１７が配列されている。そして、複数の出力バンプ電極１２および１６により長辺側電極列２６が構成されており、複数の出力バンプ電極１７により短辺側電極列２７が構成されている。なお、出力バンプ電極１６および１７は本発明の「機能電極」および「バンプ電極」の一例である。   In the semiconductor device 10 according to the second embodiment of the present invention, as shown in FIG. 5, a plurality of output bump electrodes 12 and a plurality of output bump electrodes 16 are arranged along the long side 11a. A plurality of output bump electrodes 17 are arranged along the short side 11d. The plurality of output bump electrodes 12 and 16 constitute a long side electrode row 26, and the plurality of output bump electrodes 17 constitute a short side electrode row 27. The output bump electrodes 16 and 17 are examples of the “functional electrode” and the “bump electrode” in the present invention.

出力バンプ電極１６（第１面積電極）は出力バンプ電極（第２面積電極）１２の面積（第２の面積）よりも大きい面積（第１の面積）を有する。また、出力バンプ電極（第１ピッチ電極）１６は出力バンプ電極（第２ピッチ電極）１２のピッチ（第２のピッチ）よりも大きいピッチ（第１のピッチ）で配列されている。また、出力バンプ電極１６の外側にはサブ電極３２が配置されていない。このため、出力バンプ電極１６の形成領域は出力バンプ電極１２およびサブ電極３２の形成領域に比べて狭くなっているとともに、出力バンプ電極１６は出力バンプ電極１２よりも外側に配置されている。   The output bump electrode 16 (first area electrode) has an area (first area) larger than the area (second area) of the output bump electrode (second area electrode) 12. The output bump electrodes (first pitch electrodes) 16 are arranged at a pitch (first pitch) larger than the pitch (second pitch) of the output bump electrodes (second pitch electrodes) 12. Further, the sub electrode 32 is not disposed outside the output bump electrode 16. For this reason, the formation region of the output bump electrode 16 is narrower than the formation region of the output bump electrode 12 and the sub electrode 32, and the output bump electrode 16 is disposed outside the output bump electrode 12.

出力バンプ電極１７（第１面積電極）は出力バンプ電極（第２面積電極）１４の面積（第２の面積）よりも大きい面積（第１の面積）を有する。また、出力バンプ電極（第１ピッチ電極）１７は出力バンプ電極（第２ピッチ電極）１４のピッチ（第２のピッチ）よりも大きいピッチ（第１のピッチ）で配列されている。また、出力バンプ電極１７の外側にはサブ電極３５が配置されていない。このため、出力バンプ電極１７の形成領域は出力バンプ電極１４およびサブ電極３４の形成領域に比べて狭くなっているとともに、出力バンプ電極１７は出力バンプ電極１４よりも外側に配置されている。   The output bump electrode 17 (first area electrode) has an area (first area) larger than the area (second area) of the output bump electrode (second area electrode) 14. The output bump electrodes (first pitch electrodes) 17 are arranged at a pitch (first pitch) larger than the pitch (second pitch) of the output bump electrodes (second pitch electrodes) 14. Further, the sub electrode 35 is not disposed outside the output bump electrode 17. For this reason, the formation region of the output bump electrode 17 is narrower than the formation region of the output bump electrode 14 and the sub electrode 34, and the output bump electrode 17 is disposed outside the output bump electrode 14.

これにより、出力バンプ電極１６および１７の周辺の回路形成領域１０ａは、出力バンプ電極１２および１４の周辺の回路形成領域１０ｂよりも外側まで形成されている。すなわち、第２実施形態は第１実施形態に比べて回路形成領域が広くなっている。   Thereby, the circuit formation region 10a around the output bump electrodes 16 and 17 is formed to the outside of the circuit formation region 10b around the output bump electrodes 12 and 14. That is, the circuit formation area of the second embodiment is wider than that of the first embodiment.

なお、第２実施形態のその他の構造は、上記第１実施形態と同様である。   The remaining structure of the second embodiment is the same as that of the first embodiment.

本実施形態では、上記のように、サブ電極３２を、出力バンプ電極１６に沿って配列せず、出力バンプ電極１６よりも小さい面積を有する出力バンプ電極１２に沿って配列する。出力バンプ電極１２は出力バンプ電極１６に比べてパネル４０との間の接着面積が小さく、パネル４０との接続が劣化しやすい。このため、サブ電極３２を出力バンプ電極１２に沿って配列することによって、半導体素子１０の接続信頼性が低下するのを抑制することができる。また、サブ電極３２を出力バンプ電極１６に沿って配列しないことによって、出力バンプ電極１６の周辺の回路形成領域１０ａを広くすることができる。これにより、半導体素子１０が大型化するのを抑制することができる。   In the present embodiment, as described above, the sub electrodes 32 are not arranged along the output bump electrode 16 but are arranged along the output bump electrode 12 having an area smaller than that of the output bump electrode 16. The output bump electrode 12 has a smaller bonding area between the output bump electrode 16 and the panel 40 than the output bump electrode 16, and the connection with the panel 40 is likely to deteriorate. For this reason, by arranging the sub-electrodes 32 along the output bump electrodes 12, it is possible to suppress a decrease in connection reliability of the semiconductor element 10. Further, by not arranging the sub-electrodes 32 along the output bump electrode 16, the circuit formation region 10a around the output bump electrode 16 can be widened. Thereby, it can suppress that the semiconductor element 10 enlarges.

なお、第２実施形態のその他の効果は、上記第１実施形態と同様である。   The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

（第３実施形態）
この第３実施形態では図６を参照して、上記第２実施形態と異なり、サブ電極３２を長辺側電極列２６ａの端部のみに沿って配列する場合について説明する。(Third embodiment)
In the third embodiment, with reference to FIG. 6, a case where the sub-electrodes 32 are arranged only along the end portions of the long-side electrode row 26a will be described, unlike the second embodiment.

本発明の第３実施形態による半導体素子１０では図６に示すように、長辺１１ａに沿って複数の出力バンプ電極１２、複数の出力バンプ電極１８および複数の出力バンプ電極１２が配列されている。そして、複数の出力バンプ電極１２および１８により長辺側電極列２６ａが構成されている。なお、出力バンプ電極１８は本発明の「機能電極」および「バンプ電極」の一例である。   In the semiconductor device 10 according to the third embodiment of the present invention, as shown in FIG. 6, a plurality of output bump electrodes 12, a plurality of output bump electrodes 18, and a plurality of output bump electrodes 12 are arranged along the long side 11a. . A plurality of output bump electrodes 12 and 18 constitute a long side electrode row 26a. The output bump electrode 18 is an example of the “functional electrode” and “bump electrode” in the present invention.

出力バンプ電極１８の面積およびピッチは出力バンプ電極１２と同じ大きさに形成されている。なお、出力バンプ電極１８の面積およびピッチは上記第２実施形態の出力バンプ電極１６と同じ大きさであってもよい。また、出力バンプ電極１８の外側にはサブ電極３２が配置されていない。すなわち、サブ電極３２は長辺側電極列２６ａの端部のみに沿って配列されている。そして、出力バンプ電極１８の周辺の回路形成領域１０ｃは、出力バンプ電極１２の周辺の回路形成領域１０ｄよりも外側まで形成されている。   The area and pitch of the output bump electrode 18 are formed to have the same size as the output bump electrode 12. The area and pitch of the output bump electrode 18 may be the same size as the output bump electrode 16 of the second embodiment. Further, the sub electrode 32 is not disposed outside the output bump electrode 18. That is, the sub-electrodes 32 are arranged only along the end portions of the long-side electrode row 26a. The circuit formation region 10 c around the output bump electrode 18 is formed to the outside of the circuit formation region 10 d around the output bump electrode 12.

なお、第３実施形態のその他の構造は、上記第１および第２実施形態と同様である。   The remaining structure of the third embodiment is the same as that of the first and second embodiments.

本実施形態では、上記のように、複数のサブ電極３２を長辺側電極列２６ａの端部のみに沿って配列する。長辺側電極列２６ａとパネル４０との間の接続は特に長辺側電極列２６ａの端部（半導体素子１０のコーナー部）から劣化しやすい。このため、サブ電極３２を長辺側電極列２６ａの端部に沿って配列することによって、長辺側電極列２６ａの端部の接続の劣化を抑制することができ、特に効果的である。   In the present embodiment, as described above, the plurality of sub-electrodes 32 are arranged along only the end portion of the long-side electrode row 26a. The connection between the long side electrode row 26a and the panel 40 tends to deteriorate particularly from the end portion (corner portion of the semiconductor element 10) of the long side electrode row 26a. For this reason, by arranging the sub-electrodes 32 along the end portions of the long-side electrode row 26a, it is possible to suppress deterioration of connection at the end portions of the long-side electrode row 26a, which is particularly effective.

第３実施形態のその他の効果は、上記第１および第２実施形態と同様である。   Other effects of the third embodiment are the same as those of the first and second embodiments.

なお、今回開示された実施形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態の説明ではなく請求の範囲によって示され、さらに請求の範囲と均等の意味および範囲内でのすべての変更が含まれる。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims, and further includes meanings equivalent to the scope of claims and all modifications within the scope.

たとえば、上記実施形態では、表示パネルを液晶表示パネルに適用した例について示したが、本発明はこれに限らず、液晶表示パネル以外の表示パネルに適用してもよい。   For example, in the above-described embodiment, an example in which the display panel is applied to a liquid crystal display panel has been described. However, the present invention is not limited to this and may be applied to a display panel other than the liquid crystal display panel.

また、上記実施形態では、半導体素子をパネルに実装する例について示したが、本発明はこれに限らない。半導体素子をパネル以外の素子実装部材に実装してもよい。   Moreover, although the example which mounts a semiconductor element in a panel was shown in the said embodiment, this invention is not limited to this. You may mount a semiconductor element in element mounting members other than a panel.

また、上記実施形態では、機能電極（出力バンプ電極および入力バンプ電極）が４辺に沿って配列されている例について示したが、本発明はこれに限らない。機能電極は対向する２辺（例えば２つの長辺）のみに沿って配列されていてもよい。また、機能電極は３辺のみに配列されていてもよく、この場合、残りの１辺にダミー電極が配列されていてもよい。   In the above-described embodiment, an example in which functional electrodes (output bump electrodes and input bump electrodes) are arranged along four sides has been described, but the present invention is not limited to this. The functional electrodes may be arranged along only two opposite sides (for example, two long sides). Further, the functional electrodes may be arranged on only three sides, and in this case, dummy electrodes may be arranged on the remaining one side.

また、上記実施形態では、サブ電極の幅および長さを出力バンプ電極の幅および長さよりも小さくした例について示したが、本発明はこれに限らない。サブ電極の幅および長さの一方のみを、出力バンプ電極の幅および長さの一方よりも小さくしてもよい。   In the above embodiment, the example in which the width and the length of the sub electrode are made smaller than the width and the length of the output bump electrode is shown, but the present invention is not limited to this. Only one of the width and length of the sub electrode may be smaller than one of the width and length of the output bump electrode.

また、例えば上記第１実施形態では、出力バンプ電極１２（１４および１５も同様）を１列状に配列した例について示したが、本発明はこれに限らない。例えば図７に示した本発明の第１変形例による半導体素子のように構成してもよい。すなわち、出力バンプ電極１２を２列状（千鳥状）に配列し、外側電極列（長辺側電極列）１２ａおよび内側電極列（長辺側電極列）１２ｂを形成する。そして、サブ電極３２を外側電極列１２ａに沿って外側電極列１２ａの外側に配列してもよい。また、図８に示した本発明の第２変形例による半導体素子のように、サブ電極３２を外側電極列１２ａおよび内側電極列１２ｂの両方に沿って配列してもよい。なお、第１変形例のように構成すれば、第２変形例に比べて、回路形成領域を広くすることができる。   Further, for example, in the first embodiment, the example in which the output bump electrodes 12 (14 and 15 are the same) are arranged in a line is shown, but the present invention is not limited to this. For example, you may comprise like the semiconductor element by the 1st modification of this invention shown in FIG. That is, the output bump electrodes 12 are arranged in two rows (staggered) to form an outer electrode row (long side electrode row) 12a and an inner electrode row (long side electrode row) 12b. The sub-electrodes 32 may be arranged outside the outer electrode row 12a along the outer electrode row 12a. Further, the sub-electrodes 32 may be arranged along both the outer electrode row 12a and the inner electrode row 12b as in the semiconductor element according to the second modification of the present invention shown in FIG. In addition, if it comprises like a 1st modification, a circuit formation area can be enlarged compared with a 2nd modification.

また、上記第２実施形態では、出力バンプ電極１６を出力バンプ電極１２よりも大きい面積に形成した例について示したが、本発明はこれに限らない。例えば図９に示した本発明の第３変形例による半導体素子１０のように、出力バンプ電極１６を出力バンプ電極１２と同じ面積に形成するとともに、出力バンプ電極１６（第１ピッチ電極）のピッチ（第１のピッチ）を出力バンプ電極１２（第２ピッチ電極）のピッチ（第２のピッチ）よりも大きくしてもよい。このように、出力バンプ電極１６を出力バンプ電極１２と同じ面積に形成し、出力バンプ電極１６のピッチを出力バンプ電極１２のピッチよりも大きくした場合、出力バンプ電極１２は出力バンプ電極１６に比べてパネル４０との接続が劣化しやすい。このため、サブ電極３２を出力バンプ電極１２に沿って配列することは、効果的である。   In the second embodiment, the example in which the output bump electrode 16 is formed in a larger area than the output bump electrode 12 has been described. However, the present invention is not limited to this. For example, as in the semiconductor element 10 according to the third modification of the present invention shown in FIG. 9, the output bump electrode 16 is formed in the same area as the output bump electrode 12, and the pitch of the output bump electrode 16 (first pitch electrode). The (first pitch) may be larger than the pitch (second pitch) of the output bump electrode 12 (second pitch electrode). Thus, when the output bump electrode 16 is formed in the same area as the output bump electrode 12 and the pitch of the output bump electrode 16 is larger than the pitch of the output bump electrode 12, the output bump electrode 12 is compared with the output bump electrode 16. Therefore, the connection with the panel 40 is likely to deteriorate. For this reason, it is effective to arrange the sub-electrodes 32 along the output bump electrodes 12.

なお、出力バンプ電極１６を出力バンプ電極１２と同じ面積に形成し、出力バンプ電極１６のピッチを出力バンプ電極１２のピッチよりも大きくした場合に、出力バンプ電極１２の方が出力バンプ電極１６に比べてパネル４０との接続が劣化しやすいのは以下の理由によるものと考えられる。すなわち、出力バンプ電極１２は狭ピッチで配列されているので、１つの出力バンプ電極１２を囲う（保持する）ＡＣＦ７０の量が１つの出力バンプ電極１６を囲うＡＣＦ７０の量に比べて少なくなる。このため、１つの出力バンプ電極１２当りの接着強度が１つの出力バンプ電極１６当りの接着強度に比べて小さくなるので、出力バンプ電極１２が出力バンプ電極１６に比べてパネル４０との接続が劣化しやすくなると考えられる。   When the output bump electrode 16 is formed in the same area as the output bump electrode 12 and the pitch of the output bump electrode 16 is larger than the pitch of the output bump electrode 12, the output bump electrode 12 becomes the output bump electrode 16. Compared with the panel 40, the connection is likely to be deteriorated for the following reason. That is, since the output bump electrodes 12 are arranged at a narrow pitch, the amount of ACF 70 surrounding (holding) one output bump electrode 12 is smaller than the amount of ACF 70 surrounding one output bump electrode 16. For this reason, since the adhesive strength per output bump electrode 12 is smaller than the adhesive strength per output bump electrode 16, the connection between the output bump electrode 12 and the panel 40 is deteriorated compared to the output bump electrode 16. It is thought that it becomes easy to do.

また、上記実施形態では、サブ電極を３辺に沿って配列した例について示したが、本発明はこれに限らない。サブ電極を４辺に沿って配列してもよい。また、例えば図１０に示した本発明の第４変形例による半導体素子１０のように、サブ電極（３４および３５）を２辺（例えば２つの短辺）のみに沿って配列してもよい。   In the above embodiment, an example in which the sub-electrodes are arranged along three sides has been described, but the present invention is not limited to this. The sub electrodes may be arranged along the four sides. Further, for example, the sub-electrodes (34 and 35) may be arranged along only two sides (for example, two short sides) like the semiconductor element 10 according to the fourth modification of the present invention shown in FIG.

また、上記実施形態では、サブ電極を機能電極（出力バンプ電極および入力バンプ電極）の外側に配列した例について示したが、本発明はこれに限らない。例えば図１１に示した本発明の第５変形例による半導体素子１０のように、サブ電極（３２、３４および３５）を機能電極の内側に配列してもよい。この場合、サブ電極（３２、３４および３５）を隣接する機能電極と電気的に接続するのが好ましい。サブ電極を機能電極と電気的に接続すれば、機能電極とパネルとの接続が劣化したとしても、サブ電極とパネルとの接続が劣化していなければ、半導体素子１０が誤動作することがない。   In the above embodiment, an example in which the sub-electrodes are arranged outside the functional electrodes (output bump electrode and input bump electrode) has been described, but the present invention is not limited to this. For example, like the semiconductor element 10 according to the fifth modification of the present invention shown in FIG. 11, the sub-electrodes (32, 34 and 35) may be arranged inside the functional electrode. In this case, it is preferable to electrically connect the sub-electrodes (32, 34 and 35) to the adjacent functional electrodes. If the sub electrode is electrically connected to the functional electrode, even if the connection between the functional electrode and the panel is deteriorated, the semiconductor element 10 does not malfunction unless the connection between the sub electrode and the panel is deteriorated.

また、上記実施形態では、半導体素子を液晶表示パネルに実装する場合に、ＡＣＦを用いた例について示したが、本発明はこれに限らない。半導体素子を液晶表示パネルに実装する場合に、ＡＣＰ（異方性導電ペースト（異方性導電層））を用いてもよい。   Moreover, in the said embodiment, although the example using ACF was shown when mounting a semiconductor element in a liquid crystal display panel, this invention is not limited to this. When the semiconductor element is mounted on a liquid crystal display panel, ACP (anisotropic conductive paste (anisotropic conductive layer)) may be used.

また、上記実施形態では、半導体素子にバンプ電極を設け、パネル（素子実装部材）にパッド電極を設けた例について示したが、本発明はこれに限らず、半導体素子にパッド電極を設け、素子実装部材にバンプ電極を設けてもよい。なお、半導体素子にバンプ電極を形成する方がパネルにパッド電極を形成するよりも簡単にできるので、半導体素子にバンプ電極を形成する方が好ましい。   In the above embodiment, an example in which a bump electrode is provided in a semiconductor element and a pad electrode is provided in a panel (element mounting member) has been described. However, the present invention is not limited thereto, and a pad electrode is provided in a semiconductor element. Bump electrodes may be provided on the mounting member. In addition, since it is easier to form the bump electrode on the semiconductor element than to form the pad electrode on the panel, it is preferable to form the bump electrode on the semiconductor element.

１ 液晶表示パネル（表示パネル）
１０ 半導体素子
１１ 主表面
１１ａ、１１ｂ 長辺
１１ｃ、１１ｄ 短辺
１２ 出力バンプ電極（機能電極、バンプ電極、第２面積電極、第２ピッチ電極）
１２ａ 外側電極列（長辺側電極列）
１２ｂ 内側電極列（長辺側電極列）
１３ 入力バンプ電極（機能電極、バンプ電極、第１面積電極、第１ピッチ電極）
１４ 出力バンプ電極（機能電極、バンプ電極、第２面積電極、第２ピッチ電極）
１５ 出力バンプ電極（機能電極、バンプ電極、第２面積電極、第２ピッチ電極）
１６ 出力バンプ電極（機能電極、バンプ電極、第１面積電極、第１ピッチ電極）
１７ 出力バンプ電極（機能電極、バンプ電極、第１面積電極、第１ピッチ電極）
１８ 出力バンプ電極（機能電極、バンプ電極）
２２、２３、２６、２６ａ 長辺側電極列
２４、２５、２７ 短辺側電極列
３２、３４、３５ サブ電極
４０ パネル（素子実装部材）
７０ ＡＣＦ（異方性導電層）
Ｌ１４、Ｌ３４ 長さ
Ｗ１４、Ｗ３４ 幅1 Liquid crystal display panel (display panel)
DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Main surface 11a, 11b Long side 11c, 11d Short side 12 Output bump electrode (functional electrode, bump electrode, 2nd area electrode, 2nd pitch electrode)
12a Outer electrode row (long side electrode row)
12b Inner electrode row (long side electrode row)
13 Input bump electrode (functional electrode, bump electrode, first area electrode, first pitch electrode)
14 Output bump electrode (functional electrode, bump electrode, second area electrode, second pitch electrode)
15 Output bump electrode (functional electrode, bump electrode, second area electrode, second pitch electrode)
16 Output bump electrode (functional electrode, bump electrode, first area electrode, first pitch electrode)
17 Output bump electrode (functional electrode, bump electrode, first area electrode, first pitch electrode)
18 Output bump electrode (functional electrode, bump electrode)
22, 23, 26, 26a Long side electrode row 24, 25, 27 Short side electrode row 32, 34, 35 Sub electrode 40 Panel (element mounting member)
70 ACF (anisotropic conductive layer)
L14, L34 Length W14, W34 Width

Claims (15)

４辺を有する主表面と、
前記４辺のうちの少なくとも対向する２辺に沿って配列される複数の機能電極と、
前記複数の機能電極よりも外側または内側に配置され、前記複数の機能電極の少なくとも一部に沿って配列される複数のサブ電極と、
を備え、
前記サブ電極は前記機能電極に電気的に接続され、または、ダミー電極により形成されているとともに、前記機能電極に比べて小さい面積を有することを特徴とする半導体素子。A main surface having four sides;
A plurality of functional electrodes arranged along at least two opposing sides of the four sides;
A plurality of sub-electrodes arranged outside or inside the plurality of functional electrodes and arranged along at least a part of the plurality of functional electrodes;
With
The sub-electrode is electrically connected to the functional electrode or formed by a dummy electrode, and has a smaller area than the functional electrode. 前記複数のサブ電極は前記複数の機能電極よりも外側に配置されていることを特徴とする請求項１に記載の半導体素子。   The semiconductor element according to claim 1, wherein the plurality of sub-electrodes are arranged outside the plurality of functional electrodes. 前記サブ電極の配列方向の幅は前記機能電極の配列方向の幅よりも小さいことを特徴とする請求項１または２に記載の半導体素子。   3. The semiconductor device according to claim 1, wherein a width in the arrangement direction of the sub-electrodes is smaller than a width in the arrangement direction of the functional electrodes. 前記サブ電極の配列方向と交差する方向の長さは前記機能電極の配列方向と交差する方向の長さよりも小さいことを特徴とする請求項１〜３のいずれか１項に記載の半導体素子。   4. The semiconductor device according to claim 1, wherein a length in a direction intersecting with the arrangement direction of the sub-electrodes is smaller than a length in a direction intersecting with the arrangement direction of the functional electrodes. 前記主表面は２つの長辺および２つの短辺を有する長方形状に形成されており、
前記複数の機能電極は前記長辺に沿って配列される長辺側電極列と、前記短辺に沿って配列される短辺側電極列とを含み、
前記複数のサブ電極は前記短辺側電極列に沿って配列されていることを特徴とする請求項１〜４のいずれか１項に記載の半導体素子。The main surface is formed in a rectangular shape having two long sides and two short sides,
The plurality of functional electrodes include a long side electrode array arranged along the long side and a short side electrode array arranged along the short side,
5. The semiconductor device according to claim 1, wherein the plurality of sub-electrodes are arranged along the short-side electrode row. 前記複数のサブ電極は前記短辺側電極列の少なくとも端部に沿って配列されていることを特徴とする請求項５に記載の半導体素子。   The semiconductor element according to claim 5, wherein the plurality of sub-electrodes are arranged along at least an end portion of the short-side electrode row. 前記主表面は２つの長辺および２つの短辺とを有する長方形状に形成されており、
前記複数の機能電極は前記長辺に沿って配列される長辺側電極列を含み、
前記複数のサブ電極は前記長辺側電極列に沿って配列されていることを特徴とする請求項１〜６のいずれか１項に記載の半導体素子。The main surface is formed in a rectangular shape having two long sides and two short sides,
The plurality of functional electrodes include a long side electrode array arranged along the long side,
The semiconductor element according to claim 1, wherein the plurality of sub-electrodes are arranged along the long-side electrode row. 前記複数のサブ電極は前記長辺側電極列の少なくとも端部に沿って配列されていることを特徴とする請求項７に記載の半導体素子。   The semiconductor element according to claim 7, wherein the plurality of sub-electrodes are arranged along at least an end portion of the long side electrode row. 前記複数の機能電極は第１の面積を有する複数の第１面積電極と、前記第１の面積よりも小さい第２の面積を有する複数の第２面積電極とを含み、
前記サブ電極は前記第１面積電極に沿って配列されておらず、前記第２面積電極に沿って配列されていることを特徴とする請求項１〜８のいずれか１項に記載の半導体素子。The plurality of functional electrodes include a plurality of first area electrodes having a first area, and a plurality of second area electrodes having a second area smaller than the first area,
The semiconductor element according to claim 1, wherein the sub-electrodes are not arranged along the first area electrode but are arranged along the second area electrode. . 前記複数の機能電極は第１のピッチで配列された複数の第１ピッチ電極と、前記第１のピッチよりも小さい第２のピッチで配列された複数の第２ピッチ電極とを含み、
前記サブ電極は前記第１ピッチ電極に沿って配列されておらず、前記第２ピッチ電極に沿って配列されていることを特徴とする請求項１〜９のいずれか１項に記載の半導体素子。The plurality of functional electrodes include a plurality of first pitch electrodes arranged at a first pitch, and a plurality of second pitch electrodes arranged at a second pitch smaller than the first pitch,
10. The semiconductor device according to claim 1, wherein the sub-electrodes are not arranged along the first pitch electrode, but are arranged along the second pitch electrode. 11. . 前記複数の機能電極は前記４辺のうちの少なくとも１辺に沿って２列状に配列された外側電極列および内側電極列を含み、
前記サブ電極は前記外側電極列に沿って前記外側電極列の外側に配列されていることを特徴とする請求項１〜１０のいずれか１項に記載の半導体素子。The plurality of functional electrodes include an outer electrode row and an inner electrode row arranged in two rows along at least one of the four sides,
11. The semiconductor device according to claim 1, wherein the sub-electrode is arranged outside the outer electrode row along the outer electrode row. 前記サブ電極は前記機能電極に電気的に接続されていることを特徴とする請求項１〜１１のいずれか１項に記載の半導体素子。   The semiconductor element according to claim 1, wherein the sub-electrode is electrically connected to the functional electrode. 前記機能電極および前記サブ電極は前記主表面から突出したバンプ電極を含むことを特徴とする請求項１〜１２のいずれか１項に記載の半導体素子。   The semiconductor device according to claim 1, wherein the functional electrode and the sub-electrode include a bump electrode protruding from the main surface. 前記機能電極および前記サブ電極は素子実装部材に異方性導電層を介して接続されることを特徴とする請求項１〜１３のいずれか１項に記載の半導体素子。   The semiconductor element according to claim 1, wherein the functional electrode and the sub electrode are connected to an element mounting member via an anisotropic conductive layer. 請求項１〜１４のいずれか１項に記載の半導体素子を備えることを特徴とする表示パネル。   A display panel comprising the semiconductor element according to claim 1.
JP2013502285A 2011-03-02 2012-02-24 Semiconductor element and display panel Pending JPWO2012117960A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2011044827 2011-03-02
JP2011044827 2011-03-02
PCT/JP2012/054549 WO2012117960A1 (en) 2011-03-02 2012-02-24 Semiconductor element and display panel

Publications (1)

Publication Number Publication Date
JPWO2012117960A1 true JPWO2012117960A1 (en) 2014-07-07

Family

ID=46757897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013502285A Pending JPWO2012117960A1 (en) 2011-03-02 2012-02-24 Semiconductor element and display panel

Country Status (2)

Country Link
JP (1) JPWO2012117960A1 (en)
WO (1) WO2012117960A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6129671B2 (en) * 2013-07-19 2017-05-17 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP7267837B2 (en) * 2019-05-20 2023-05-02 株式会社ジャパンディスプレイ Display device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10308413A (en) * 1997-05-07 1998-11-17 Casio Comput Co Ltd Electronic component and electronic component mount module
JP3781967B2 (en) * 2000-12-25 2006-06-07 株式会社日立製作所 Display device
KR20040075377A (en) * 2003-02-20 2004-08-30 삼성전자주식회사 Drive ic and display device having the same
TWM243783U (en) * 2003-06-30 2004-09-11 Innolux Display Corp Structure of chip on glass
JP2008172117A (en) * 2007-01-15 2008-07-24 Epson Imaging Devices Corp Electrooptic device, board for electrooptic device, semiconductor element and electronic apparatus

Also Published As

Publication number Publication date
WO2012117960A1 (en) 2012-09-07

Similar Documents

Publication Publication Date Title
JP3730037B2 (en) Liquid crystal display device
WO2012121113A1 (en) Electronic circuit substrate, display device, and wiring substrate
JP4820372B2 (en) Circuit member, electrode connection structure, and display device including the same
CN110286531B (en) Display device and manufacturing method thereof
US8299631B2 (en) Semiconductor element and display device provided with the same
JP5539346B2 (en) Semiconductor chip and its mounting structure
KR102413480B1 (en) Display apparatus and method of manufacturing the same
TWI434383B (en) Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures
JP2014026042A (en) Display device
JP2012227480A (en) Display device and semiconductor integrated circuit device
WO2019148549A1 (en) Display device and chip on film structure thereof
TWI446314B (en) Pixel array substrate, conductive structure and display panel
JP4572376B2 (en) Semiconductor device manufacturing method and electronic device manufacturing method
JP5472557B1 (en) Composite electronic component and electronic device including the same
WO2012117960A1 (en) Semiconductor element and display panel
JP2010027847A (en) Structure for mounting semiconductor element, and display device having the same
US10048550B2 (en) Driver chip structure and liquid crystal display device
JP2014082282A (en) Semiconductor chip and display panel equipped with the same
TW200923494A (en) Liquid crystal display device
WO2012117959A1 (en) Semiconductor element and display panel
JP5105103B2 (en) Semiconductor device
JP2009099765A (en) Mounting structure of electronic component
JP2008203484A (en) Electrooptical device, package structure for flexible circuit board, and electronic equipment
TWI585500B (en) Contact pad array structure and electrical bonding structure using the same
CN111830754A (en) Liquid crystal display device having a plurality of pixel electrodes