JPWO2012102029A1 - Plasma display panel driving method and plasma display device - Google Patents

Abstract

Even a high-definition large-screen plasma display panel suppresses an increase in power consumption and generates stable discharge. For this purpose, a plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode is applied with a downward ramp waveform voltage that decreases toward a predetermined negative voltage. In a driving method of a plasma display panel that is driven by forming one field with a plurality of subfields having an initialization period, an address period, and a sustain period, a downward ramp waveform voltage is applied to the scan electrodes in the initialization period. The scan electrode is set to the high impedance state before, and the scan electrode potential is lowered by applying a voltage waveform that changes from a high potential to a low potential to the sustain electrode. Voltage.

Description

  The present invention relates to a plasma display device using an AC surface discharge type plasma display panel and a driving method of the plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate which are arranged to face each other.

  In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

  The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

  Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

  A subfield method is generally used as a method for displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a discharge cell.

  In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to a desired gradation value. Thus, each discharge cell emits light with the emission luminance of one field set to a desired gradation value, and an image composed of various combinations of gradation values is displayed in the image display area of the panel.

  In the subfield method, each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation for generating an initialization discharge in each discharge cell is performed. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

  In the address period, scan pulses are sequentially applied to the scan electrodes, and address pulses are selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).

  In the sustain period, a number of sustain pulses based on the gradation weights determined for each subfield are alternately applied to the display electrode pairs including the scan electrodes and the sustain electrodes. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.) Thereby, in each subfield, each discharge cell is made to emit light with the luminance according to the gradation weight. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

  In order to reduce power consumption, a technique for generating a sustain pulse to be applied to a display electrode pair during a sustain period using a power recovery circuit is disclosed (for example, see Patent Document 1). The power recovery circuit resonates the inductor provided in the power recovery circuit and the interelectrode capacitance of the display electrode pair, and recovers the electric power stored in the interelectrode capacitance in the power recovery capacitor. When a sustain pulse is applied to the display electrode pair, the power stored in the power recovery capacitor is reused by the above-described inductor, interelectrode capacitance, and resonance.

  In the above driving method, weak initializing discharge is generated in the initializing period. Therefore, it is necessary to generate a ramp waveform voltage that gradually rises or falls and applies it to one or both of the display electrode pairs.

  And in order to generate this ramp waveform voltage stably, the Miller integration circuit is mainly used (for example, refer to patent documents 2 and 3).

  However, if a high voltage is applied to the Miller integrating circuit to generate a ramp waveform voltage having a large amplitude, there is a problem that the power consumption of the Miller integrating circuit increases.

  The Miller integrating circuit uses a semiconductor element in the active region. Therefore, in a Miller integration circuit with high power consumption, the characteristics are completely different from each other in order to reduce the power consumption of individual semiconductor elements by connecting the semiconductor elements in parallel and distributing the power consumption to a plurality of semiconductor elements. It is necessary to use matched semiconductor elements. Therefore, in the Miller integrating circuit with high power consumption, the semiconductor elements that can be used for the configuration of the Miller integrating circuit are limited.

  Further, a Miller integrating circuit with high power consumption also generates a large amount of heat. Therefore, a large heat radiating plate is required to radiate the heat generated in the Miller integrating circuit. Thus, the Miller integration circuit with high power consumption is difficult to design for heat dissipation.

  And in a plasma display device using a large-screen panel with high definition, the power consumption when driving the panel increases, so the power consumption when generating the ramp waveform voltage also increases relatively, Design for heat dissipation also becomes more difficult.

Japanese Patent Laid-Open No. 11-133914 JP 2010-160226 A JP 2010-160227 A

  According to the present invention, a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode and a data electrode is applied to a scan electrode with a downward ramp waveform voltage that decreases toward a predetermined negative voltage. This is a panel driving method in which one field is constituted by a plurality of subfields each having a conversion period, an address period, and a sustain period. In this driving method, before applying the downward ramp waveform voltage to the scan electrode, the scan electrode is set to a high impedance state and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode during the initialization period. Thus, the potential of the scan electrode is lowered, and the lowered potential is set as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention applies a down-gradient waveform voltage that descends toward a predetermined negative voltage to a scan electrode in a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode. This is a panel driving method in which one field is constituted by a plurality of subfields having an initialization period, an address period, and a sustain period. In this driving method, before applying the downward ramp waveform voltage to the scan electrode, the scan electrode is set to a high impedance state and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode in the initialization period. Thus, the potential of the scan electrode is lowered, and the lowered potential is set as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a downward falling toward a predetermined negative voltage. This is a panel driving method in which one field is constituted by a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. In this driving method, before applying the downward ramp waveform voltage to the scan electrode during the erasing period, the scan electrode is set to a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode. The potential of the scan electrode is lowered, and the lowered potential is set as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a downward falling toward a predetermined negative voltage. This is a panel driving method in which one field is constituted by a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. In this driving method, before applying the downward ramp waveform voltage to the scan electrode during the erasing period, the scan electrode is set to a high impedance state and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode. The potential of the scan electrode is lowered, and the lowered potential is set as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention applies a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and a downward ramp waveform voltage falling toward a predetermined negative voltage to the scan electrode. The plasma display device includes a drive circuit that drives a panel by forming one field with a plurality of subfields having an initialization period, an address period, and a sustain period. The driving circuit of this plasma display device has a voltage waveform in which the scan electrode is set to a high impedance state and a sustain electrode is changed from a high potential to a low potential before the downward ramp waveform voltage is applied to the scan electrode during the initialization period. Is applied to lower the potential of the scan electrode, and the potential after the decrease is used as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention applies a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and a downward ramp waveform voltage falling toward a predetermined negative voltage to the scan electrode. The plasma display device includes a drive circuit that drives a panel by forming one field with a plurality of subfields having an initialization period, an address period, and a sustain period. The driving circuit of the plasma display device sets the scan electrode to a high impedance state and applies a voltage waveform that changes from a high potential to a low potential on the data electrode before applying a downward ramp waveform voltage to the scan electrode during the initialization period. Is applied to lower the potential of the scan electrode, and the potential after the decrease is used as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention provides a panel including a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period, a sustain period, and a downward descending toward a predetermined negative voltage. A plasma display device includes a driving circuit that drives a panel by forming one field with a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. The driving circuit of this plasma display device has a voltage waveform in which the scan electrode is set to a high impedance state and a sustain electrode is changed from a high potential to a low potential before the downward ramp waveform voltage is applied to the scan electrode during the initialization period. Is applied to lower the potential of the scan electrode, and the potential after the decrease is used as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

  In addition, the present invention provides a panel including a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period, a sustain period, and a downward descending toward a predetermined negative voltage. A plasma display device includes a driving circuit that drives a panel by forming one field with a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. The driving circuit of the plasma display device sets the scan electrode to a high impedance state and applies a voltage waveform that changes from a high potential to a low potential on the data electrode before applying a downward ramp waveform voltage to the scan electrode during the initialization period. Is applied to lower the potential of the scan electrode, and the potential after the decrease is used as the start voltage of the downward ramp waveform voltage.

  As a result, even a large-screen panel with high definition can suppress the increase in power consumption and generate stable discharge.

FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 4 is a diagram schematically showing an example of a circuit block constituting the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 5 is a diagram schematically showing an example of a driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 6 is a timing chart for explaining the operation of the drive circuit during the initialization period of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 7 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of a panel used in the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 8 is a diagram schematically showing another example of a drive voltage waveform applied to each electrode of the panel used in the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 9 is a timing chart for explaining the operation of the drive circuit during the initialization period of the plasma display device according to the second embodiment of the present invention. FIG. 10 is a timing chart for explaining the operation of the drive circuit during the erasing period and the initialization period of the plasma display device according to the third embodiment of the present invention. FIG. 11 is a timing chart for explaining the operation of the drive circuit during the erase period and the initialization period of the plasma display device according to the fourth embodiment of the present invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

  On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15.

  This protective layer 16 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is made of a material mainly composed of magnesium oxide (MgO).

  The protective layer 16 may be composed of one layer or may be composed of a plurality of layers. Moreover, the structure which particle | grains exist on a layer may be sufficient.

  A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. On the side surfaces of the barrier ribs 24 and on the dielectric layer 23, a phosphor layer 25R that emits red (R), a phosphor layer 25G that emits green (G), and a phosphor layer 25B that emits blue (B). Is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. For example, a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.

  The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells constituting pixels are formed at portions where display electrode pairs 14 and data electrodes 22 intersect.

  Then, discharge is generated in these discharge cells, and the phosphor layer 25 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.

  In the panel 10, one pixel is composed of three continuous discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) (red discharge cell), and a discharge cell having a phosphor layer 25G and emitting green (G) (green). And a discharge cell having a phosphor layer 25B and emitting blue (B) light (blue discharge cell).

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

  The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) extended in the horizontal direction (row direction and line direction) and n sustain electrodes SU1 to SUn (FIG. 1). The sustain electrodes 13) are arranged, and m data electrodes D1 to Dm (data electrodes 22 in FIG. 1) extending in the vertical direction (column direction) are arranged.

  One discharge cell is formed in a region where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080.

  As shown in FIGS. 1 and 2, in panel 10, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn are provided in parallel to each other. Therefore, a large interelectrode capacitance Cp exists between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.

  As shown in FIGS. 1 and 2, in panel 10, scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm intersect with each other across a discharge space. Similarly, sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm intersect each other across the discharge space. Therefore, an interelectrode capacitance Cpd exists between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, and between sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. There is also an interelectrode capacitance Cpd.

  Therefore, when viewed from the scan electrode driving circuit, scan electrode SC1 to scan electrode SCn are capacitive loads. Similarly, when viewed from the sustain electrode driving circuit, sustain electrode SU1 through sustain electrode SUn are capacitive loads.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described.

  The plasma display device in the present embodiment drives panel 10 by the subfield method. In the subfield method, one field of an image signal is divided into a plurality of subfields on the time axis, and a gradation weight is set for each subfield. Therefore, each field has a plurality of subfields having different gradation weights.

  Each subfield has an initialization period, an address period, a sustain period, and an erase period. Based on the image signal, light emission / non-light emission of each discharge cell is controlled for each subfield. That is, a plurality of gradations based on the image signal are displayed on the panel 10 by combining the light-emitting subfield and the non-light-emitting subfield based on the image signal.

  In the initializing period, an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.

  Initialization operation includes “forced initialization operation” that forcibly generates an initializing discharge in all discharge cells regardless of the operation of the immediately preceding subfield and an addressing discharge that occurs in the addressing period of the immediately preceding subfield. There is a “selective initialization operation” in which initializing discharge is selectively generated only in the discharge cells. In the forced initializing operation, the rising ramp waveform voltage and the falling ramp waveform voltage are applied to the scan electrode 12 to generate an initializing discharge in the discharge cell. In the selective initialization operation, a falling ramp waveform voltage is applied to the scan electrode 12 to selectively generate an initialization discharge in the discharge cell.

  In the present embodiment, among the plurality of subfields constituting one field, the forced initializing operation is performed in all discharge cells in the initializing period of one subfield, and in the initializing period of the other subfield. A configuration for performing the selective initialization operation in all the discharge cells will be described. However, the present invention is not limited to this configuration. For example, the configuration may be such that the forced initialization operation is performed only once for a plurality of fields. Or the structure which provides the subfield which has only one initialization period in several subfields, or the structure which provides the subfield which has only one initialization period in several fields may be sufficient.

  Hereinafter, the initialization period in which the forced initialization operation is performed is referred to as “forced initialization period”, and the subfield having the forced initialization period is referred to as “forced initialization subfield”. An initialization period for performing the selective initialization operation is referred to as a “selective initialization period”, and a subfield having the selective initialization period is referred to as a “selective initialization subfield”.

  In the present embodiment, subfield SF1 is a forced initialization subfield, and the other subfields (subfields subsequent to subfield SF2) are selective initialization subfields. However, the present invention is not limited to the above-described subfields as subfields for forced initialization subfields and subfields for selective initialization subfields. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

  In the address period, a scan pulse is applied to the scan electrode 12 and an address pulse is selectively applied to the data electrode 22 to selectively generate an address discharge in the discharge cells to emit light. Then, an address operation is performed to form wall charges in the discharge cells for generating a sustain discharge in the subsequent sustain period.

  In the sustain period, sustain pulses of the number obtained by multiplying the gradation weight set in each subfield by a predetermined proportional constant are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate an address discharge in the immediately preceding address period. A sustain discharge is generated in the discharged discharge cell, and a sustain operation for emitting light from the discharge cell is performed. This proportionality constant is a luminance multiple.

  The gradation weight represents a ratio of the magnitudes of luminance displayed in each subfield, and the number of sustain pulses corresponding to the gradation weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the gradation weight “8” emits light with a luminance about eight times that of the subfield with the gradation weight “1”, and about four times as high as the subfield with the gradation weight “2”. Emits light. Therefore, for example, if the subfield with the gradation weight “8” and the subfield with the gradation weight “2” are emitted, the discharge cell can emit light with a luminance corresponding to the gradation value “10”.

  In this way, by controlling the light emission / non-light emission of each discharge cell for each subfield in a combination according to the image signal, each subfield is selectively emitted, whereby each discharge cell emits light with various gradation values. That is, a gradation value corresponding to an image signal can be displayed on each discharge cell, and an image based on the image signal can be displayed on the panel 10.

  In the erasing period, a rising ramp waveform voltage is applied to the scan electrode 12, and a weak discharge is generated in the discharge cell that generated the sustain discharge in the immediately preceding sustain period. As a result, the wall charge in the discharge cell in which the sustain discharge has occurred is adjusted, and the wall voltage on each electrode is adjusted to a value suitable for the subsequent initialization operation.

  In this embodiment, one field is composed of 10 subfields from subfield SF1 to subfield SF10, and each subfield from subfield SF1 to subfield SF10 has (1, 2, 3, An example in which the luminance weights 6, 11, 18, 30, 44, 60, 80) are set will be described. Then, the subfield SF1 is set as a forced initialization subfield, and the subfields SF2 to SF10 are set as selective initialization subfields.

  However, in the present invention, the number of subfields constituting one field, the frequency of occurrence of forced initialization operation, the luminance weight of each subfield, and the like are not limited to the numerical values described above. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

  FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

  FIG. 3 shows data electrode D1 to data electrode Dm, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and sustain electrodes SU1 to SU1. The drive voltage waveform applied to each of the sustain electrodes SUn is shown. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

  FIG. 3 shows a subfield SF1 that is a forced initialization subfield and a subfield SF2 that is a selective initialization subfield. The subfield SF1 and the subfield SF2 are different in the waveform shape of the drive voltage applied to the scan electrode 12 during the initialization period.

  Although the subfields after subfield SF3 are not shown, each subfield except subfield SF1 is a selective initialization subfield, and substantially the same drive voltage waveform in each period except the number of sustain pulses. Is generated.

  First, subfield SF1, which is a forced initialization subfield, will be described.

  In the first half of the initializing period of subfield SF1 in which the forced initializing operation is performed, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, and voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn. Apply. A voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as an “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. ) Is applied. At this time, voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn, and voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. To do.

  While the rising ramp waveform voltage rises, scan electrode SC1 to scan electrode SCn and sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode SCn and data electrode D1 to data electrode Dm of each discharge cell. In between, weak initializing discharges are continuously generated. Negative wall voltage is accumulated on scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated on data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  When the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vi2, the voltage of scan electrode SC1 through scan electrode SCn is lowered to voltage Vs lower than voltage Vi2. At this time, the voltage applied to sustain electrode SU1 through sustain electrode SUn is once increased from voltage 0 (V) to voltage Vs.

  In the latter half of the initialization period of subfield SF1, positive voltage Ve lower than voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Therefore, the potentials of sustain electrode SU1 through sustain electrode SUn are reduced from high potential voltage Vs to low potential Ve. The voltage 0 (V) is kept applied to the data electrodes D1 to Dm. A scan waveform SC1 to scan electrode SCn is applied with a ramp waveform voltage (hereinafter referred to as “down ramp waveform voltage”) that gently falls from voltage Vq lower than voltage Vs to negative voltage Vi3. Voltage Vq is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn, and voltage Vi3 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.

  While this downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn, between discharge electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn. And a weak initializing discharge are generated between data electrode D1 and data electrode Dm. Thereby, the negative wall voltage on scan electrode SC1 through scan electrode SCn and the positive wall voltage on sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage on data electrode D1 through data electrode Dm The voltage is adjusted to a voltage suitable for the writing operation in the period.

  The above voltage waveform is a forced initializing waveform that generates an initializing discharge in the discharge cell regardless of the operation of the immediately preceding subfield. The operation for applying the forced initialization waveform to the scan electrode 12 is the forced initialization operation.

  Thus, the forced initializing operation in the initializing period of the forced initializing subfield (subfield SF1) is completed. In the initializing period of the forced initializing subfield, initializing discharge is forcibly generated in all the discharge cells in the image display area of panel 10.

  In the address period of subfield SF1, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn are applied to scan electrode SC1. A voltage Vc is applied.

  Next, a negative scan pulse having a negative voltage Va is applied to the first (first row) scan electrode SC1 in terms of arrangement. Then, a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.

  In the discharge cell at the intersection of the data electrode Dk to which the address pulse voltage Vd is applied and the scan electrode SC1 to which the scan pulse voltage Va is applied, the voltage difference between the data electrode Dk and the scan electrode SC1 exceeds the discharge start voltage. A discharge occurs between the data electrode Dk and the scan electrode SC1.

  In addition, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, sustain electrode SU1 in the region intersecting data electrode Dk is induced by the discharge generated between data electrode Dk and scan electrode SC1. Discharge also occurs between scan electrode SC1 and scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied.

  In the discharge cell in which the address discharge has occurred, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk.

  In this way, the address operation in the discharge cells in the first row is completed. In the discharge cell having the data electrode Dh to which the address pulse is not applied (the data electrode Dh is the data electrode D1 to the data electrode Dm excluding the data electrode Dk), the intersection of the data electrode Dh and the scan electrode SC1. Since the voltage of the portion does not exceed the discharge start voltage, the address discharge does not occur, and the wall voltage after the initialization period is maintained.

  Next, a scan pulse of the voltage Va is applied to the second (second row) scan electrode SC2 from the top, and the voltage Vd is applied to the data electrode Dk corresponding to the discharge cell to emit light in the second row. Apply the write pulse. As a result, address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Thus, the address operation in the discharge cells in the second row is performed.

  A similar address operation is sequentially performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn up to the discharge cell in the n-th row, and the address period of subfield SF1 is completed. In this manner, in the address period, address discharge is selectively generated in the discharge cells to emit light, and wall charges for sustain discharge are formed in the discharge cells.

  Note that voltage Ve applied to sustain electrode SU1 through sustain electrode SUn in the second half of the initialization period and voltage Ve applied to sustain electrode SU1 through sustain electrode SUn during the write period may be different from each other.

  In the sustain period of subfield SF1, voltage 0 (V) is first applied to sustain electrode SU1 through sustain electrode SUn. Then, sustain pulse of positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn.

  In the discharge cell in which the address discharge is generated in the address period by the application of the sustain pulse, the voltage difference between the scan electrode SCi and the sustain electrode SUi exceeds the discharge start voltage, and the sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi. Will occur. The phosphor layer 25 of the discharge cell in which the sustain discharge has occurred emits light by the ultraviolet rays generated by the sustain discharge. In addition, due to the sustain discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. However, no sustain discharge occurs in the discharge cells in which no address discharge has occurred during the address period.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Similarly, sustain pulses of the number obtained by multiplying the gradation weight by a predetermined luminance multiple are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. Thus, the discharge cells that have generated the address discharge in the address period generate the sustain discharges the number of times corresponding to the gradation weight, and emit light with the luminance corresponding to the gradation weight.

  Thus, the sustain operation in the sustain period of subfield SF1 is completed.

  In the erasing period of subfield SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn have a voltage lower than the discharge start voltage. To a negative voltage Vi3 exceeding the discharge start voltage, a downward ramp waveform voltage that gently falls at the same gradient as the downward ramp waveform voltage generated in the forced initialization period is applied.

  While applying the downward ramp waveform voltage to scan electrode SC1 through scan electrode SCn, a weak discharge (erase discharge) is continuously generated in a discharge cell that has generated a sustain discharge in the immediately preceding sustain period. When the decreasing voltage reaches predetermined voltage Vi3, the voltage applied to scan electrode SC1 through scan electrode SCn is increased to voltage 0 (V).

  Subsequently, an upward ramp waveform voltage that gently rises from voltage 0 (V) to voltage Vr is applied to scan electrode SC1 through scan electrode SCn.

  By setting the voltage Vr to a voltage exceeding the discharge start voltage, a sustain discharge is generated in the immediately preceding sustain period while the rising ramp waveform voltage applied to scan electrode SC1 to scan electrode SCn rises above the discharge start voltage. A weak discharge (erase discharge) is continuously generated between the sustain electrode SUi and the scan electrode SCi of the discharge cell.

  The charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thereby, the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi are weakened while the positive wall voltage on data electrode Dk remains. Thus, unnecessary wall charges in the discharge cell are erased.

  When the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V). Thus, the erase operation in the erase period of subfield SF1 is completed.

  Thus, the subfield SF1 is completed.

  Next, the selective initialization subfield will be described by taking the subfield SF2 as an example.

  In the initialization period of subfield SF2, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage Vs is once applied to sustain electrode SU1 to sustain electrode SUn, and then lower than voltage Vs. A positive voltage Ve is applied.

  Scanning electrode SC1 to scanning electrode SCn are applied with a descending ramp waveform voltage that descends at the same gradient as the descending ramp waveform voltage generated in the forced initialization period from a voltage lower than the discharge start voltage toward negative voltage Vi3. The voltage Vi3 is set to a voltage exceeding the discharge start voltage.

  In the discharge cell in which the sustain discharge is generated in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 3) while applying this downward ramp waveform voltage to scan electrode SC1 through scan electrode SCn, the sustain electrode is maintained as scan electrode SCi. A weak initializing discharge is generated between the electrode SUi and between the scan electrode SCi and the data electrode Dk.

  This initialization discharge weakens the negative wall voltage on scan electrode SCi and the positive wall voltage on sustain electrode SUi. In addition, an excessive portion of the positive wall voltage on the data electrode Dk is discharged. Thus, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation in the address period.

  On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1), the initialization discharge does not occur and the previous wall voltage is maintained.

  The voltage waveform described above is a selective initializing waveform in which initializing discharge is selectively generated in the discharge cells that have performed the addressing operation in the address period (here, the address period) of the immediately preceding subfield. The operation of applying the selective initialization waveform to the scan electrode 12 is the selective initialization operation.

  Thus, the selective initialization operation in the initialization period of subfield SF2, which is a selective initialization subfield, is completed.

  In the address period of the subfield SF2, the same drive voltage waveform as that in the address period of the subfield SF1 is applied to each electrode. In the subsequent sustain period, as in the sustain period of subfield SF1, the number of sustain pulses corresponding to the gradation weight is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. In the subsequent erasing period, the same drive voltage waveform as that in the erasing period of the subfield SF1 is applied to each electrode.

  In each subfield after subfield SF3, the same drive voltage waveform as in subfield SF2 is applied to each electrode except for the number of sustain pulses generated in the sustain period.

  The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vi1 = 150 (V), voltage Vi2 = 350 (V), voltage Vi3 = −200 (V), voltage Vc = −70 (V ), Voltage Va = −220 (V), voltage Vs = 200 (V), voltage Vq = 150 (V), voltage Ve = 120 (V), voltage Vr = 200 (V), voltage Vd = 60 (V) It is. Further, the gradient of the rising ramp waveform voltage generated in the initialization period is about 1.3 V / μsec, and the gradient of the rising ramp waveform voltage generated in the erasing period is about 10 V / μsec. The slope of the downward ramp waveform voltage generated at ˜ is about −1.5 V / μsec.

  In the present embodiment, the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient. Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, subfield SF1 is a forced initialization subfield for performing a forced initialization operation, and other subfields (subfields subsequent to subfield SF2) are a selective initialization subfield for performing a selective initialization operation. However, the present invention is not limited to this configuration. For example, the subfield SF1 may be a selective initialization subfield and other subfields may be forced initialization subfields, or a plurality of subfields may be forced initialization subfields.

  As described above, in the subfield method, one field is composed of a plurality of subfields in which gradation weights are determined in advance. Then, by combining a subfield that is lit (lighting subfield) and a subfield that is not lit (non-lighting subfield), each discharge cell emits light with a light emission luminance corresponding to the magnitude of the gradation value based on the image signal. .

  Next, the configuration of the plasma display device in the present embodiment will be described.

  FIG. 4 is a diagram schematically showing an example of a circuit block constituting the plasma display device 30 according to the first embodiment of the present invention.

  The plasma display device 30 includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

  The image signals input to the image signal processing circuit 31 are a red image signal, a green image signal, and a blue image signal. Based on the red image signal, the green image signal, and the blue image signal, the image signal processing circuit 31 sets each gradation value of red, green, and blue (a gradation value expressed by one field) to each discharge cell. To do. In the image signal processing circuit 31, the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal). In some cases, a red image signal, a green image signal, and a blue image signal are calculated based on the luminance signal and the saturation signal, and then, each gradation value of red, green, and blue is set in each discharge cell. Then, the red, green, and blue gradation values set in each discharge cell are associated with image data indicating lighting / non-lighting for each subfield (light emission / non-light emission corresponds to digital signals “1” and “0”). Data) and output. That is, the image signal processing circuit 31 converts the red image signal, the green image signal, and the blue image signal into red image data, green image data, and blue image data and outputs the converted image data.

  The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).

  Scan electrode drive circuit 33 includes a ramp waveform generation unit, a sustain pulse generation unit, and a scan pulse generation unit (not shown in FIG. 4), and generates a drive voltage waveform based on a timing signal supplied from timing generation circuit 35. And applied to each of scan electrode SC1 to scan electrode SCn. The ramp waveform generator generates a forced initialization waveform and a selective initialization waveform to be applied to scan electrode SC1 through scan electrode SCn during the initialization period based on the timing signal. Sustain pulse generating unit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period based on the timing signal. The scan pulse generator includes a plurality of scan electrode drive ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 to scan electrode SCn in the address period based on the timing signal.

  Sustain electrode drive circuit 34 includes a sustain pulse generation unit and a circuit (not shown in FIG. 4) for generating voltage Ve, and generates and maintains a drive voltage waveform based on the timing signal supplied from timing generation circuit 35. It applies to each of electrode SU1-sustain electrode SUn. In the sustain period, a sustain pulse is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn. In the initialization period and the address period, voltage Ve is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn.

  The data electrode drive circuit 32 generates an address pulse corresponding to each of the data electrodes D1 to Dm based on the image data of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. . The data electrode drive circuit 32 applies the address pulse to the data electrodes D1 to Dm during the address period.

  Next, details and operation of the drive circuit included in the plasma display device 30 will be described.

  FIG. 5 is a diagram schematically showing an example of a drive circuit of plasma display device 30 in the first exemplary embodiment of the present invention.

  FIG. 5 shows details of scan electrode drive circuit 33, sustain electrode drive circuit 34, and data electrode drive circuit 32.

  FIG. 5 also shows the interelectrode capacitance Cp and the interelectrode capacitance Cpd of the panel 10. Interelectrode capacitance Cp is an interelectrode capacitance generated between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. Interelectrode capacitance Cpd is an interelectrode capacitance generated between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm Between the electrodes.

  Scan electrode drive circuit 33 includes sustain pulse generator 50, first ramp waveform voltage generator 55, second ramp waveform voltage generator 56, reference potential setting unit 57, separation unit 58, and scan pulse generator 59. Have.

  Sustain electrode drive circuit 34 has a sustain pulse generator 60 and a reference potential setting unit 65.

  The sustain pulse generation unit 50 of the scan electrode drive circuit 33 includes a first power recovery unit 51 and a first clamp unit 53.

  The first power recovery unit 51 includes a capacitor C51, a switching element Q51, a switching element Q52, a diode Di51, a diode Di52, and an inductor L51.

  The first clamp part 53 includes a switching element Q53 and a switching element Q54.

  First power recovery unit 51 resonates interelectrode capacitance Cp between scan electrode SC <b> 1 through scan electrode SCn and sustain electrode SU <b> 1 through sustain electrode SUn, and inductor L <b> 51 to rise and fall the sustain pulse. .

  At the rise of the sustain pulse, the interelectrode capacitance Cp and the inductor L51 are resonated, and a current is passed from the capacitor C51 to the scan electrode SC1 to the scan electrode SCn via the switching element Q51, the diode Di51, and the inductor L51, and stored in the capacitor C51. The generated charge is moved to the interelectrode capacitance Cp.

  At the fall of the sustain pulse, the interelectrode capacitance Cp and the inductor L51 are caused to resonate, and the electric charge stored in the interelectrode capacitance Cp is collected in the capacitor C51 via the inductor L51, the diode Di52, and the switching element Q52.

  In this way, the first power recovery unit 51 rises and falls the sustain pulse that changes from the positive voltage Vs to the voltage 0 (V). The first power recovery unit 51 drives the scan electrodes SC1 to SCn by LC resonance without being supplied with power from the power source. Therefore, the power consumption in the first power recovery unit 51 is ideally “0”. The capacitor C51 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to an intermediate potential (voltage Vs / 2) between the voltage Vs and the voltage 0 (V). Work as a power source.

  First clamp portion 53 conducts switching element Q53 to clamp scan electrode SC1 through scan electrode SCn to positive voltage Vs. Further, by turning on switching element Q54, scan electrode SC1 through scan electrode SCn are clamped to voltage 0 (V). Thus, the first clamp unit 53 clamps the voltage of the sustain pulse applied to scan electrode SC1 through scan electrode SCn to voltage Vs or voltage 0 (V). Therefore, the impedance when the voltage is applied to scan electrode SC1 through scan electrode SCn by first clamp portion 53 is relatively small, and a large discharge current due to a strong sustain discharge can flow stably.

  In this way, the first power recovery unit 51 and the first clamp unit 53, based on the timing signal supplied from the timing generation circuit 35, set the voltage at the node P59, which is the reference potential of the scan pulse generation unit 59, The voltage Vs is changed to voltage 0 (V), and the voltage 0 (V) is changed to voltage Vs. Thus, the sustain pulse is applied to scan electrode SC1 through scan electrode SCn, which is one end of interelectrode capacitance Cp, via scan pulse generator 59 that is in a short-circuit state during the sustain period.

  Note that sustain pulse generator 50, first ramp waveform voltage generator 55, second ramp waveform voltage generator 56, reference potential setting unit 57, and scan pulse generator 59 are electrically connected to node P59. It is a connection point.

  The first ramp waveform voltage generator 55 has a Miller integrating circuit. This Miller integrating circuit is a ramp waveform voltage generating circuit that generates a ramp waveform voltage that rises during the initialization period and the erase period.

  This Miller integrating circuit is composed of a switching element Q55, a capacitor C55, and a resistor R55, and raises the voltage at the node P59 to a positive voltage Vr to generate an up-slope waveform voltage.

  The second ramp waveform voltage generator 56 has a Miller integrating circuit. This Miller integrating circuit is a ramp waveform voltage generating circuit that generates a ramp waveform voltage that falls during the initialization period and the erase period.

  This Miller integrating circuit is constituted by a switching element Q56, a capacitor C56, and a resistor R56. The Miller integrating circuit lowers the voltage at the node P59 to a negative voltage Vi3 to generate a downward ramp waveform voltage.

  The reference potential setting unit 57 includes a switching element Q57. Then, by turning on the switching element Q57, the voltage at the node P59 is clamped to the negative voltage Va.

  The separation unit 58 includes a switching element Q58. When negative voltage Vi3 or negative voltage Va is applied to scan electrode SC1 through scan electrode SCn, switching element Q58 is cut off to prevent a through current from flowing through switching element Q54, and ground potential (voltage 0 The current can be prevented from flowing from (V)) to the voltage Vi3 or from the ground potential (voltage 0 (V)) to the voltage Va.

  Scan pulse generating unit 59 includes power supply E59, switching element Q5H1 to switching element Q5Hn, and switching element Q5L1 to switching element Q5Ln.

  The power supply E59 superimposes a positive voltage Vq on the voltage at the node P59, which is the reference potential of the scan pulse generator 59. Switching element Q5H1 to switching element Q5Hn applies a voltage on the high voltage side of power supply E59 (that is, a voltage in which positive voltage Vq is superimposed on node P59) to scan electrode SC1 to scan electrode SCn. Switching element Q5L1 to switching element Q5Ln applies the voltage on the low voltage side of power supply E59 (that is, the voltage at node P59) to scan electrode SC1 to scan electrode SCn.

  In scan pulse generator 59 configured in this manner, in the address period, switching element Q57 is turned on to connect node P59 to negative voltage Va, and negative voltage Va is applied to switching elements Q5L1 to Q5Ln. The voltage Vc, which is the voltage Va + voltage Vq, is applied to the switching elements Q5H1 to Q5Hn. Then, based on the timing signal supplied from the timing generation circuit 35, the switching element Q5Hi is turned off and the switching element Q5Li is turned on for the scan electrode SCi to which the scan pulse is applied. Then, the scan pulse of the negative voltage Va is applied to the scan electrode SCi. For the scan electrode SCh to which no scan pulse is applied (h is a value obtained by excluding i from 1 to n), the switching element Q5Lh is turned off and the switching element Q5Hh is turned on, whereby the switching element Q5Hh is turned on. The voltage Va + voltage Vq is applied to the scan electrode SCh via.

  In this embodiment, voltage Vq = 150 (V), voltage Vc is equal to voltage (Vq + Va), and voltage Vi2 is equal to voltage (Vr + Vq).

  Sustain pulse generation unit 60 of sustain electrode drive circuit 34 includes a second power recovery unit 61 and a second clamp unit 63.

  The second power recovery unit 61 includes a capacitor C61, a switching element Q61, a switching element Q62, a diode Di61, a diode Di62, and an inductor L61.

  The second clamp part 63 has a switching element Q63 and a switching element Q64.

  Second power recovery unit 61 resonates interelectrode capacitance Cp between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and inductor L61 to perform rise and fall of the sustain pulse. .

  At the rise of the sustain pulse, the interelectrode capacitance Cp and the inductor L61 are caused to resonate, and a current flows from the capacitor C61 to the sustain electrode SU1 through the sustain electrode SUn via the switching element Q61, the diode Di61, and the inductor L61, and is stored in the capacitor C61. The generated charge is moved to the interelectrode capacitance Cp.

  At the fall of the sustain pulse, the interelectrode capacitance Cp and the inductor L61 are caused to resonate, and the electric charge stored in the interelectrode capacitance Cp is recovered in the capacitor C61 via the inductor L61, the diode Di62, and the switching element Q62.

  In this way, the second power recovery unit 61 rises and falls the sustain pulse that changes from the positive voltage Vs to the voltage 0 (V). The second power recovery unit 61 drives the sustain electrodes SU1 to SUn by LC resonance without being supplied with power from the power source. Therefore, the power consumption in the second power recovery unit 61 is ideally “0”. The capacitor C61 has a capacity sufficiently larger than the interelectrode capacity Cp, is charged to an intermediate potential (voltage Vs / 2) between the voltage Vs and the voltage 0 (V), and the second power recovery unit 61 Work as a power source.

  Second clamp portion 63 conducts switching element Q63 to clamp sustain electrode SU1 through sustain electrode SUn to positive voltage Vs. In addition, by making switching element Q64 conductive, sustain electrode SU1 through sustain electrode SUn are clamped to voltage 0 (V). As described above, the second clamp unit 63 clamps the voltage of the sustain pulse applied to the sustain electrode SU1 to the sustain electrode SUn to the voltage Vs or the voltage 0 (V). Therefore, the impedance when the voltage is applied to sustain electrode SU1 through sustain electrode SUn by second clamp portion 63 is relatively small, and a large discharge current due to a strong sustain discharge can flow stably.

  In this way, the second power recovery unit 61 and the second clamp unit 63 generate the voltage applied to the sustain electrodes SU1 to SUn from the voltage Vs based on the timing signal supplied from the timing generation circuit 35. The voltage is changed to 0 (V), and the voltage is changed from 0 (V) to the voltage Vs. Thus, sustain electrode drive circuit 34 applies the sustain pulse to sustain electrode SU1 through sustain electrode SUn, which is one end of interelectrode capacitance Cp.

  Reference potential setting unit 65 includes switching element Q65 and switching element Q66. Then, switching element Q65 and switching element Q66 are rendered conductive during the initialization period and the writing period, whereby sustain electrode SU1 through sustain electrode SUn are clamped to positive voltage Ve.

  The data electrode drive circuit 32 has the same number of switching elements Q71 and switching elements Q72 as the data electrodes 22 (only one switching element Q71 and one switching element Q72 are shown in FIG. 5).

  In the present embodiment, since the number of data electrodes 22 is “m”, the data electrode driving circuit 32 has m switching elements Q71 and switching elements Q72. Each of the m switching elements Q71 and Q72 has a connection point between the switching element Q71 and the switching element Q72 connected to each of the m data electrodes D1 to Dm.

  The data electrode drive circuit 32 generates an address pulse corresponding to each of the data electrodes D1 to Dm based on the image data of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. .

  That is, the data electrode drive circuit 32 performs an operation of turning on the switching element Q71 and cutting off the switching element Q72 based on image data and an operation of turning off the switching element Q71 and turning on the switching element Q72 based on the image data during the writing period. The address pulse (address pulse voltage Vd or 0 (V)) is applied to each of the data electrodes D1 to Dm.

  Data electrode drive circuit 32 includes switching element Q71 and switching element Q72 for selectively applying voltage Vd to sustain electrode SU1 through sustain electrode SUn in accordance with image display data during the write period.

  Next, drive voltages applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn during the initializing period (forced initializing period) of the forced initializing subfield (in this embodiment, subfield SF1). The operation of the drive circuit when generating a waveform will be described.

  FIG. 6 is a timing chart for explaining the operation of the drive circuit during the initialization period of plasma display device 30 in the first exemplary embodiment of the present invention.

  FIG. 6 shows drive voltage waveforms applied to scan electrode SC1 through scan electrode SCn and drive voltage waveforms applied to sustain electrode SU1 through sustain electrode SUn. In this drawing, the voltage waveform generated during the forced initializing operation will be described as an example. However, in the selective initializing operation and the operation of generating the downward ramp waveform voltage in the erasing period, the downward ramp waveform voltage described in FIG. This is similar to the operation that occurs.

  In FIG. 6, the voltage waveform generated when the forced initialization operation is performed is divided into three periods indicated by a period T11, a period T12, and a period T13, and each period is described. Further, in the drawing, the conduction of the switching element is expressed as “ON”, and the disconnection is expressed as “OFF”.

(Period T11)
In the period T11, first, the switching element Q54 and the switching element Q58 are turned on, the switching element Q51, the switching element Q52, the switching element Q53, the switching element Q55, the switching element Q56, and the switching element Q57 are turned off. Is set to a voltage of 0 (V). Then, switching element Q5L1 to switching element Q5Ln are turned on, switching element Q5H1 to switching element Q5Hn are turned off, and voltage at node P59 is applied to scan electrode SC1 to scan electrode SCn. As a result, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn.

  Further, switching element Q64 is turned on, switching element Q61, switching element Q62, switching element Q63, switching element Q65, and switching element Q66 are turned off, and voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. .

  Next, at time t1, switching element Q5L1 to switching element Q5Ln are turned off, and switching element Q5H1 to switching element Q5Hn are turned on. Thereby, a voltage obtained by superimposing voltage Vq on voltage of node P59 is applied to scan electrode SC1 through scan electrode SCn. At this time, since the voltage at node P59 is voltage 0 (V), voltage Vq is applied to scan electrode SC1 through scan electrode SCn.

  Next, at time t2, the switching element Q54 of the first clamp unit 53 is turned off, and the voltage at the node P59 is in a high impedance state (a state in which the voltage is electrically cut off from the power supply, ground potential, circuit output terminal, etc. ).

  Next, a voltage is applied to the resistor R55 of the first ramp waveform voltage generator 55, and a constant current is passed toward the capacitor C55. Thereby, the switching element Q55 is turned on, the source voltage of the switching element Q55 increases from the voltage 0 (V) in a ramp shape, and the output voltage of the scan electrode drive circuit 33 starts to increase from the voltage Vq in a ramp shape. At this time, the voltage applied to the resistor R55 is adjusted so that the gradient of the ramp waveform voltage becomes a desired value (for example, 1.3 V / μsec).

  Thus, an upward ramp waveform voltage rising from the voltage Vi1 (equal to the voltage Vq in the present embodiment) toward the voltage Vi2 (equal to the voltage Vq + the voltage Vr in the present embodiment) is generated. This voltage increase continues during the period when the voltage is applied to the resistor R55 or until the voltage at the node P59 reaches the voltage Vr.

  In the period T11, the voltage Vi1 (equal to the voltage Vq in the present embodiment) is gradually increased in this way toward the voltage Vi2 (equal to the voltage Vq + the voltage Vr in the present embodiment) exceeding the discharge start voltage. Ascending rising ramp waveform voltage is generated and applied to scan electrode SC1 through scan electrode SCn.

(Period T12)
In the period T12, first, at time t3, the switching element Q55 of the first ramp waveform voltage generation unit 55 is turned off, the switching element Q53 of the first clamp unit 53 is turned on, and the switching elements Q5H1 to Q51 of the scan pulse generation unit 59 are turned on. Switching element Q5Hn is turned off, and switching element Q5L1 to switching element Q5Ln are turned on. Thereby, scan electrode SC1 to scan electrode SCn are clamped to voltage Vs.

  Next, at time t4, the switching element Q64 of the second clamp part 63 of the sustain electrode drive circuit 34 is turned off, and the switching element Q61 of the second power recovery part 61 is turned on. As a result, the inductor L61 and the interelectrode capacitance Cp undergo LC resonance, and the charge stored in the capacitor C61 moves to the interelectrode capacitance Cp via the switching element Q61, the diode Di61, and the inductor L61. Thus, the voltage of sustain electrode SU1 through sustain electrode SUn increases from voltage 0 (V) toward voltage Vs.

  At time t5 when the voltage of sustain electrode SU1 through sustain electrode SUn rises to near voltage Vs, switching element Q63 of second clamp portion 63 is turned on. Thereby, sustain electrode SU1 through sustain electrode SUn are clamped at voltage Vs.

  At time t6 after sustain electrode SU1 to sustain electrode SUn are clamped to voltage Vs, scanning element Q53 of first clamp part 53 of switching electrode drive circuit 33 and switching element Q58 of separation part 58 are turned off to perform scanning. Electrode SC1 through scan electrode SCn are brought into a high impedance state.

  At time t7, a voltage waveform that changes from a high potential to a low potential is applied to sustain electrode SU1 through sustain electrode SUn. Specifically, the switching element Q61 of the second power recovery unit 61 and the switching element Q63 of the second clamp unit 63 of the sustain electrode drive circuit 34 are turned off, and the switching element Q65 and switching element Q66 of the reference potential setting unit 65 are turned off. Turn on. As a result, the potential of sustain electrode SU1 through sustain electrode SUn is lowered from voltage Vs, which is a high potential, to voltage Ve, which is a low potential.

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when potential of sustain electrode SU1 to sustain electrode SUn decreases, scan electrode SC1 is formed between scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. The potentials of scan electrode SC1 through scan electrode SCn also decrease through interelectrode capacitance Cp.

The voltage drop at this time is the interelectrode capacitance Cp formed between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, scan electrode SC1 through scan electrode SCn, data electrode D1 through data electrode Dm. It is determined by the partial pressure with the interelectrode capacitance Cpd formed therebetween. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
(Vs−Ve) × Cp / (Cp + Cpd)
(Period T13)
In the period T13, at time t8, a voltage is applied to the resistor R56 of the second ramp waveform voltage generator 56, and a constant current flows toward the capacitor C56. As a result, the switching element Q56 is turned on, the drain voltage of the switching element Q56 decreases in a ramp shape from the voltage 0 (V) toward the negative voltage Vi3, and the output voltage of the scan electrode driving circuit 33 is also a negative voltage. It starts to descend in a ramp shape toward Vi3. At this time, the voltage applied to the resistor R56 is adjusted so that the gradient of the ramp waveform voltage becomes a desired value (for example, −1.5 V / μsec).

  In this way, a downward ramp waveform voltage that decreases toward the negative voltage Vi3 is generated from the voltage that has dropped from the voltage Vi2 by the voltage according to the above equation. This voltage drop continues until a voltage is applied to the resistor R56 or until the voltage at the node P59 reaches the voltage Vi3.

  In period T13, the downward ramp waveform voltage thus generated is applied to scan electrode SC1 through scan electrode SCn.

  At time t9 after the voltage of scan electrode SC1 through scan electrode SCn reaches voltage Vi3, switching element Q5L1 through switching element Q5Ln of scan pulse generator 59 is turned off, and switching element Q5H1 through switching element Q5Hn are turned on. Thus, the voltage of scan electrode SC1 through scan electrode SCn rises from voltage Vi3 to a voltage (Vi3 + voltage Vq) obtained by superimposing voltage Vq on negative voltage Vi3.

  Thereafter, the switching element Q57 is turned on to clamp the voltage at the node P59 to the negative voltage Va, and the voltage Vc obtained by superimposing the voltage Vq on the voltage Va is applied to the scan electrode SC1 to the scan electrode SCn. Prepare.

  As described above, in the present embodiment, in the forced initialization period, the period from when the application of the upward ramp waveform voltage to the start of application of the downward ramp waveform voltage after the completion of the application of the upward ramp waveform voltage to scan electrode SC1 is described above. A period T12 is provided.

  As a result, the start voltage when the downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn can be reduced from voltage Vs by (Vs−Ve) × Cp / (Cp + Cpd). That is, the operation of the second ramp waveform voltage generator 56 can be started from a voltage that has decreased from the voltage Vs by (Vs−Ve) × Cp / (Cp + Cpd).

  Therefore, when compared with the prior art in which the voltage Vs is used as the start voltage of the falling ramp waveform voltage without providing the above-described period T12, if the slope of the falling ramp waveform voltage is the same, the descending to the negative voltage Vi3. The time for operating the second ramp waveform voltage generator 56 to generate the ramp waveform voltage can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the starting voltage of the downward ramp waveform voltage is The voltage drops from the voltage Vs by that amount.
(Vs−Ve) × Cp / (Cp + Cpd)
= (200-120) × 3 / (3 + 1)
= 80 × 3/4
= 60
Therefore, in this case, the voltage 140 (V) in which the voltage is reduced by 60 (V) from the voltage Vs is the start voltage of the downward ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a ramp waveform voltage that drops from the voltage 140 (V) to the voltage Vi3 (for example, voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage Vs (for example, 200 (V)) to voltage Vi3 (for example, voltage -200 (V)).

  As described above, in the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are placed in a high impedance state immediately before applying a downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn, and sustain electrode The voltage of SU1 to sustain electrode SUn is reduced. As a result, the start voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn can be reduced. If the slope of the downward ramp waveform voltage is the same when compared with the prior art, a negative voltage is applied. The time for operating the second ramp waveform voltage generator 56 in order to generate the ramp waveform voltage falling to Vi3 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

  Thereby, for example, the second ramp waveform voltage generator 56 can be configured using a semiconductor element having a relatively low rated value.

(Embodiment 2)
In the first embodiment, the voltage is applied to sustain electrode SU1 through sustain electrode SUn and scan electrode SC1 through scan electrode SCn during the initializing period (forced initializing period) of the forced initializing subfield (in this embodiment, subfield SF1). The operation of the drive circuit when generating the drive voltage waveform to be performed has been described. In the present embodiment, when a drive voltage waveform to be applied to the data electrodes D1 to Dm is generated in the initialization period (forced initialization period) of the forced initialization subfield (subfield SF1 in the present embodiment). The operation of the drive circuit will be described.

  The configuration of the plasma display device in the present embodiment is the same as that of the plasma display device 30 shown in the first embodiment, and the configuration of one field in the present embodiment is also one field shown in the first embodiment. The configuration is the same. Therefore, the description thereof is omitted in the present embodiment.

  FIG. 7 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of panel 10 used in the plasma display device in accordance with the second exemplary embodiment of the present invention.

  FIG. 8 is a diagram schematically showing another example of the drive voltage waveform applied to each electrode of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

  In the present embodiment, as shown in FIGS. 7 and 8, in the first half of the initialization period of the subfield SF1 in which the forced initialization operation is performed, the voltage Vd is applied to the data electrodes D1 to Dm and maintained. Voltage 0 (V) is applied to electrode SU1 through sustain electrode SUn. Then, voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn after voltage 0 (V) is applied, and an upward ramp waveform voltage that gradually rises from voltage Vi1 to voltage Vi2 is applied.

  Then, as shown in FIG. 7, when the rising ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vi2, the voltage of scan electrode SC1 through scan electrode SCn is lowered to voltage Vs lower than voltage Vi2. . At this time, the voltage applied to sustain electrode SU1 through sustain electrode SUn is once increased from voltage 0 (V) to voltage Vs.

  In the latter half of the initialization period of subfield SF1, positive voltage Ve lower than voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Therefore, the potentials of sustain electrode SU1 through sustain electrode SUn are reduced from high potential voltage Vs to low potential Ve.

  In the second half of the initialization period of subfield SF1, voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Therefore, the potentials of the data electrodes D1 to Dm are decreased from the high voltage Vd to the low voltage 0 (V).

  Then, a downward ramp waveform voltage that gently falls from voltage Vq lower than voltage Vs to negative voltage Vi3 is applied to scan electrode SC1 through scan electrode SCn.

  As shown in FIG. 8, when the rising ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vi2, and the voltage applied to scan electrode SC1 through scan electrode SCn is lowered from voltage Vi2 to voltage Vs. The voltage applied to sustain electrode SU1 through sustain electrode SUn may be maintained at voltage 0 (V).

  In the second half of the initializing period of subfield SF1, positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Therefore, the potentials of the data electrodes D1 to Dm are decreased from the high voltage Vd to the low voltage 0 (V).

  Then, a downward ramp waveform voltage that gently falls from voltage Vq lower than voltage Vs to negative voltage Vi3 is applied to scan electrode SC1 through scan electrode SCn.

  Thus, in the present embodiment, in the latter half of the initialization period of subfield SF1, the potentials of data electrode D1 to data electrode Dm are set immediately before the downward ramp waveform voltage is applied to scan electrode SC1 to scan electrode SCn. The voltage Vd, which is a high potential, is reduced to a voltage 0 (V), which is a low potential.

  At this time, the potential of sustain electrode SU1 through sustain electrode SUn may be lowered from high potential voltage Vs to low potential Ve as shown in FIG. Alternatively, as shown in FIG. 8, a configuration may be used in which a voltage that varies from voltage 0 (V) to voltage Vs is applied instead of lowering the potential of sustain electrode SU <b> 1 through sustain electrode SUn. In any case, the start voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn can be lowered from voltage Vs to a voltage lower than voltage Vs.

  FIG. 9 is a timing chart for explaining the operation of the drive circuit during the initialization period of plasma display device 30 according to the second embodiment of the present invention.

  FIG. 9 shows drive voltage waveforms applied to scan electrode SC1 through scan electrode SCn, drive voltage waveforms applied to sustain electrode SU1 through sustain electrode SUn, and drive voltage waveforms applied to data electrode D1 through data electrode Dm.

  FIG. 9 is a timing chart when the drive voltage waveform shown in FIG. 7 is generated.

  In FIG. 9, the voltage waveform generated when the forced initialization operation is performed is divided into three periods indicated by a period T11, a period T12, and a period T13, and each period will be described. It is assumed that drive circuit 33 and sustain electrode drive circuit 34 operate in the same manner as described with reference to FIG. Therefore, in the present embodiment, description of operations of scan electrode drive circuit 33 and sustain electrode drive circuit 34 is omitted, and operation of data electrode drive circuit 32 is described.

(Period T11)
At time t1, the switching element Q71 of the data electrode driving circuit 32 is turned on, the switching element Q72 is turned off, and the voltage Vd is applied to the data electrodes D1 to Dm.

(Period T12)
Subsequent to the period T11, the switching element Q71 of the data electrode driving circuit 32 is turned on, the switching element Q72 is turned off, and the voltage Vd is applied to the data electrodes D1 to Dm.

  Next, at time t7, a voltage waveform that changes from a high potential to a low potential is applied to the data electrodes D1 to Dm. Specifically, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. Therefore, at time t7, the potentials of the data electrodes D1 to Dm drop from the high potential voltage Vd to the low potential voltage 0 (V).

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when the potential of data electrode D1 to data electrode Dm decreases, scan electrode SC1 is formed between scan electrode SCn and data electrode D1 to data electrode Dm. The potentials of scan electrode SC1 through scan electrode SCn also decrease through interelectrode capacitance Cpd.

  Further, as described in the first embodiment, since the potential of sustain electrode SU1 through sustain electrode SUn drops from voltage Vs to voltage Ve at time t7, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. The potentials of scan electrode SC1 through scan electrode SCn decrease via interelectrode capacitance Cp formed between the two.

The voltage drop at this time is determined by the partial pressure of the interelectrode capacitance Cp and the interelectrode capacitance Cpd. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
(Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
The potential of sustain electrode SU1 through sustain electrode SUn is not lowered from the high potential to the low potential, and the voltage drop at this time when only the potential of data electrode D1 through data electrode Dm is lowered from the high potential to the low potential is as follows: It becomes like the formula.
Vd × Cpd / (Cp + Cpd)
The period T13 is the same as the operation described with reference to FIG.

  As a result, the start voltage when the downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn is reduced from voltage Vs by (Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd). be able to. That is, the operation of the second ramp waveform voltage generator 56 can be started from a voltage that has decreased from the voltage Vs by (Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd).

  Therefore, when compared with the prior art in which the voltage Vs is used as the starting voltage of the falling ramp waveform voltage without providing the above-described period T12, if the slope of the falling ramp waveform voltage is the same, the descending to the negative voltage Vi3. The time for operating the second ramp waveform voltage generator 56 to generate the ramp waveform voltage can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), the voltage Vd = 60 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the downward slope The starting voltage of the waveform voltage decreases from the voltage Vs by the following amount.
(Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
= (200-120) * 3 / (3 + 1) + 60 * 1 / (3 + 1)
= 80 × 3/4 + 60 × 1/4
= 75
Therefore, in this case, the voltage 125 (V) in which the voltage is reduced by 75 (V) from the voltage Vs is the start voltage of the downward ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a down ramp waveform voltage that drops from the voltage 125 (V) to the voltage Vi3 (for example, voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage Vs (for example, voltage 200 (V)) to voltage Vi3 (for example, voltage −200 (V)). .

  Although the description of the timing chart when generating the drive voltage waveform shown in FIG. 8 is omitted, when the drive voltage waveform shown in FIG. 8 is generated, in the period T12, the sustain electrodes SU1 to SUn The applied voltage may be maintained at voltage 0 (V).

  As described above, in the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are placed in a high impedance state immediately before applying a downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn, and sustain electrode The voltages of SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm are reduced.

  Alternatively, immediately before the downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn, scan electrode SC1 through scan electrode SCn are brought into a high impedance state and the voltage of data electrode D1 through data electrode Dm is reduced.

  As a result, the start voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn can be reduced. If the slope of the downward ramp waveform voltage is the same when compared with the prior art, a negative voltage is applied. The time for operating the second ramp waveform voltage generator 56 in order to generate the ramp waveform voltage falling to Vi3 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

  Thereby, for example, the second ramp waveform voltage generator 56 can be configured using a semiconductor element having a relatively low rated value.

(Embodiment 3)
In the present embodiment, scan electrode SC <b> 1 to scan electrode are included in the sustain period, the erase period, and the initializing period (selective initializing period) of the selective initializing subfield (in this embodiment, the subfield after subfield SF <b> 2). An operation of the drive circuit when generating a drive voltage waveform to be applied to SCn and sustain electrode SU1 to sustain electrode SUn will be described.

  The configuration of the plasma display device in the present embodiment is the same as that of the plasma display device 30 shown in the first embodiment, and the configuration of one field in the present embodiment is also one field shown in the first embodiment. The configuration is the same. Therefore, the description thereof is omitted in the present embodiment.

  FIG. 10 is a timing chart for explaining the operation of the drive circuit during the erasing period and the initialization period of the plasma display device according to the third embodiment of the present invention.

  FIG. 10 shows drive voltage waveforms applied to scan electrode SC1 through scan electrode SCn, and drive voltage waveforms applied to sustain electrode SU1 through sustain electrode SUn. In this drawing, the voltage waveform generated at the end of the sustain period is divided into two periods indicated by periods T21 and T22, and the voltage waveform generated during the erase period is divided into two periods indicated by periods T23 and T24. Then, the voltage waveform generated when performing the selective initialization operation in the selective initialization period is divided into two periods indicated by a period T25 and a period T26, and each period will be described.

  In the sustain period, switching element Q55, switching element Q56, switching element Q57, switching element Q65, and switching element Q66 are kept off, and switching element Q58 is kept on. Further, switching element Q5H1 to switching element Q5Hn are kept off, switching element Q5L1 to switching element Q5Ln are kept on, and voltage of node P59 is applied to scan electrode SC1 to scan electrode SCn.

(Period T21)
In period T21, at time t10, switching element Q62 and switching element Q64 are on, and switching element Q61 and switching element Q63 are off. Therefore, the voltage of sustain electrode SU1 through sustain electrode SUn is clamped at voltage 0 (V).

  At time t10, switching element Q51 is turned on, and switching element Q52, switching element Q53, and switching element Q54 are turned off. As a result, the inductor L51 and the interelectrode capacitance Cp resonate with each other, and the charge stored in the capacitor C51 passes through the switching element Q51, the diode Di51, the inductor L51, the switching element Q58, and the switching elements Q5L1 to Q5Ln. It moves to the interelectrode capacitance Cp. Thus, the voltage of scan electrode SC1 through scan electrode SCn starts to rise from voltage 0 (V) toward voltage Vs.

  At time t11 when the voltage of scan electrode SC1 through scan electrode SCn rises to near voltage Vs, switching element Q53 of first clamp portion 53 is turned on. Thereby, scan electrode SC1 to scan electrode SCn are clamped to voltage Vs.

  At time t12 after the sustain discharge is generated in the discharge cell, the switching element Q51 of the first power recovery unit 51 of the sustain pulse generation unit 50 and the switching element Q53 of the first clamp unit 53 are turned off, and the first The switching element Q52 of the power recovery unit 51 is turned on. As a result, the inductor L51 and the interelectrode capacitance Cp undergo LC resonance, and the charge stored in the interelectrode capacitance Cp passes through the switching element Q5L1 to the switching element Q5Ln, the switching element Q58, the inductor L51, the diode Di52, and the switching element Q52. To be recovered by the capacitor C51. Thus, the voltage of scan electrode SC1 through scan electrode SCn starts to drop from voltage Vs toward voltage 0 (V).

(Period T22)
At time t13 when the voltage of scan electrode SC1 through scan electrode SCn drops to near voltage 0 (V), switching element Q54 of first clamp portion 53 is turned on. Thereby, scan electrode SC1 to scan electrode SCn are clamped at voltage 0 (V).

  At time t13, the switching element Q61 of the second power recovery unit 61 is turned on, and the switching element Q62 of the second power recovery unit 61 and the switching element Q64 of the second clamp unit 63 are turned off. As a result, the inductor L61 and the interelectrode capacitance Cp undergo LC resonance, and the charge stored in the capacitor C61 moves to the interelectrode capacitance Cp via the switching element Q61, the diode Di61, and the inductor L61. Thus, the voltage of sustain electrode SU1 through sustain electrode SUn begins to rise from voltage 0 (V) toward voltage Vs.

  At time t14 when the voltage of sustain electrode SU1 through sustain electrode SUn rises to the vicinity of voltage Vs, switching element Q63 of second clamp portion 63 is turned on. Thereby, sustain electrode SU1 through sustain electrode SUn are clamped at voltage Vs.

  At time t15 after the sustain discharge is generated in the discharge cell, the switching element Q61 of the second power recovery unit 61 and the switching element Q63 of the second clamp unit 63 of the sustain pulse generation unit 60 are turned off, and the reference potential is set. Switching element Q65 and switching element Q66 of unit 65 are turned on. Thus, sustain electrode SU1 through sustain electrode SUn are clamped at voltage Ve lower than voltage Vs.

(Period T23)
Next, at time t <b> 16, switching element Q <b> 52 of first power recovery unit 51 of sustain pulse generation unit 50 of scan electrode drive circuit 33, switching element Q <b> 54 of first clamp unit 53, and switching element Q <b> 58 of separation unit 58. Turn off. Thereby, scan electrode SC1 to scan electrode SCn are brought into a high impedance state.

  Then, a voltage waveform that changes from a high potential to a low potential is applied to sustain electrode SU1 through sustain electrode SUn. Specifically, switching element Q65 and switching element Q66 of reference potential setting unit 65 of sustain electrode drive circuit 34 are turned off, and switching element Q64 of second clamp unit 63 of sustain pulse generating unit 60 is turned on. As a result, the potentials of sustain electrode SU1 through sustain electrode SUn drop from voltage Ve, which is a high potential, to voltage 0 (V), which is a low potential.

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when potential of sustain electrode SU1 to sustain electrode SUn decreases, scan electrode SC1 is formed between scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. The potentials of scan electrode SC1 through scan electrode SCn also decrease through interelectrode capacitance Cp.

The voltage drop at this time is the interelectrode capacitance Cp formed between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, scan electrode SC1 through scan electrode SCn, data electrode D1 through data electrode Dm. It is determined by the partial pressure with the interelectrode capacitance Cpd formed therebetween. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
Ve × Cp / (Cp + Cpd)
At time t17, a voltage is applied to the resistor R56 of the second ramp waveform voltage generator 56, and a constant current is caused to flow toward the capacitor C56. As a result, the switching element Q56 is turned on, the drain voltage of the switching element Q56 decreases in a ramp shape from the voltage 0 (V) toward the negative voltage Vi3, and the output voltage of the scan electrode driving circuit 33 is also a negative voltage. It starts to descend in a ramp shape toward Vi3. At this time, the voltage applied to the resistor R56 is adjusted so that the gradient of the ramp waveform voltage becomes a desired value (for example, −1.5 V / μsec).

  In this manner, a downward ramp waveform voltage that decreases toward the negative voltage Vi3 is generated from the voltage that has dropped from the voltage 0 (V) by the voltage according to the above equation. This voltage drop continues until a voltage is applied to the resistor R56 or until the voltage at the node P59 reaches the voltage Vi3.

  In period T23, the downward ramp waveform voltage generated in this way is applied to scan electrode SC1 through scan electrode SCn.

  At time t18 after the voltage of scan electrode SC1 through scan electrode SCn reaches voltage Vi3, switching element Q5L1 through switching element Q5Ln of scan pulse generator 59 is turned off, and switching element Q5H1 through switching element Q5Hn are turned on. Thus, the voltage of scan electrode SC1 through scan electrode SCn rises from voltage Vi3 to a voltage (Vi3 + voltage Vq) obtained by superimposing voltage Vq on negative voltage Vi3.

  At time t19, switching elements Q5H1 to Q5Hn of scan pulse generating unit 59 are turned off, and switching elements Q5L1 to Q5Ln are turned on. Further, the switching element Q56 of the second ramp waveform voltage generator 56 is turned off, and the switching element Q54 of the first clamp part 53 of the sustain pulse generator 50 and the switching element Q58 of the separator 58 are turned on. Thereby, scan electrode SC1 to scan electrode SCn are clamped at voltage 0 (V).

  As described above, in the present embodiment, in the erasing period, the start voltage when applying the downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn is set to the voltage from 0 (V) to Ve × Cp / (Cp + Cpd). Can only be lowered. That is, the operation of the second ramp waveform voltage generator 56 can be started from a voltage that has decreased from the voltage 0 (V) by Ve × Cp / (Cp + Cpd).

  Therefore, when compared with the prior art in which the voltage 0 (V) is the starting voltage of the descending ramp waveform voltage, if the slope of the descending ramp waveform voltage is the same, the descending ramp waveform voltage that falls to the negative voltage Vi3 is generated. Therefore, the time for operating the second ramp waveform voltage generator 56 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the starting voltage of the downward ramp waveform voltage is The voltage drops from the voltage Vs by that amount.
Ve × Cp / (Cp + Cpd)
= 120 × 3 / (3 + 1)
= 120 × 3/4
= 90
Therefore, in this case, the voltage −90 (V) in which the voltage is reduced by 90 (V) from the voltage 0 (V) is the start voltage of the descending ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a ramp waveform voltage that drops from a voltage −90 (V) to a voltage Vi3 (for example, a voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage 0 (V) to voltage Vi3 (for example, voltage −200 (V)).

(Period T24)
At time t20, switching element Q54 of first clamp unit 53 of sustain pulse generating unit 50 is turned off, and the voltage at node P59 is set to a high impedance state.

  Next, a voltage is applied to the resistor R55 of the first ramp waveform voltage generator 55, and a constant current is passed toward the capacitor C55. Thereby, the switching element Q55 is turned on, the source voltage of the switching element Q55 increases from the voltage 0 (V) in a ramp shape, and the output voltage of the scan electrode drive circuit 33 starts to increase from the voltage Vq in a ramp shape. At this time, the voltage applied to the resistor R55 is adjusted so that the gradient of the ramp waveform voltage becomes a desired value (for example, 10 V / μsec).

  Thus, an upward ramp waveform voltage rising from the voltage 0 (V) toward the voltage Vr is generated. This voltage increase continues during the period when the voltage is applied to the resistor R55 or until the voltage at the node P59 reaches the voltage Vr.

  In the period T24, an upward ramp waveform voltage that gradually increases from the voltage 0 (V) toward the voltage Vr exceeding the discharge start voltage is generated and applied to the scan electrodes SC1 to SCn.

  At time t21 after the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vr, switching element Q55 of first ramp waveform voltage generator 55 is turned off.

  Then, switching element Q52 of first power recovery unit 51 of sustain pulse generating unit 50 is turned on. As a result, the inductor L51 and the interelectrode capacitance Cp undergo LC resonance, and the charge stored in the interelectrode capacitance Cp passes through the switching element Q5L1 to the switching element Q5Ln, the switching element Q58, the inductor L51, the diode Di52, and the switching element Q52. To be recovered by the capacitor C51. Thus, the voltage of scan electrode SC1 through scan electrode SCn starts to drop from voltage Vr toward voltage 0 (V).

  At time t22 when the voltage of scan electrode SC1 through scan electrode SCn drops to near voltage 0 (V), switching element Q54 of first clamp portion 53 is turned on. Thereby, scan electrode SC1 to scan electrode SCn are clamped at voltage 0 (V).

(Period T25)
At time t23, the switching element Q64 of the second clamp unit 63 of the sustain pulse generator 60 of the sustain electrode drive circuit 34 is turned off, and the switching element Q61 of the second power recovery unit 61 is turned on. As a result, the inductor L61 and the interelectrode capacitance Cp undergo LC resonance, and the charge stored in the capacitor C61 moves to the interelectrode capacitance Cp via the switching element Q61, the diode Di61, and the inductor L61. Thus, the voltage of sustain electrode SU1 through sustain electrode SUn begins to rise from voltage 0 (V) toward voltage Vs.

  At time t24 when the voltage of sustain electrode SU1 through sustain electrode SUn rises to near voltage Vs, switching element Q63 of second clamp unit 63 of sustain pulse generating unit 60 is turned on. Thereby, sustain electrode SU1 through sustain electrode SUn are clamped at voltage Vs.

  Next, at time t25, the switching element Q52 of the first power recovery unit 51 of the sustain pulse generating unit 50 of the scan electrode driving circuit 33, the switching element Q54 of the first clamp unit 53, and the switching element Q58 of the separation unit 58. Turn off. Thereby, scan electrode SC1 to scan electrode SCn are brought into a high impedance state.

  Then, a voltage waveform that changes from a high potential to a low potential is applied to sustain electrode SU1 through sustain electrode SUn. Specifically, the switching element Q61 of the second power recovery unit 61 and the switching element Q63 of the second clamp unit 63 of the sustain pulse generation unit 60 of the sustain electrode drive circuit 34 are turned off, and the reference potential setting unit 65 is switched. Element Q65 and switching element Q66 are turned on. As a result, the potential of sustain electrode SU1 through sustain electrode SUn is lowered from voltage Vs, which is a high potential, to voltage Ve, which is a low potential.

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when potential of sustain electrode SU1 to sustain electrode SUn decreases, scan electrode SC1 is formed between scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. The potentials of scan electrode SC1 through scan electrode SCn also decrease through interelectrode capacitance Cp.

The voltage drop at this time is the interelectrode capacitance Cp formed between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, scan electrode SC1 through scan electrode SCn, data electrode D1 through data electrode Dm. It is determined by the partial pressure with the interelectrode capacitance Cpd formed therebetween. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
(Vs−Ve) × Cp / (Cp + Cpd)
(Period T26)
At time t26, a voltage is applied to the resistor R56 of the second ramp waveform voltage generator 56, and a constant current is caused to flow toward the capacitor C56. As a result, the switching element Q56 is turned on, the drain voltage of the switching element Q56 decreases in a ramp shape from the voltage 0 (V) toward the negative voltage Vi3, and the output voltage of the scan electrode driving circuit 33 is also a negative voltage. It starts to descend in a ramp shape toward Vi3. At this time, the voltage applied to the resistor R56 is adjusted so that the gradient of the ramp waveform voltage becomes a desired value (for example, −1.5 V / μsec).

  In this manner, a downward ramp waveform voltage that decreases toward the negative voltage Vi3 is generated from the voltage that has dropped from the voltage 0 (V) by the voltage according to the above equation. This voltage drop continues until a voltage is applied to the resistor R56 or until the voltage at the node P59 reaches the voltage Vi3.

  In period T26, the downward ramp waveform voltage generated in this way is applied to scan electrode SC1 through scan electrode SCn.

  At time t27 after the voltage of scan electrode SC1 through scan electrode SCn reaches voltage Vi3, switching element Q5L1 through switching element Q5Ln of scan pulse generator 59 is turned off, and switching element Q5H1 through switching element Q5Hn are turned on. Thus, the voltage of scan electrode SC1 through scan electrode SCn rises from voltage Vi3 to a voltage (Vi3 + voltage Vq) obtained by superimposing voltage Vq on negative voltage Vi3.

  As described above, in the present embodiment, in the selective initialization period, the start voltage when applying the downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn is changed from voltage 0 (V) to (Vs−Ve) × Cp. / (Cp + Cpd). That is, the operation of the second ramp waveform voltage generator 56 can be started from a voltage that has decreased from the voltage 0 (V) by (Vs−Ve) × Cp / (Cp + Cpd).

  Therefore, when compared with the prior art in which the voltage 0 (V) is the starting voltage of the descending ramp waveform voltage, if the slope of the descending ramp waveform voltage is the same, the descending ramp waveform voltage that falls to the negative voltage Vi3 is generated. Therefore, the time for operating the second ramp waveform voltage generator 56 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the starting voltage of the downward ramp waveform voltage is The voltage drops from the voltage Vs by that amount.
(Vs−Ve) × Cp / (Cp + Cpd)
= (200-120) × 3 / (3 + 1)
= 80 × 3/4
= 60
Therefore, in this case, the voltage −60 (V), in which the voltage is decreased by 60 (V) from the voltage 0 (V), becomes the start voltage of the downward ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a ramp waveform voltage that drops from voltage −60 (V) to voltage Vi3 (for example, voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage 0 (V) to voltage Vi3 (for example, voltage −200 (V)).

  As described above, in the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are placed in a high impedance state immediately before applying a downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn, and sustain electrode The voltage of SU1 to sustain electrode SUn is reduced. As a result, the start voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn can be reduced. If the slope of the downward ramp waveform voltage is the same when compared with the prior art, a negative voltage is applied. The time for operating the second ramp waveform voltage generator 56 in order to generate the ramp waveform voltage falling to Vi3 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

  Thereby, for example, the second ramp waveform voltage generator 56 can be configured using a semiconductor element having a relatively low rated value.

(Embodiment 4)
In the third embodiment, scan electrode SC1 to scan electrode in the sustain period, the erase period, and the initializing period (selective initializing period) of the selective initializing subfield (in this embodiment, the subfield after subfield SF2). The operation of the drive circuit when generating the drive voltage waveform applied to SCn and sustain electrode SU1 to sustain electrode SUn has been described. In the present embodiment, the data electrode D1 to the data electrode in the sustain period, the erase period, and the initializing period (selective initializing period) of the selective initializing subfield (subfield SF2 and subsequent subfields in this exemplary embodiment). The operation of the drive circuit when generating the drive voltage waveform applied to Dm will be described.

  The configuration of the plasma display device in the present embodiment is the same as that of the plasma display device 30 shown in the first embodiment, and the configuration of one field in the present embodiment is also one field shown in the first embodiment. The configuration is the same. Therefore, the description thereof is omitted in the present embodiment.

  FIG. 11 is a timing chart for explaining the operation of the drive circuit during the initialization period of plasma display device 30 according to the fourth embodiment of the present invention.

  FIG. 11 shows drive voltage waveforms applied to scan electrode SC1 through scan electrode SCn, drive voltage waveforms applied to sustain electrode SU1 through sustain electrode SUn, and drive voltage waveforms applied to data electrode D1 through data electrode Dm.

  In FIG. 11, the voltage waveform generated at the end of the sustain period is divided into two periods indicated by periods T21 and T22, and the voltage waveform generated during the erase period is divided into two periods indicated by periods T23 and T24. The voltage waveform generated when performing the selective initialization operation in the selective initialization period is divided into two periods indicated by a period T25 and a period T26, and each period will be described. In each period, the scan electrode drive circuit 33 and sustain electrode drive circuit 34 are assumed to perform the same operation as described in FIG. Therefore, in the present embodiment, description of operations of scan electrode drive circuit 33 and sustain electrode drive circuit 34 is omitted, and operation of data electrode drive circuit 32 is described.

(Period T21)
In the period T21, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

(Period T22)
Subsequent to the period T21, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

  Immediately before time t15, the switching element Q71 of the data electrode driving circuit 32 is turned on, the switching element Q72 is turned off, and the voltage Vd is applied to the data electrodes D1 to Dm.

  Next, at time t16, a voltage waveform that changes from a high potential to a low potential is applied to the data electrodes D1 to Dm. Specifically, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. Therefore, at time t16, the potentials of the data electrodes D1 to Dm drop from the high potential voltage Vd to the low potential voltage 0 (V).

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when the potential of data electrode D1 to data electrode Dm decreases, scan electrode SC1 is formed between scan electrode SCn and data electrode D1 to data electrode Dm. The potentials of scan electrode SC1 through scan electrode SCn are lowered through interelectrode capacitance Cpd.

  Further, as described in the third embodiment, since the potential of sustain electrode SU1 through sustain electrode SUn drops from voltage Ve to voltage 0 (V) at time t16, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through The potentials of scan electrode SC1 through scan electrode SCn are lowered via interelectrode capacitance Cp formed between sustain electrodes SUn.

The voltage drop at this time is determined by the partial pressure of the interelectrode capacitance Cp and the interelectrode capacitance Cpd. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
Ve × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
The potential of sustain electrode SU1 through sustain electrode SUn is not lowered from the high potential to the low potential, and the voltage drop at this time when only the potential of data electrode D1 through data electrode Dm is lowered from the high potential to the low potential is as follows: It becomes like the formula.
Vd × Cpd / (Cp + Cpd)
As a result, the start voltage when applying the downward ramp waveform voltage to scan electrode SC1 through scan electrode SCn is reduced from voltage 0 (V) by Ve × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd). Can do. That is, the operation of the second ramp waveform voltage generator 56 can be started from a voltage that has decreased from the voltage 0 (V) by Ve × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd).

  Therefore, when compared with the prior art in which the voltage 0 (V) is the starting voltage of the descending ramp waveform voltage, if the slope of the descending ramp waveform voltage is the same, the descending ramp waveform voltage that falls to the negative voltage Vi3 is generated. Therefore, the time for operating the second ramp waveform voltage generator 56 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), the voltage Vd = 60 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the downward slope The starting voltage of the waveform voltage decreases from the voltage Vs by the following amount.
Ve × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
= 120 × 3 / (3 + 1) + 60 × 1 / (3 + 1)
= 120 x 3/4 + 60 x 1/4
= 90 + 15
= 105
Therefore, in this case, the voltage −105 (V) in which the voltage is decreased by 105 (V) from the voltage 0 (V) is the start voltage of the downward ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a ramp waveform voltage that drops from the voltage −105 (V) to the voltage Vi3 (for example, the voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage 0 (V) to voltage Vi3 (for example, voltage −200 (V)).

(Period T23)
In the period T23, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

(Period T24)
In the period T24, following the period T23, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

(Period T25)
Subsequent to the period T24, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

  Immediately after time t24, the switching element Q71 of the data electrode driving circuit 32 is turned on, the switching element Q72 is turned off, and the voltage Vd is applied to the data electrodes D1 to Dm.

  Next, at time t25, a voltage waveform that changes from a high potential to a low potential is applied to the data electrodes D1 to Dm. Specifically, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. Therefore, at time t25, the potentials of the data electrodes D1 to Dm drop from the high voltage Vd to the low voltage 0 (V).

  At this time, since scan electrode SC1 to scan electrode SCn are in a high impedance state, when the potential of data electrode D1 to data electrode Dm decreases, scan electrode SC1 is formed between scan electrode SCn and data electrode D1 to data electrode Dm. The potentials of scan electrode SC1 through scan electrode SCn are lowered through interelectrode capacitance Cpd.

  Further, as described in the third embodiment, since the potential of sustain electrode SU1 through sustain electrode SUn drops from voltage Vs to voltage Ve at time t25, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. The potentials of scan electrode SC1 through scan electrode SCn decrease via interelectrode capacitance Cp formed between the two.

The voltage drop at this time is determined by the partial pressure of the interelectrode capacitance Cp and the interelectrode capacitance Cpd. The potentials of scan electrode SC1 through scan electrode SCn ideally decrease by the following equation without substantially consuming power.
(Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
As a result, the start voltage when applying the downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn is the voltage from 0 (V) to (Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd). Can only be lowered. That is, the operation of the second ramp waveform voltage generator 56 is started from a voltage that has decreased from the voltage 0 (V) by (Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd). it can.

  Therefore, when compared with the prior art in which the voltage 0 (V) is the starting voltage of the descending ramp waveform voltage, if the slope of the descending ramp waveform voltage is the same, the descending ramp waveform voltage that falls to the negative voltage Vi3 is generated. Therefore, the time for operating the second ramp waveform voltage generator 56 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

For example, if the voltage Vs = 200 (V), the voltage Ve = 120 (V), the voltage Vd = 60 (V), and the interelectrode capacitance Cp and the interelectrode capacitance Cpd are in a ratio of 3: 1, the downward slope The starting voltage of the waveform voltage decreases from the voltage Vs by the following amount.
(Vs−Ve) × Cp / (Cp + Cpd) + Vd × Cpd / (Cp + Cpd)
= (200-120) * 3 / (3 + 1) + 60 * 1 / (3 + 1)
= 80 × 3/4 + 60 × 1/4
= 60 + 15
= 75
Therefore, in this case, a voltage −75 (V) in which the voltage is reduced by 75 (V) from the voltage 0 (V) becomes the start voltage of the downward ramp waveform voltage. Therefore, the second ramp waveform voltage generator 56 only needs to generate a down ramp waveform voltage that drops from a voltage −75 (V) to a voltage Vi3 (for example, a voltage −200 (V)). Therefore, power consumption can be reduced as compared with the case of generating a downward ramp waveform voltage that drops from voltage 0 (V) to voltage Vi3 (for example, voltage −200 (V)).

(Period T26)
In the period T26, the switching element Q71 of the data electrode driving circuit 32 is turned off, the switching element Q72 is turned on, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.

  As described above, in the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are placed in a high impedance state immediately before applying a downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn, and sustain electrode The voltages of SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm are reduced.

  Alternatively, immediately before the downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn, scan electrode SC1 through scan electrode SCn are brought into a high impedance state and the voltage of data electrode D1 through data electrode Dm is reduced.

  As a result, the start voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn can be reduced. If the slope of the downward ramp waveform voltage is the same when compared with the prior art, a negative voltage is applied. The time for operating the second ramp waveform voltage generator 56 in order to generate the ramp waveform voltage falling to Vi3 can be shortened. Thereby, the power loss in switching element Q56 can be reduced, and the power consumption of second ramp waveform voltage generator 56 can be reduced.

  Thereby, for example, the second ramp waveform voltage generator 56 can be configured using a semiconductor element having a relatively low rated value.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are set to a high impedance state immediately before applying a downward ramp waveform voltage to scan electrode SC1 to scan electrode SCn, and sustain electrode SU1 to sustain electrode is set. By applying a voltage waveform that changes from a high potential to a low potential to SUn, scan electrodes SC1 to SC1 are scanned via interelectrode capacitance Cp generated between scan electrode SC1 to scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. The potential of the electrode SCn is lowered. The potential change of sustain electrode SU1 through sustain electrode SUn is set so that no discharge occurs in the discharge cell when the potential of scan electrode SC1 through scan electrode SCn decreases.

  Further, in the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are set to a high impedance state immediately before the falling ramp waveform voltage is applied to scan electrode SC1 to scan electrode SCn, and data electrode D1 to data electrode By applying a voltage waveform that changes from a high potential to a low potential to Dm, scan electrodes SC1 to SC1 are scanned via interelectrode capacitance Cpd generated between scan electrode SC1 to scan electrode SCn and data electrode D1 to data electrode Dm. The potential of the electrode SCn is lowered. It is assumed that the potential change of data electrode D1 to data electrode Dm is set so that no discharge occurs in the discharge cell when the potential of scan electrode SC1 to scan electrode SCn decreases.

  In the present invention, the number of subfields constituting one field, subfields to be forced initialization subfields, gradation weights of each subfield, and the like are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

  The drive voltage waveforms shown in FIGS. 3, 6, 7, 8, 9, 10, and 11 are merely examples in the embodiment of the present invention. The driving voltage waveform is not limited.

  The circuit configurations shown in FIGS. 4 and 5 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations.

  Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

  In the embodiment of the present invention, an example in which one field is composed of 10 subfields has been described. However, in the present invention, the number of subfields constituting one field is not limited to the above number. For example, by increasing the number of subfields, the number of gradations that can be displayed on the panel 10 can be further increased. Alternatively, the time required for driving panel 10 can be shortened by reducing the number of subfields.

  In the embodiment of the present invention, an example in which one pixel is constituted by discharge cells of three colors of red, green, and blue has been described. However, a panel in which one pixel is constituted by discharge cells of four colors or more. However, it is possible to apply the configuration shown in the embodiment of the present invention, and the same effect can be obtained.

  The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Further, the number of subfields constituting one field, the gradation weight of each subfield, and the like are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on an image signal or the like. May be configured to switch.

  INDUSTRIAL APPLICABILITY The present invention is useful as a panel driving method and a plasma display device because even a large-screen panel with high definition can suppress the increase in power consumption and generate a stable discharge. It is.

DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display device 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 50 Sustain pulse generation unit 51 First power recovery unit 53 First clamp unit 55 First ramp waveform voltage generation unit 56 Second Ramp waveform voltage generation unit 57 Reference potential setting unit 58 Separation unit 59 Scan pulse generation unit 60 Sustain pulse generation unit 61 Second power recovery unit 63 Second clamp unit 65 Reference potential setting unit Cp, Cpd Interelectrode capacitance Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, 62, Q63, Q64, Q65, Q66, Q5H1~Q5Hn, Q5L1~Q5Ln switching element Di51, Di52, Di61, Di62 diode L51, L61 inductor R55, R56 resistors C51, C55, C56, C61 capacitor E59 power P59 node

In addition, the present invention provides a panel including a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period, a sustain period, and a downward descending toward a predetermined negative voltage. A plasma display device includes a driving circuit that drives a panel by forming one field with a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. In the erasing period, the driving circuit of the plasma display device sets the scan electrode to a high impedance state and applies a voltage waveform that changes from a high potential to a low potential on the sustain electrode before applying the downward ramp waveform voltage to the scan electrode. By applying the voltage, the potential of the scan electrode is lowered, and the lowered potential is used as the start voltage of the downward ramp waveform voltage.

In addition, the present invention provides a panel including a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period, a sustain period, and a downward descending toward a predetermined negative voltage. A plasma display device includes a driving circuit that drives a panel by forming one field with a plurality of subfields having an erasing period in which a ramp waveform voltage is applied to a scan electrode. The driving circuit of the plasma display device sets the scan electrode to a high impedance state and applies a voltage waveform that changes from a high potential to a low potential on the data electrode before applying the downward ramp waveform voltage to the scan electrode during the erasing period. By applying the voltage, the potential of the scan electrode is lowered, and the lowered potential is used as the start voltage of the downward ramp waveform voltage.

In this embodiment, one field is composed of 10 subfields from subfield SF1 to subfield SF10, and each subfield from subfield SF1 to subfield SF10 has (1, 2, 3, (6, 11, 18, 30, 44, 60, 80) An example of setting gradation weights will be described. Then, the subfield SF1 is set as a forced initialization subfield, and the subfields SF2 to SF10 are set as selective initialization subfields.

However, the present invention is not limited to the above-described numerical values for the number of subfields constituting one field, the frequency of occurrence of forced initialization operation, the gradation weight of each subfield, and the like. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

Above the voltage waveform is a selectively selective initializing waveform for causing an initializing discharge in the discharge cells having undergone the address operation between writing period of the immediately preceding subfield. The operation of applying the selective initialization waveform to the scan electrode 12 is the selective initialization operation.

Claims (8)

Initializing a plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and applying a downward ramp waveform voltage falling toward a predetermined negative voltage to the scan electrode A driving method of a plasma display panel, wherein one field is constituted by a plurality of subfields having a period, an address period, and a sustain period.
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode, whereby the potential of the scan electrode Reduce
A driving method of a plasma display panel, wherein the lowered potential is used as a start voltage of the downward ramp waveform voltage. Initializing a plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and applying a downward ramp waveform voltage falling toward a predetermined negative voltage to the scan electrode A driving method of a plasma display panel, wherein one field is constituted by a plurality of subfields having a period, an address period, and a sustain period.
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode, whereby the potential of the scan electrode Reduce
A driving method of a plasma display panel, wherein the lowered potential is used as a start voltage of the downward ramp waveform voltage. A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode has an address period, a sustain period, and a downward ramp waveform voltage that decreases toward a predetermined negative voltage. A driving method of a plasma display panel, wherein a plurality of subfields having an erasing period to be applied to the scan electrodes constitute one field and are driven,
In the erasing period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode, whereby the potential of the scan electrode Reduce
A driving method of a plasma display panel, wherein the lowered potential is used as a start voltage of the downward ramp waveform voltage. A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode has an address period, a sustain period, and a downward ramp waveform voltage that decreases toward a predetermined negative voltage. A driving method of a plasma display panel, wherein a plurality of subfields having an erasing period to be applied to the scan electrodes constitute one field and are driven,
In the erasing period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode, whereby the potential of the scan electrode Reduce
A driving method of a plasma display panel, wherein the lowered potential is used as a start voltage of the downward ramp waveform voltage. A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
The plasma display panel includes a plurality of subfields each having an initializing period in which a downward ramp waveform voltage falling toward a predetermined negative voltage is applied to the scan electrodes, an address period, and a sustain period, A plasma display device comprising a drive circuit for driving
The drive circuit is
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode, whereby the potential of the scan electrode Reduce
The plasma display device according to claim 1, wherein the lowered potential is used as a start voltage of the descending ramp waveform voltage. A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
The plasma display panel includes a plurality of subfields each having an initializing period in which a downward ramp waveform voltage falling toward a predetermined negative voltage is applied to the scan electrodes, an address period, and a sustain period, A plasma display device comprising a drive circuit for driving
The drive circuit is
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode, whereby the potential of the scan electrode Reduce
The plasma display device according to claim 1, wherein the lowered potential is used as a start voltage of the descending ramp waveform voltage. A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
The plasma display panel includes a plurality of subfields each having an address period, a sustain period, and an erasing period in which a falling ramp waveform voltage falling toward a predetermined negative voltage is applied to the scan electrode. A plasma display device comprising a driving circuit for driving,
The drive circuit is
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the sustain electrode, whereby the potential of the scan electrode Reduce
The plasma display device according to claim 1, wherein the lowered potential is used as a start voltage of the descending ramp waveform voltage. A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
The plasma display panel includes a plurality of subfields each having an address period, a sustain period, and an erasing period in which a falling ramp waveform voltage falling toward a predetermined negative voltage is applied to the scan electrode. A plasma display device comprising a driving circuit for driving,
The drive circuit is
In the initialization period,
Before applying the descending ramp waveform voltage to the scan electrode, the scan electrode is put into a high impedance state, and a voltage waveform that changes from a high potential to a low potential is applied to the data electrode, whereby the potential of the scan electrode Reduce
The plasma display device according to claim 1, wherein the lowered potential is used as a start voltage of the descending ramp waveform voltage.

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