JPWO2010013587A1 - Semiconductor integrated circuit - Google Patents

Abstract

The semiconductor integrated circuit in which the logic circuit is duplicated includes a comparison circuit that outputs a comparison result as to whether or not the output values of the logic circuits match each other. The memory circuit included in each logic circuit is a signal that alternately repeats the first cycle and the second cycle, and the start of each first cycle coincides with the end of the second cycle. Supply a clock signal. At least one of these clock signals has a length different from the first period and the second period, and at least one of the clock signals has a signal pattern different from the other clock signals.

Description

  The present invention relates to a semiconductor integrated circuit having high reliability.

  In a system that is required to operate without error for a long time, it is important to improve the reliability of a semiconductor integrated circuit used in the system. For example, a highly reliable semiconductor integrated circuit is required for a device in a place where repair is impossible or difficult, such as a space device, or a device having a large impact on human life or society, such as a medical device or a nuclear power controller.

  As a method for improving the reliability of a semiconductor integrated circuit, two logic circuits having the same function are provided and operated in parallel, and the operation of each logic circuit is verified by detecting the coincidence / mismatch of the outputs. The configuration is known (see, for example, Patent Document 1). Hereinafter, such a semiconductor integrated circuit including two logic circuits having the same function is referred to as a “duplicated logic circuit”.

  As other methods for improving the reliability of the semiconductor integrated circuit, there are methods described in Patent Document 2 and Non-Patent Document 1.

  Patent Document 2 includes a storage circuit that operates in synchronization with one clock signal and a storage circuit that operates in synchronization with the other clock signal obtained by delaying the clock signal. Is stored in these two storage circuits, and the two stored values are compared to detect an increase in calculation time generated in the calculation circuit.

  In Non-Patent Document 1, the output value of the arithmetic circuit is stored in the storage circuit in synchronization with the clock signal, and the same output value of the arithmetic circuit is stored in another storage circuit at an earlier point in time. A method is described in which it is determined that the calculation time of the calculation circuit has increased when the two stored values are different.

  The semiconductor integrated circuit according to the background art described above has a problem that it can detect a failure that has already occurred, but cannot detect an event (failure factor) that occurs before the failure occurs. Hereinafter, this problem will be described.

  FIG. 1 is a block diagram showing the configuration of the background art of a semiconductor integrated circuit, and FIG. 2 is a timing chart showing how the semiconductor integrated circuit shown in FIG. 1 detects a failure.

  The background art semiconductor integrated circuit shown in FIG. 1 includes a first logic circuit including a memory circuit FF0A, an arithmetic circuit L1A, and a memory circuit FF1A, and a second logic circuit including a memory circuit FF0B, an arithmetic circuit L1B, and a memory circuit FF1B. The configuration includes a logic circuit and a comparison circuit C1 that outputs a comparison result as to whether or not the output value of the memory circuit FF1A matches the output value of the memory circuit FF1B. The first logic circuit and the second logic circuit have the same function.

  The memory circuits FF0A, FF1A, FF0B, and FF1B hold and output the input value in synchronization with the clock signal supplied to each of them. In addition, the arithmetic circuits L1A and L1B execute predetermined arithmetic processing on the input value, and output the arithmetic result after a predetermined arithmetic time has elapsed.

  Hereinafter, like the calculation time of the calculation circuits L1A and L1B, the time required for inputting a value to the circuit and outputting the corresponding value is referred to as “delay time”.

  The output value of the memory circuit FF0A is input to the arithmetic circuit L1A, and the output value of the arithmetic circuit L1A is input to the memory circuit FF1A. The output value of the memory circuit FF0B is input to the arithmetic circuit L1B, and the output value of the arithmetic circuit L1B is input to the memory circuit FF1B.

  The same clock signal CK is supplied to the memory circuits FF0A, FF1A, FF0B, and FF1B, and the output values of the memory circuits FF1A and FF1B are input to the comparison circuit C1.

  As shown in FIG. 1, in the semiconductor integrated circuit according to the background art, the same clock signal CK having the cycle T is supplied to the memory circuits FF0A, FF1A, FF0B, and FF1B.

  As shown in FIG. 2, the memory circuits FF0A, FF1A, FF0B, and FF1B hold the input value in synchronization with the rising edge of the clock signal CK and output the value.

  Here, for example, it is assumed that at time D (L1 (D2)), the arithmetic circuit L1A outputs an incorrect value F ′ (D2), and the arithmetic circuit L1B outputs a correct value F (D2).

  In this case, at time T, the memory circuit FF1A holds and outputs the incorrect value F ′ (D2) output from the arithmetic circuit L1A, and the memory circuit FF1B outputs the correct value F (D2) output from the arithmetic circuit L1B. Is output. Therefore, since the output value of the memory circuit FF1A and the output value of the memory circuit FF1B do not match, the output value of the comparison circuit C1 changes (in the example shown in FIG. 2, the logic “0” (Low level) changes to the logic “1”. (High level)). Therefore, it can be determined whether or not a failure has occurred by monitoring the output value of the comparison circuit C1.

  By the way, as a failure factor that occurs in the semiconductor integrated circuit as shown in FIG. 1, an increase in the delay time of the arithmetic circuit or a decrease in the delay time due to performance deterioration of the transistor or the like can be considered. For example, when the delay time of the arithmetic circuit L1A shown in FIG. 1 increases and becomes longer than the cycle of the clock signal CK, the memory circuit FF1A erroneously outputs from the arithmetic circuit L1A in synchronization with the rising edge of the clock signal CK. Incorrect calculation result is output because the calculation result is taken in. On the other hand, if the delay time of the arithmetic circuit L1A shown in FIG. 1 decreases and becomes shorter than the hold time of the memory circuit FF1A, the memory circuit FF1A cannot correctly capture the arithmetic result of the arithmetic circuit L1A. Output the result.

  FIG. 3 is a timing chart showing how the semiconductor integrated circuit shown in FIG. 1 cannot detect a failure factor.

  Here, with respect to the value D2 input at time 0, the arithmetic circuit L1B outputs the correct arithmetic result value F (D2) at time D (L1 (D2)), and the arithmetic circuit L1A outputs the time D (L1 An example will be described in which a correct operation result value F (D2) is output at a time d (L2 (D2)) + d later than (D2)).

  As shown in FIG. 3, when the time D (L1 (D2)) + d at which the operation result is output from the arithmetic circuit L1A is within the cycle T of the clock signal CK, the memory circuit FF1A starts from the arithmetic circuit L1A at time T. The output value F (D2) is held and output. The memory circuit FF1B holds and outputs the value F (D2) output from the arithmetic circuit L1B at time T.

  Therefore, the comparison circuit C1 cannot detect an increase in delay time generated in the arithmetic circuit L1A because the output value does not change because the same value is input. The increase in delay time generated in such an arithmetic circuit or the like increases with time, and eventually causes a malfunction of the semiconductor integrated circuit.

  In the circuits described in Patent Document 2 and Non-Patent Document 1 described above, an increase in delay time occurring in an arithmetic circuit or the like can be detected within a preset detection time range. However, an increase in the delay time exceeding the preset detection time cannot be detected. In the circuits described in Patent Document 2 and Non-Patent Document 1, an increase in delay time can be detected, but a decrease in delay time cannot be detected.

  Furthermore, in the semiconductor integrated circuit of the background art, it is impossible to determine which of the duplicated logic circuits is causing the failure. For example, by selecting the output of the normal logic circuit, the semiconductor integrated circuit The normal operation of the circuit cannot be maintained.

JP 2003-316599 A US Patent Publication No. 2005/0246613

T. Nakura et al., "Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops" (ISSCC2007)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit composed of duplicated logic circuits that can detect a failure factor such as an increase or decrease in delay time and improve operation reliability. To do.

In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a first arithmetic circuit that executes predetermined arithmetic processing,
A second arithmetic circuit that executes the same arithmetic processing as the first arithmetic circuit;
A first memory circuit connected to an input of the first arithmetic circuit and holding and outputting an input value in synchronization with a first clock signal;
A second memory circuit connected to the output of the first arithmetic circuit and holding and outputting an input value in synchronization with a second clock signal;
A third memory circuit connected to the input of the second arithmetic circuit and holding and outputting an input value in synchronization with a third clock signal;
A fourth memory circuit connected to the output of the second arithmetic circuit and holding and outputting an input value in synchronization with a fourth clock signal;
A first comparison circuit that outputs a comparison result as to whether or not the output value of the second storage circuit and the output value of the fourth storage circuit match;
Have
The first, second, third, and fourth clock signals are signals that alternately repeat a first period and a second period, and the start of each of the first periods coincides, and The end of the second cycle coincides,
At least one of the first, second, third, and fourth clock signals has a length different from the first period and the second period, and at least one of the other clock signals and Different signal patterns.
Alternatively, a first logic circuit including a plurality of first arithmetic circuits that execute predetermined arithmetic processing and a plurality of first memory circuits that are alternately connected to the plurality of first arithmetic circuits,
A second logic circuit including a second arithmetic circuit that executes the same arithmetic processing as the first arithmetic circuit and a plurality of second memory circuits that are alternately connected to the plurality of second arithmetic circuits; ,
A plurality of comparison circuits each outputting a comparison result as to whether or not the output value of the first storage circuit and the output value of the second storage circuit match;
Have
The first clock signal and the second clock signal are alternately supplied to the plurality of first memory circuits,
A third clock signal and a fourth clock signal are alternately supplied to the plurality of second memory circuits,
The first, second, third, and fourth clock signals are signals that alternately repeat a first period and a second period, and the start of each of the first periods coincides, and The end of the second cycle coincides,
At least one of the first, second, third, and fourth clock signals has a length different from the first period and the second period, and at least one of the other clock signals and Different signal patterns.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit of the background art. FIG. 2 is a timing chart showing how the semiconductor integrated circuit shown in FIG. 1 detects a failure. FIG. 3 is a timing chart showing how the semiconductor integrated circuit shown in FIG. 1 cannot detect a failure factor. FIG. 4 is a block diagram showing the configuration of the semiconductor integrated circuit of the first embodiment. FIG. 5A is a timing chart showing an example of each clock signal supplied to the semiconductor integrated circuit of the first embodiment. FIG. 5B is a timing chart illustrating the operation of the semiconductor integrated circuit according to the first embodiment. FIG. 5C is a timing chart illustrating the operation of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a block diagram showing the configuration of the semiconductor integrated circuit of the second embodiment. FIG. 7 is a timing chart showing the operation when no failure factor has occurred in the semiconductor integrated circuit of the second embodiment. FIG. 8 is a timing chart showing the operation of the semiconductor integrated circuit according to the second embodiment when a failure factor that increases the delay time occurs in the arithmetic circuit L1A. FIG. 9 is a timing chart showing the operation of the semiconductor integrated circuit according to the second embodiment when a failure factor that increases the delay time occurs in the arithmetic circuit L1B. FIG. 10 is a block diagram showing the configuration of the semiconductor integrated circuit of the third embodiment. FIG. 11 is a timing chart showing the operation when no failure factor has occurred in the semiconductor integrated circuit of the fourth embodiment. FIG. 12 is a timing chart showing an operation in the semiconductor integrated circuit according to the fourth embodiment when a failure factor causing a decrease in delay time occurs in the arithmetic circuit L1A. FIG. 13 is a timing chart showing the operation of the semiconductor integrated circuit of the fifth embodiment. FIG. 14 is a timing chart showing the operation of the semiconductor integrated circuit according to the sixth embodiment. FIG. 15 is a block diagram showing the configuration of the semiconductor integrated circuit of the seventh embodiment. FIG. 16 is a block diagram showing the configuration of the semiconductor integrated circuit of the eighth embodiment. FIG. 17 is a block diagram showing the configuration of the semiconductor integrated circuit of the ninth embodiment. FIG. 18 is a block diagram showing the configuration of the semiconductor integrated circuit of the tenth embodiment. FIG. 19 is a block diagram showing the configuration of the semiconductor integrated circuit of the eleventh embodiment. FIG. 20 is a block diagram showing the configuration of the semiconductor integrated circuit of the twelfth embodiment. FIG. 21 is a block diagram showing the configuration of the semiconductor integrated circuit of the thirteenth embodiment. FIG. 22 is a timing chart showing the operation of the semiconductor integrated circuit of the thirteenth embodiment. FIG. 23 is a block diagram showing the configuration of the semiconductor integrated circuit of the fourteenth embodiment. FIG. 24 is a block diagram showing the configuration of the semiconductor integrated circuit of the fifteenth embodiment. FIG. 25 is a timing chart showing the operation of the semiconductor integrated circuit of the fifteenth embodiment. FIG. 26 is a block diagram showing the configuration of the semiconductor integrated circuit according to the sixteenth embodiment. FIG. 27 is a timing chart showing the operation of the semiconductor integrated circuit according to the sixteenth embodiment. FIG. 28 is a block diagram showing the configuration of the semiconductor integrated circuit according to the seventeenth embodiment. FIG. 29 is a timing chart showing the operation of the semiconductor integrated circuit of the seventeenth embodiment. FIG. 30 is a block diagram showing the configuration of the semiconductor integrated circuit of the eighteenth embodiment. FIG. 31 is a timing chart showing the operation of the semiconductor integrated circuit of the eighteenth embodiment. FIG. 32 is a block diagram showing the configuration of the semiconductor integrated circuit of the nineteenth embodiment. FIG. 33A is a block diagram showing the configuration of the semiconductor integrated circuit of the twentieth embodiment. FIG. 33B is a block diagram showing a configuration of a modified example of the semiconductor integrated circuit of the twentieth embodiment. FIG. 34 is a flowchart showing the processing procedure of the clock control circuit provided in the semiconductor integrated circuit of the twentieth embodiment. FIG. 35 is a block diagram showing the configuration of the semiconductor integrated circuit of the twenty-first embodiment. FIG. 36 is a block diagram showing the configuration of the semiconductor integrated circuit of the twenty-second embodiment. FIG. 37 is a flowchart showing the test procedure of the semiconductor integrated circuit of the twenty-third embodiment. FIG. 38 is a flowchart showing the test procedure of the semiconductor integrated circuit of the twenty-fourth embodiment.

Next, the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 4 is a block diagram showing the configuration of the semiconductor integrated circuit of the first embodiment.

  As shown in FIG. 4, the semiconductor integrated circuit of the first embodiment includes a first logic circuit including a memory circuit FF0A, an arithmetic circuit L1A, and a memory circuit FF1A, a memory circuit FF0B, an arithmetic circuit L1B, and a memory circuit FF1B. The second logic circuit is provided, and a comparison circuit C1 that outputs a comparison result as to whether or not the output value of the memory circuit FF1A and the output value of the memory circuit FF1B match. The first logic circuit and the second logic circuit have the same function.

  The memory circuits FF0A, FF1A, FF0B, and FF1B hold and output the input value in synchronization with the rising edge of the clock signal supplied thereto. In addition, the arithmetic circuits L1A and L1B execute predetermined arithmetic processing on the input value, and output the arithmetic result after a predetermined arithmetic time has elapsed.

  The output value of the memory circuit FF0A is input to the arithmetic circuit L1A, and the output value of the arithmetic circuit L1A is input to the memory circuit FF1A. The output value of the memory circuit FF0B is input to the arithmetic circuit L1B, and the output value of the arithmetic circuit L1B is input to the memory circuit FF1B. The output values of the memory circuits FF1A and FF1B are input to the comparison circuit C1.

  In the semiconductor integrated circuit of the first embodiment, the clock signal CKA is supplied to the memory circuit FF0A, and the clock signal CKA ′ is supplied to the memory circuit FF1A. Further, the clock signal CKB is supplied to the memory circuit FF0B, and the clock signal CKB ′ is supplied to the memory circuit FF1B.

  FIG. 5A is a timing chart showing an example of each clock signal supplied to the semiconductor integrated circuit of the first embodiment.

  As shown in FIG. 5A, the clock signal CKA is a signal that alternately repeats the first cycle T1A and the second cycle T2A, and the clock signal CKA ′ includes the first cycle T1A ′ and the second cycle T2A ′. Is a signal that repeats alternately. The clock signal CKB is a signal that alternately repeats the first cycle T1B and the second cycle T2B, and the clock signal CKB ′ is a signal that alternately repeats the first cycle T1B ′ and the second cycle T2B ′. It is.

Note that in order for the first logic circuit and the second logic circuit shown in FIG. 4 to operate correctly as a synchronous circuit, the memory circuits FF0A and FF0B are already at the time when the memory circuits FF1A and FF1B hold the input values. Value must be output,
T1A ≦ T1A '…………………… (1)
And T1B ≦ T1B '…………………… (2)
It is necessary to satisfy the conditions.

  However, the setup time and hold time of each memory circuit are negligible.

  The clock signals CKA, CKA ′, CKB, and CKB ′ are assumed to have the same start of the first period and the same end of the second period.

  In addition, at least one of the clock signals CKA, CKA ′, CKB, and CKB ′ has a length different between the first period and the second period.

  Further, at least one of the clock signals CKA, CKA ′, CKB and CKB ′ has a signal pattern different from that of the other clock signals.

  FIG. 5A shows that the clock signals CKA, CKA ′, CKB and CKB ′ each have a first period and a second period having different lengths, and each clock signal has a signal pattern different from other clock signals. An example is shown.

  For example, Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno, "A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test" Capability ", ISSCC 2007 digest of technical papers, pp. 174-175. (Hereinafter referred to as non-patent document 2) and the like.

  In the following, an example in which the duty ratio of each of the first and second cycles of each clock signal (the ratio of the period in which the signal value occupies the entire cycle is 1) is 50%, respectively, the first cycle and The duty ratio of the second cycle is not limited to 50%.

  A storage circuit (including a comparison storage circuit to be described later) will be described as an example of holding an input value in synchronization with a rising edge of a clock signal and outputting the held value. Any configuration may be used.

  In the following description, it is assumed that the computation time (delay time) of the arithmetic circuits L1A and L1B is the same, but the two arithmetic circuits may have different internal configurations as long as their processing functions are the same. The times may be different.

  These conditions are also applied to second to seventeenth embodiments described later.

  Next, the operation of the semiconductor integrated circuit according to the first embodiment will be described with reference to the drawings.

  5B and 5C are timing charts showing the operation of the semiconductor integrated circuit of the first embodiment.

  The solid line in FIG. 5B shows the operation when the failure factor that increases the delay time does not occur in the arithmetic circuit L1A shown in FIG. 4, and the dotted line in FIG. 5B shows the delay time in the arithmetic circuit L1A shown in FIG. This shows the operation when a failure factor occurs.

  When the failure factor that increases the delay time does not occur in the arithmetic circuit L1A, the output value of the memory circuit FF1A becomes logic “1” (High level), and the output value of the memory circuit FF1B also becomes logic “1”. The output value of the comparison circuit C1 is stabilized at logic “0” (Low level).

  On the other hand, when a failure factor that increases the delay time occurs in the arithmetic circuit L1A, the output value of the memory circuit FF1A becomes logic “0” and the output value of the memory circuit FF1B becomes logic “1”. The output value of the circuit C1 becomes logic “1”.

  Therefore, by monitoring the output value of the comparison circuit C1, it is possible to determine whether or not a failure factor that increases the delay time occurs.

  Note that, as indicated by the solid line in FIG. 5B, there is a period in which the output value of the comparison circuit C1 is logic “1” even when there is no failure factor that increases the delay time in the arithmetic circuit L1A. However, this can be ignored by setting the period from the rise of any one of the clock signals CKA, CKA ', CKB and CKB' to the rise of all the remaining clock signals as the dead period of the comparison result.

  The solid line in FIG. 5C shows the operation when there is no failure factor causing the delay time to decrease in the arithmetic circuit L1A shown in FIG. 4, and the dotted line in FIG. 5C shows the delay time in the arithmetic circuit L1A shown in FIG. This shows the operation when a failure factor occurs.

  When there is no failure factor that reduces the delay time in the arithmetic circuit L1A, the time when the output value of the arithmetic circuit L1A becomes logic “1” is after the clock signal CKA ′ rises, and the output value of the memory circuit FF1A Becomes logic “0”, and the output value of the memory circuit FF1B also becomes logic “0”. Therefore, the output value of the comparison circuit C1 is stabilized at logic “0”.

  On the other hand, when a failure factor that reduces the delay time occurs in the arithmetic circuit L1A, the time when the output value of the arithmetic circuit L1A becomes logic “1” is before the clock signal CKA ′ rises, and the output of the memory circuit FF1A Since the value is logic “1” and the output value of the memory circuit FF1B is logic “0”, the output value of the comparison circuit C1 is logic “1”.

  Therefore, by monitoring the output value of the comparison circuit C1, it is possible to determine whether or not a failure factor that reduces the delay time occurs.

  According to the semiconductor integrated circuit of the first embodiment, the start of the first cycle of each clock signal coincides with the end of the second cycle, and at least one of the clock signals supplied to each memory circuit is the first. A clock signal in which the first cycle and the second cycle are alternately repeated, and at least one of them has a signal pattern different from that of the other clock signals, is repeated to each memory circuit. By supplying and comparing the values of the storage circuit at the final stage of the duplicated logic circuit, a failure factor that increases or decreases the delay time generated in the logic circuit can be detected.

Here, in the clock signals CKA, CKA ′, CKB and CKB ′ shown in FIG. 5A,
T1A '<T1B' …………………… (3)
Or T1A> T1B …………………… (4)
When the above condition is satisfied, the time from the rise of the clock signal CKA input to the memory circuit FFA0 to the rise of the clock signal CKA ′ input to the memory circuit FFA1 is the rise of the clock signal CKB input to the memory circuit FFB0. Is shorter than the time until the clock signal CKB ′ input to the memory circuit FFB1 rises. Therefore, it is possible to detect a failure factor that increases the delay time occurring in the arithmetic circuit L1A.

Also,
T1A '>T1B' …………………… (5)
Or T1A <T1B …………………… (6)
When the above condition is satisfied, the time from the rise of the clock signal CKA input to the memory circuit FFA0 to the rise of the clock signal CKA ′ input to the memory circuit FFA1 is the rise of the clock signal CKB input to the memory circuit FFB0. Longer than the time until the clock signal CKB ′ input to the memory circuit FFB1 rises. Therefore, it is possible to detect a failure factor that increases the delay time generated in the arithmetic circuit L1B.

In the clock signals CKA, CKA ′, CKB and CKB ′ shown in FIG. 5A,
T1A <T1A '…………………… (7)
If the delay time of the arithmetic circuit L1A has not changed when the above condition is satisfied, the memory circuit FF1A obtains the calculation result of the value output from the memory circuit FF0A in synchronization with the rising of the first cycle of the clock signal CKA. If the delay time of the arithmetic circuit L1A decreases, the memory circuit FF1A holds the arithmetic result of the value output from the memory circuit FF0A in synchronization with the rising of the second period of the clock signal CKA. Therefore, it is possible to detect a failure factor that reduces the delay time occurring in the arithmetic circuit L1A.

Also,
T1B <T1B '………………………… (8)
If the delay time of the arithmetic circuit L1B does not change when the above condition is satisfied, the memory circuit FF1B outputs the arithmetic result of the value output from the memory circuit FF0B in synchronization with the rising of the first cycle of the clock signal CKB. If the delay time of the arithmetic circuit L1B decreases, the memory circuit FF1B holds the arithmetic result of the value output from the memory circuit FF0B in synchronization with the rising of the second period of the clock signal CKB. Therefore, it is possible to detect a failure factor that reduces the delay time occurring in the arithmetic circuit L1B.
(Second embodiment)
FIG. 6 is a block diagram showing the configuration of the semiconductor integrated circuit of the second embodiment.

  As shown in FIG. 6, the semiconductor integrated circuit of the second embodiment includes a comparison memory circuit FFC1 for holding the output value of the comparison circuit C1, in addition to the semiconductor integrated circuit of the first embodiment shown in FIG. This is a configuration provided. A signal obtained by inverting the clock signal CKB ′ by the inverting circuit NOT is supplied to the comparison memory circuit FFC1. Note that a signal obtained by inverting the clock signal CKA, CKA ', or CKB may be supplied to the comparison memory circuit FFC1.

  The semiconductor integrated circuit of the second embodiment is an example in which the clock signals CKA, CKA ′, CKB, and CKB ′ supplied to each logic circuit satisfy the above conditions (3) and (6).

  FIG. 7 is a timing chart showing the operation when no failure factor has occurred in the semiconductor integrated circuit of the second embodiment.

  As shown in FIG. 7, the clock signals CKA and CKA ′ supplied to the semiconductor integrated circuit according to the second embodiment alternately repeat the first cycle TS and the second cycle TL longer than the first cycle TS. Signal. The clock signals CKB and CKB ′ are signals that alternately repeat the first cycle TL and the second cycle TS shorter than the first cycle TL. That is, the clock signals CKA, CKA ′, CKB and CKB ′ supplied to each logic circuit satisfy the above conditions (3) and (6).

  Here, to simplify the description, the first period TS of the clock signals CKA and CKA ′ is equal to the second period TS of the clock signals CKB and CKB ′, and the second period TS of the clock signals CKA and CKA ′ is the same. And the first cycle TL of the clock signal CKB and the clock signal CKB ′ are equal.

  As shown in FIG. 7, at time 0, the memory circuit FF0A holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKA, and the memory circuit FF1A synchronizes with the rising edge of the clock signal CKA ′. The input value F (D1) is held and output. The storage circuit FF0B holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D1) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  The arithmetic circuits L1A and L1B, to which the value D2 is input at time 0, change the output value to F (D2) at time D (L1 (D2)). That is, the time D (L1 (D2)) is a calculation time necessary for the calculation of the value D2 when the arithmetic circuits L1A and L1B are normal.

  At time TS, the storage circuit FF0A holds and outputs the input value D3 in synchronization with the rising edge of the clock signal CKA, and the storage circuit FF1A inputs the input value F (D2 in synchronization with the rising edge of the clock signal CKA ′. ) Is output. At time TS, the memory circuits FF0B and FF1B do not operate, and thus the output value F (D2) of the memory circuit FF1A does not match the output value F (D1) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 changes (in the example shown in FIG. 7, the logic “0” to the logic “1”).

  The arithmetic circuit L1A to which the value D3 is input at the time TS changes its output value to F (D3) at the time TS + D (L1 (D3)). That is, the time D (L1 (D3)) is an operation time necessary for the operation of the value D3 when the operation circuit L1A is normal.

  At time TL, the storage circuit FF0B holds and outputs the input value D3 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D2 in synchronization with the rising edge of the clock signal CKB ′. ) Is output. At time TL, since the memory circuits FF0A and FF1A do not operate, the output value F (D2) of the memory circuit FF1A matches the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 returns to the original value (in the example shown in FIG. 7, the logic “1” to the logic “0”).

  The arithmetic circuit L1B, to which the value D3 is input at time TL, changes its output value to F (D3) at time TL + D (L1 (D3)). That is, the time D (L1 (D3)) is an operation time necessary for the operation of the value D3 when the operation circuit L1B is normal.

  At time TL + TS, the storage circuit FF0A holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKA, and the storage circuit FF1A outputs the input value F (in synchronization with the rising edge of the clock signal CKA ′. D3) is held and output. The storage circuit FF0B holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D3) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  Thereafter, the semiconductor integrated circuit of the second embodiment repeats the same operation as the operation from time 0 to time TL + TS shown in FIG.

  As described above, in the semiconductor integrated circuit of the second embodiment, a signal obtained by inverting the clock signal CKB ′ is supplied to the comparison memory circuit FFC1. Therefore, as shown in FIG. 7, even if the output value of the comparison circuit C1 changes during the period from the rise of the clock signal CKA to the rise of the clock signal CKB ′, the output value of the comparison storage circuit FFC1 does not change. That is, in the semiconductor integrated circuit according to the second embodiment, if each logic circuit operates normally, the output value of the comparison memory circuit FFC1 does not change. It is possible to determine whether or not a failure factor that increases time occurs.

  FIG. 8 is a timing chart showing the operation of the semiconductor integrated circuit according to the second embodiment when a failure factor that increases the delay time occurs in the arithmetic circuit L1A.

  Note that the clock signals CKA, CKA ′, CKB, and CKB ′ illustrated in FIG. 8 are the same as the clock signals CKA, CKA ′, CKB, and CKB ′ illustrated in FIG.

  As shown in FIG. 8, at time 0, the memory circuit FF0A holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKA, and the memory circuit FF1A synchronizes with the rising edge of the clock signal CKA ′. The input value F (D1) is held and output. The storage circuit FF0B holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D1) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  The arithmetic circuit L1B to which the value D2 is input at time 0 changes its output value to F (D2) at time D (L1 (D2)). On the other hand, since a failure factor with an increased delay time has occurred in the arithmetic circuit L1A, when the value D2 is input at time 0, the output value is changed to F (D2) at time D (L1 (D2)) + d. Change.

  At time TS, the memory circuit FF0A holds and outputs the input value D3 in synchronization with the rising edge of the clock signal CKA. Further, since the output value of the arithmetic circuit L1A is F (D1), the memory circuit FF1A again holds and outputs the input value F (D1) in synchronization with the rising edge of the clock signal CKA '. Even if the input value changes to F (D2) at time D (L1 (D2)) + d, the memory circuit FF1A maintains the output value at F (D1) until the next rising edge of the clock signal CKA '.

  The arithmetic circuit L1A to which the value D3 is input at the time TS changes its output value to F (D3) at the time TS + D (L1 (D3)).

  At time TS, since the memory circuits FF0B and FF1B do not operate, the output value F (D1) of the memory circuit FF1A matches the output value F (D1) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 does not change (logic “0” in the example shown in FIG. 8).

  Next, at time TL, the storage circuit FF0B holds and outputs the input value D3 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B inputs in synchronization with the rising edge of the clock signal CKB ′. The value F (D2) is held and output. At time TL, since the memory circuits FF0A and FF1A do not operate, the output value F (D1) of the memory circuit FF1A does not match the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 changes (in the example shown in FIG. 8, logic “0” to logic “1”).

  The arithmetic circuit L1B, to which the value D3 is input at time TL, changes its output value to F (D3) at time TL + D (L1 (D3)).

  Further, the comparison memory circuit FFC1 holds and outputs the output value of the comparison circuit C1 (logic “1” in the example shown in FIG. 8) at the time TL + TS / 2.

  Next, at time TL + TS, the memory circuit FF0A holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKA. Since the output value of the arithmetic circuit L1A changes to F (D3) at time TL + D (L1 (D3)), the memory circuit FF1A holds the input value F (D3) in synchronization with the rising edge of the clock signal CKA ′. Output. The storage circuit FF0B holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D3) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  At time TL + TS, the output value F (D3) of the memory circuit FF1A matches the output value F (D3) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 returns to the original value (in the example shown in FIG. 8, logic “1” to logic “0”). Even when the input value changes to logic “0” at time TL + TS, the comparison memory circuit FFC1 maintains the output value at logic “0” until the next rising edge of the clock signal CKB ′ supplied by being inverted.

  Therefore, by monitoring the output value of the comparison memory circuit FFC1, it is possible to detect a failure factor that increases the delay time generated in the arithmetic circuit L1A.

  FIG. 9 is a timing chart showing the operation of the semiconductor integrated circuit according to the second embodiment when a failure factor that increases the delay time occurs in the arithmetic circuit L1B.

  The clock signals CKA, CKA ′, CKB and CKB ′ shown in FIG. 9 are the same as the clock signals CKA, CKA ′, CKB and CKB ′ shown in FIG. In the operation example shown in FIG. 9, the operation from time 0 to time TL is the same as the operation example shown in the timing chart of FIG. Therefore, the description thereof is omitted here.

  As shown in FIG. 9, since a failure factor with an increased delay time has occurred in the arithmetic circuit L1B, when the value D3 is input at time TL, the output value is output at time TL + D (L1 (D3)) + d. Change to F (D3).

  At time TL + TS, the storage circuit FF0A holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKA, and the storage circuit FF1A outputs the input value F (in synchronization with the rising edge of the clock signal CKA ′. D3) is held and output. The memory circuit FF0B holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKB.

  Since the output value of the arithmetic circuit L1B is F (D2), the memory circuit FF1B again holds and outputs the input value F (D2) in synchronization with the rising edge of the clock signal CKB '. Even when the input value changes to F (D3) at time TL + D (L1 (D3)) + d, the memory circuit FF1B maintains the output value at F (D2) until the next rising edge of the clock signal CKB '.

  At time TL + TS, the output value F (D3) of the memory circuit FF1A does not match the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 changes (in the example shown in FIG. 9, the logic “0” to the logic “1”).

  The comparison memory circuit FFC1 holds and outputs the output value of the comparison circuit C1 (logic “1” in the example shown in FIG. 9) at time TL + TS + TL / 2.

Therefore, by monitoring the output value of the comparison memory circuit FFC1, it is possible to detect a failure factor that increases the delay time occurring in the arithmetic circuit L1B.
(Third embodiment)
FIG. 10 is a block diagram showing the configuration of the semiconductor integrated circuit of the third embodiment.

  As shown in FIG. 10, in the semiconductor integrated circuit of the third embodiment, a clock signal CKB ′ is received using a delay circuit d1 instead of the inverting circuit NOT included in the semiconductor integrated circuit of the second embodiment shown in FIG. In this configuration, the delayed signal is supplied to the comparison memory circuit FFC1. Since other configurations and operations are the same as those of the second embodiment, the description thereof is omitted.

Even in such a configuration, as in the second embodiment, if each logic circuit is operating normally, the output value of the comparison memory circuit FFC1 does not change, so only the output value of the comparison memory circuit FFC1 is monitored. It is possible to determine whether or not a failure factor with an increased delay time has occurred.
(Fourth embodiment)
The semiconductor integrated circuit according to the fourth embodiment is an example in which the clock signals CKA, CKA ′, CKB and CKB ′ supplied to each logic circuit satisfy the above conditions (7) and (8). Since the configuration of the semiconductor integrated circuit of the fourth embodiment is the same as that of the second embodiment, description thereof is omitted.

  FIG. 11 is a timing chart showing the operation when no failure factor has occurred in the semiconductor integrated circuit of the fourth embodiment.

  As shown in FIG. 11, the clock signals CKA and CKB are signals that alternately repeat a first cycle TS and a second cycle TL that is longer than the first cycle TS. Further, the clock signals CKA ′ and CKB ′ are signals having a period T. That is, the clock signals CKA, CKA ′, CKB and CKB ′ supplied to each logic circuit satisfy the above conditions (7) and (8).

  As shown in FIG. 11, at time 0, the memory circuit FF0A holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKA, and the memory circuit FF1A synchronizes with the rising edge of the clock signal CKA ′. The input value F (D1) is held and output. The storage circuit FF0B holds and outputs the input value D2 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D1) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  The arithmetic circuits L1A and L1B, to which the value D2 is input at time 0, change the output value to F (D2) at time D (L1 (D2)). That is, the time D (L1 (D2)) is a calculation time necessary for the calculation of the value D2 when the arithmetic circuits L1A and L1B are normal.

  At time TS, the storage circuit FF0A holds and outputs the input value D3 in synchronization with the rising edge of the clock signal CKA, and the storage circuit FF1A holds the input value D3 in synchronization with the rising edge of the clock signal CKB. And output. At time TS, since the memory circuits FF0B and FF1B do not operate, the output value F (D2) of the memory circuit FF1A matches the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 does not change (logic “0” in the example shown in FIG. 11).

  The arithmetic circuits L1A and L1B, to which the value D3 is input at the time TS, change the output value to F (D3) at the time TS + D (L1 (D3)). That is, the time D (L1 (D3)) is a calculation time necessary for the calculation of the value D3 when the arithmetic circuits L1A and L1B are normal.

  Next, at time T, the memory circuit FF1A holds and outputs the input value F (D2) in synchronization with the rising edge of the clock signal CKA ′, and the memory circuit FF1B reaches the rising edge of the clock signal CKB ′. In synchronization, the input value F (D2) is held and output. At time T, the output value F (D2) of the memory circuit FF1A matches the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 does not change (logic “0” in the example shown in FIG. 11).

  Subsequently, at time TL + TS (= 2T), the memory circuit FF0A holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKA, and the memory circuit FF1A synchronizes with the rising edge of the clock signal CKA ′. The input value F (D3) is held and output. The storage circuit FF0B holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D3) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  Thereafter, the semiconductor integrated circuit of the fourth embodiment repeats the same operation as the operation from time 0 to time TL + TS (= 2T) shown in FIG.

  In the operation example shown in FIG. 11, the output value of the comparison circuit C1 and the output value of the comparison storage circuit FFC1 do not change. That is, when the semiconductor integrated circuit according to the fourth embodiment operates normally, the output value of the comparison memory circuit FFC1 does not change.

  FIG. 12 is a timing chart showing an operation in the semiconductor integrated circuit according to the fourth embodiment when a failure factor causing a decrease in delay time occurs in the arithmetic circuit L1A.

  Note that the clock signals CKA, CKA ′, CKB, and CKB ′ illustrated in FIG. 12 are the same as the clock signals CKA, CKA ′, CKB, and CKB ′ illustrated in FIG. In the operation example shown in FIG. 12, the operation from time 0 to time TS is the same as the operation example shown in the timing chart of FIG. Therefore, the description thereof is omitted here.

  As shown in FIG. 12, since the failure factor that the delay time decreases occurs in the arithmetic circuit L1A, when the value D3 is input at the time TS, the output value at the time TS + D (L1 (D3))-d. Is changed to F (D3). On the other hand, the arithmetic circuit L1B to which the value D3 is input at the time TS changes the output value to F (D3) at the time TS + D (L1 (D3)).

  At time T, since the output value of the arithmetic circuit L1A is changed to F (D3) at time TS + D (L1 (D3)) − d, the memory circuit FF1A is input in synchronization with the rising edge of the clock signal CKA ′. The value F (D3) is held and output. The memory circuit FF1B holds and outputs the input value F (D2) in synchronization with the rising edge of the clock signal CKB '. At time T, the output value F (D3) of the memory circuit FF1A does not match the output value F (D2) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 changes (in the example shown in FIG. 12, “logic“ 0 ”to logic“ 1 ”)”.

  The comparison memory circuit FFC1 holds and outputs the output value of the comparison circuit C1 (logic “1” in the example shown in FIG. 12) at time T + T / 2.

  Next, at time TL + TS (= 2T), the memory circuit FF0A holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKA. The storage circuit FF1A again holds and outputs the input value F (D3) in synchronization with the rising edge of the clock signal CKA '. The storage circuit FF0B holds and outputs the input value D4 in synchronization with the rising edge of the clock signal CKB, and the storage circuit FF1B outputs the input value F (D3) in synchronization with the rising edge of the clock signal CKB ′. Hold and output.

  At time TL + TS, the output value F (D3) of the memory circuit FF1A matches the output value F (D3) of the memory circuit FF1B. Therefore, the output value of the comparison circuit C1 returns to the original value (in the example shown in FIG. 12, logic “1” to logic “0”). Even if the input value changes to logic “0” at time TL + TS (= 2T), the comparison memory circuit FFC1 outputs the output value to logic “1” until the next rising edge of the clock signal CKB ′ supplied by being inverted. Maintain with.

Therefore, by observing the output value of the comparison memory circuit FFC1, it is possible to detect a failure factor that reduces the delay time generated in the arithmetic circuit L1A.
(5th Example)
FIG. 13 is a timing chart showing the operation of the semiconductor integrated circuit of the fifth embodiment.

  The semiconductor integrated circuit of the fifth embodiment is an example in which the clock signals CKA, CKA ′, CKB and CKB ′ supplied to each logic circuit satisfy the above-described conditions (3), (6), (7) and (8). is there. Since the configuration of the semiconductor integrated circuit of the fifth embodiment is the same as that of the second embodiment, description thereof is omitted.

According to the semiconductor integrated circuit of the fifth embodiment, it is possible to detect a failure factor that increases the delay time of the arithmetic circuits L1A and L1B and a failure factor that decreases the delay time. Conditions (1) and (2) are included in conditions (7) and (8).
(Sixth embodiment)
FIG. 14 is a timing chart showing the operation of the semiconductor integrated circuit of the sixth embodiment.

The semiconductor integrated circuit of the sixth embodiment is an example in which the clock signals CKA, CKA ′, CKB and CKB ′ supplied to each logic circuit satisfy the above-mentioned conditions (4), (5), (7) and (8). is there. Since the configuration of the semiconductor integrated circuit of the sixth embodiment is the same as that of the second embodiment, the description thereof is omitted. According to the semiconductor integrated circuit of the sixth embodiment, the delay times of the arithmetic circuits L1A and L1B increase. A failure factor and a failure factor with a reduced delay time can be detected. Conditions (1) and (2) are included in conditions (7) and (8).
(Seventh embodiment)
FIG. 15 is a block diagram showing the configuration of the semiconductor integrated circuit of the seventh embodiment.

  The semiconductor integrated circuit of the seventh embodiment includes a comparison circuit C0 in addition to the semiconductor integrated circuit of the first embodiment shown in FIG. 4, and the comparison circuit C0 outputs the output value of the storage circuit FF0A and the output value of the storage circuit FF0B. Is a configuration for outputting a comparison result as to whether or not. Since other configurations and operations are the same as those of the semiconductor integrated circuit of the first embodiment, description thereof is omitted.

According to the semiconductor integrated circuit of the seventh embodiment, not only the failure factor that increases or decreases the delay time occurring in the arithmetic circuits L1A and L1B, but also the unillustrated circuit connected to the previous stage of the memory circuits FF0A and FF0B. A failure factor that increases or decreases the delay time generated in the logic circuit can also be detected.
(Eighth embodiment)
FIG. 16 is a block diagram showing the configuration of the semiconductor integrated circuit of the eighth embodiment.

  In the semiconductor integrated circuit according to the eighth embodiment, the comparison storage circuit FFC1 is connected to the output of the comparison circuit C1 included in the semiconductor integrated circuit according to the seventh embodiment shown in FIG. 15, and the comparison storage circuit FFC0 is connected to the output of the comparison circuit C0. It is a connected configuration. The comparison memory circuits FFC1 and FFC0 are supplied with signals obtained by inverting the clock signal CKB ′ by the inverting circuit NOT. Note that a signal obtained by inverting the clock signal CKA, CKA ', or CKB may be supplied to the comparison memory circuits FFC1 and FFC0. Further, the comparison memory circuits FFC1 and FFC0 may be supplied with a signal obtained by delaying the clock signal CKA, CKA ', CKB or CKB' as in the third embodiment. Since other configurations and operations are the same as those of the semiconductor integrated circuit of the seventh embodiment, description thereof is omitted.

According to the semiconductor integrated circuit of the eighth embodiment, the comparison results of the comparison circuits C1 and C0 can be held. Therefore, as in the semiconductor integrated circuit of the second embodiment, if each logic circuit operates normally, the comparison is possible. The output values of the memory circuits FFC1 and FFC0 do not change. Therefore, only by monitoring the output values of the comparison memory circuits FFC1 and FFC0, a failure factor that increases or decreases the delay time generated in the arithmetic circuits L1A and L1B, and a failure connected to the previous stage of the memory circuits FF0A and FF0B. A failure factor that increases or decreases the delay time generated in the illustrated logic circuit can be detected.
(Ninth embodiment)
FIG. 17 is a block diagram showing the configuration of the semiconductor integrated circuit of the ninth embodiment.

  As shown in FIG. 17, the semiconductor integrated circuit of the ninth embodiment displays only a plurality of memory circuits FF0A to FFnA (n is a positive positive number) and a plurality of arithmetic circuits L1A to LnA (in FIG. 17, only L1A and L2A). ) Alternately connected to each other, and a plurality of memory circuits FF0B to FFnB and a plurality of arithmetic circuits L1B to LnB (only L1B and L2B are shown in FIG. 17) connected to each other. And a plurality of comparison circuits C0 to Cn that respectively output comparison results as to whether or not the output values of the memory circuits FF0A to FFnA match the output values of the memory circuits FF0B to FFnB. is there. The first logic circuit and the second logic circuit have the same function.

  A multi-input comparison circuit Cmp is connected to the outputs of the comparison circuits C0 to Cn, and a comparison memory circuit FFC is connected to the output of the multi-input comparison circuit Cmp. A signal obtained by inverting the clock signal CKB 'is supplied to the comparison memory circuit FFC. Note that a signal obtained by inverting the clock signal CKA, CKA ′, or CKB may be supplied to the comparison memory circuit FFC. Further, a signal obtained by delaying the clock signal CKA, CKA ′, CKB or CKB ′ may be supplied to the comparison memory circuit FFC as in the third embodiment.

  The multi-input comparison circuit Cmp outputs a signal indicating a mismatch when at least one of the output values of the comparison circuits C0 to Cn does not match the other output values.

  Since the operations of the memory circuits FF0A to FFnA and FF0B to FFnB, the arithmetic circuits L1A to LnA and L1B to LnB, the comparison circuits C0 to Cn, and the comparison memory circuit FFC are the same as those in the second embodiment, description thereof is omitted.

According to the semiconductor integrated circuit of the ninth embodiment, even in a configuration including a plurality of arithmetic circuits, it is possible to detect a failure factor that increases or decreases the delay time generated in any of the arithmetic circuits.
(Tenth embodiment)
FIG. 18 is a block diagram showing the configuration of the semiconductor integrated circuit of the tenth embodiment.

  As shown in FIG. 18, the semiconductor integrated circuit of the tenth embodiment displays only a plurality of memory circuits FF0A to FFnA (n is a positive positive number) and a plurality of arithmetic circuits L1A to LnA (in FIG. 18, only L1A and L2A). ) Alternately connected to each other, and a plurality of memory circuits FF0B to FFnB and a plurality of arithmetic circuits L1B to LnB (only L1B and L2B are shown in FIG. 18) are connected to each other. And a plurality of comparison circuits C0 to Cn that respectively output comparison results as to whether or not the output values of the storage circuits FF0B to FFnB match the output values of the storage circuits FF0B to FFnB. is there. The first logic circuit and the second logic circuit have the same function.

  Multiplexers MUX0 to MUXn are connected to the outputs of the comparison circuits C0 to Cn, and comparison storage circuits FFC0 to FFCn are connected to the outputs of the multiplexers MUX0 to MUXn. A signal obtained by inverting the clock signal CKB 'is supplied to each of the comparison memory circuits FFC0 to FFCn. Note that a signal obtained by inverting the clock signal CKA, CKA ', or CKB may be supplied to the comparison memory circuit comparison memory circuits FFC0 to FFCn. Further, a signal obtained by delaying the clock signal CKA, CKA ', CKB or CKB' may be supplied to the comparison memory circuit comparison memory circuits FFC0 to FFCn as in the third embodiment.

  The multiplexers MUX0 to MUXn select the outputs of the comparison circuits C0 to Cn and output them to the comparison storage circuits FFC0 to FFCn during the normal operation of the semiconductor integrated circuit according to a control signal (not shown).

  Further, the multiplexers MUX0 to MUXn select the output of the comparison memory circuits FFC0 to FFCn-1 at the previous stage and output to the comparison memory circuits FFC0 to FFCn during the scan test of the semiconductor integrated circuit according to a control signal (not shown). That is, at the time of the scan test of the semiconductor integrated circuit, the output of the comparison memory circuit FFC (i−1) at the previous stage is input to the comparison memory circuit FFCi (i = 0 to n), and a known scan path is formed.

According to the semiconductor integrated circuit of the tenth embodiment, as with the semiconductor integrated circuit of the ninth embodiment, it is possible to detect a failure factor of increase or decrease in delay time occurring in any of a plurality of arithmetic circuits, and to compare By reading the comparison result held in the memory circuits FFC0 to FFCn as a serial signal, the arithmetic circuit in which the failure factor has occurred can be specified.
(Eleventh embodiment)
FIG. 19 is a block diagram showing the configuration of the semiconductor integrated circuit of the eleventh embodiment.

  The semiconductor integrated circuit of the eleventh embodiment is configured to supply a common clock signal CKA to the memory circuits FF0A, FF1A, and FF0B and to supply a clock signal CKB 'to the memory circuit FF1B. Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

  In the semiconductor integrated circuit according to the eleventh embodiment, a failure factor that causes an increase in delay time in the arithmetic circuit L1A, a failure factor that causes an increase in delay time in the arithmetic circuit L1B, and a failure that causes a delay time in the arithmetic circuit L1B to decrease. It is possible to detect the factor.

According to the semiconductor integrated circuit of the eleventh embodiment, since the number of clock signal wirings is reduced, the layout area of the semiconductor integrated circuit can be reduced.
(Twelfth embodiment)
FIG. 20 is a block diagram showing the configuration of the semiconductor integrated circuit of the twelfth embodiment.

  The semiconductor integrated circuit according to the twelfth embodiment is configured to supply a common clock signal CKA to the memory circuits FF0A and FF1A and to supply a common clock signal CKB to the memory circuits FF0B and FF1B. Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

  In the semiconductor integrated circuit of the twelfth embodiment, it is possible to detect a failure factor that increases the delay time generated in the arithmetic circuits L1A and L1B.

According to the semiconductor integrated circuit of the twelfth embodiment, since the number of clock signal wirings is reduced, the layout area of the semiconductor integrated circuit can be reduced.
(Thirteenth embodiment)
FIG. 21 is a block diagram showing the configuration of the semiconductor integrated circuit of the thirteenth embodiment.

  As shown in FIG. 21, the semiconductor integrated circuit of the thirteenth embodiment includes a plurality of memory circuits FF0A to FFnA (only FF0A to FF2A are shown in FIG. 21) and a plurality of arithmetic circuits L1A to LnA (L1A and L2A in FIG. 21). Only one display), a plurality of memory circuits FF0B to FFnB (only FF0B to FF2B are displayed in FIG. 21) and a plurality of arithmetic circuits L1B to LnB (in FIG. 21, L1B and L2B). A plurality of outputs of comparison results as to whether or not the output values of the second logic circuits and the memory circuits FF0B to FFnB and the output values of the memory circuits FF0B to FFnB coincide with each other. Comparison circuits C0 to Cn, failure determination circuits D0 and D1, and failure determination storage circuits FFD0 and FFD1. The first logic circuit and the second logic circuit have the same function.

  The failure determination circuit D0 receives the output value of the comparison circuit C0 and the failure diagnosis information errCHK, and the failure determination circuit D1 receives the output value of the comparison circuit C1 and the failure diagnosis information errCHK. The output value of failure determination circuit D0 is input to failure determination storage circuit FFD0, and the output value of failure determination circuit D1 is input to failure determination storage circuit FFD1.

  The output value of the failure determination storage circuit FFD0 is input to the failure determination circuit D0, and the output value of the failure determination storage circuit FFD1 is input to the failure determination circuit D1. The failure determination memory circuits FFD0 and FFD1 are supplied with a clock signal CKE.

  The failure diagnosis information is information for designating a failure diagnosis target logic circuit (first logic circuit or second logic circuit) and a failure factor type (increase or decrease in delay time). It is a signal that changes according to the period of the clock signal to be supplied.

  For example, when a short cycle clock signal is supplied to the first logic circuit and a long cycle clock signal is supplied to the second logic circuit, the delay time is reduced by the first logic circuit in the failure diagnosis information. A signal for designating whether or not a failure factor to occur (hereinafter referred to as delay reduction failure diagnosis) is used is used.

  On the other hand, when the long-cycle clock signal is supplied to the first logic circuit and the short-cycle clock signal is supplied to the second logic circuit, the failure diagnosis information includes the delay reduction failure diagnosis of the second logic circuit. A signal designating is used.

  FIG. 22 is a timing chart showing the operation of the semiconductor integrated circuit of the thirteenth embodiment.

  FIG. 22 shows an operation example when the clock signals CKA and CKA ′ are equal, the clock signals CKB and CKB ′ are equal, and an inverted signal of the clock signal CKB is supplied as the clock signal CKE to the failure determination storage circuits FFD0 and FFD1. Show.

  Further, in the operation example shown in FIG. 22, the operation from time 0 to time TS is the same as the operation example shown in the timing chart of FIG. Therefore, the description thereof is omitted here.

  At time TS, a signal (As) designating delay reduction failure diagnosis of the first logic circuit is input as failure diagnosis information errCHK. At this time, when a signal (logic “1”) indicating that the output values of the storage circuits FF1A and FF1B are different is output from the comparison circuit C1, the failure determination circuit D1 directly uses the output value of the comparison circuit C1 as the failure determination storage circuit. Output to FFD1.

  The failure determination storage circuit FFD1 holds and outputs the output value of the failure determination circuit D1 at time TL + TS / 2. The output of the failure determination storage circuit FFD1 is input to the failure determination circuit D1, and thereafter, the failure determination storage circuit FFD1 maintains the determination result of failure detection even if the output value of the comparison circuit C1 changes.

  At time TL + TS, a signal (B−s) that designates delay reduction failure diagnosis of the second logic circuit is input as failure diagnosis information errCHK. At this time, when a signal (logic “1”) indicating that the output values of the memory circuits FF1A and FF1B are different is output from the comparison circuit C1, the failure determination circuit D1 outputs the output value of the comparison circuit C1 as described above. Is output to the failure determination storage circuit FFD1, and the determination result is held by the failure determination storage circuit FFD1.

The semiconductor integrated circuit according to the thirteenth embodiment includes a failure determination circuit for determining a failure location and a failure factor from the result of the comparison circuit and failure diagnosis information, and a failure determination storage circuit for storing the failure determination result. Further, by reading out the comparison result to the outside in parallel, it is possible to determine the location of the failure and the type of failure factor that has occurred.
(14th embodiment)
FIG. 23 is a block diagram showing the configuration of the semiconductor integrated circuit of the fourteenth embodiment.

  The semiconductor integrated circuit according to the fourteenth embodiment is different from the semiconductor integrated circuit according to the thirteenth embodiment in that the output value of the failure determination storage circuit FFD0 is input to the failure determination circuit D1 at the next stage. That is, the semiconductor integrated circuit of this embodiment has a configuration in which a scan path is formed by a plurality of failure determination storage circuits. Since other configurations are the same as those of the thirteenth embodiment, the description thereof is omitted.

  For example, when the failure determination circuit D1 outputs a signal (logic “1”) indicating that the output value of the memory circuit FF1A is different from the output value of the FF1B, the cause is the failure factor in the arithmetic circuit L1A or L1B. Has occurred, the output value of the memory circuit FF1A differs from the output value of the memory circuit FF1B, or a failure factor has occurred in the logic circuit connected to the preceding stage (not shown), so that the output of the memory circuit FF0A The value is different from the output value of the storage circuit FF0B.

Therefore, when the output value of the failure determination circuit D0 indicates “no failure”, it can be determined that the failure factor has occurred in the arithmetic circuit L1A or L1B. In addition, when the output value of the failure determination circuit D0 indicates “no failure”, it can be determined that the failure factor has occurred in the logic circuit connected to the preceding stage (not shown).
(15th embodiment)
FIG. 24 is a block diagram showing the configuration of the semiconductor integrated circuit of the fifteenth embodiment.

  The semiconductor integrated circuit of the fifteenth embodiment is configured to include selection circuits S1 and S2 and failure determination storage circuits FFD0F and FFD1F in addition to the semiconductor integrated circuit of the fourteenth embodiment.

  The selection circuit S1 is inserted between the arithmetic circuits L1A and L1B and the memory circuits FF1A and FF1B. The selection circuit S2 is inserted between the arithmetic circuits L2A and L2B and the memory circuits FF2A and FF2B.

  The selection circuit S1 supplies either the output value of the arithmetic circuit L1A or the output value of the arithmetic circuit L1B to the memory circuits FF1A and FF1B according to the output values of the failure determination storage circuits FFD0 and FFD1F.

  The selection circuit S2 stores either the output value of the arithmetic circuit L2A or the output value of the arithmetic circuit L2B according to the output value of the failure determination storage circuit FFD1 and the FFD 2F (not shown) connected to the next stage, as the storage circuits FF2A and FF2B. Output to.

  The failure determination storage circuit FFD0F receives the output value of the failure determination circuit D0, and the output value of the failure determination storage circuit FFD0F is fed back to the input of the failure determination circuit D0. Further, the output value of the failure determination circuit D1 is input to the failure determination storage circuit FFD1F, and the output value of the failure determination storage circuit FFD1F is fed back to the input of the failure determination circuit D1.

  The failure determination storage circuit FFD0 is a circuit that holds the output value (determination result) of the failure determination circuit D0 for only one cycle of the clock signal CKE, and the failure determination storage circuit FFD0F continues the determination result of the failure determination circuit D0. It is a circuit for holding.

  The failure determination storage circuit FFD1 is a circuit that holds the determination result of the failure determination circuit D1 for a period of one cycle of the clock signal CKE, and the failure determination storage circuit FFD1F continuously holds the determination result of the failure determination circuit D1. It is a circuit for. Since other configurations are the same as those of the semiconductor integrated circuit of the fourteenth embodiment, description thereof is omitted.

  In the semiconductor integrated circuit according to the fifteenth embodiment, for example, when the failure determination circuit D1 determines that a failure factor has occurred in the arithmetic circuit L1A, the selection circuit S1 stores the output value of the normal arithmetic circuit L1B as a storage circuit. Supply to FF1A and FF1B.

  In that case, an erroneous output value is input from the memory circuit FF1A to the arithmetic circuit L2A at the next stage for only one cycle of the clock signal CKA '. Therefore, the selection circuit S2 outputs the output value of the arithmetic circuit L2B that has received the correct input value to the storage circuits FF2A and FF2B.

  FIG. 25 is a timing chart showing the operation of the semiconductor integrated circuit of the fifteenth embodiment.

  FIG. 25 shows an operation example when the clock signals CKA and CKA ′ are equal, the clock signals CKB and CKB ′ are equal, and an inverted signal of the clock signal CKB is supplied as the clock signal CKE to the failure determination storage circuits FFD0 and FFD1. Show.

  In the operation example shown in FIG. 25, the operation from time 0 to time TL + TS / 2 is the same as that of the thirteenth embodiment shown in FIG.

When failure determination storage circuits FFD1 and FFD1F hold the determination result of failure determination circuit D1 at time TL + TS / 2, selection circuit S1 outputs the output value of the arithmetic circuit in which no failure factor has occurred to storage circuits FF1A and FF1B. The selection circuit S2 supplies the output value of the arithmetic circuit that has received the correct input value to the memory circuits FF2A and FF2B.
(Sixteenth embodiment)
FIG. 26 is a block diagram showing the configuration of the semiconductor integrated circuit of the sixteenth embodiment.

  The semiconductor integrated circuit according to the sixteenth embodiment has a configuration including duplicated storage circuits FF0A and FF0B and an external input storage circuit FFin for storing values input from the outside of the semiconductor integrated circuit shown in FIG.

  The output value of the external input storage circuit FFin is input to the storage circuits FF0A and FF0B. A clock signal CKA is supplied to the memory circuit FF0A, and a clock signal CKB is supplied to the memory circuit FF0B.

  The external input storage circuit FFin is supplied with a clock signal for maintaining the output value until the storage circuits FF0A and FF0B hold the input values. For example, when the external input storage circuit FFin holds an input value in synchronization with the rising edge of the clock signal, the external input storage circuit FFin may be supplied with a logical product signal (CKA & CKB) of the clock signals CKA and CKB.

  FIG. 27 is a timing chart showing the operation of the semiconductor integrated circuit of the sixteenth embodiment.

  In the operation example shown in FIG. 27, a logical product signal (CKA & CKB) of clock signals CKA and CKB is supplied to the external input memory circuit FFin.

  In this case, the external input storage circuit FFin can maintain the output value until the storage circuits FF0A and FF0B hold the input values at the rising edges of the clock signals CKA and CKB.

According to the semiconductor integrated circuit of the sixteenth embodiment, a duplicated logic circuit and a non-duplexed logic circuit can be connected, and both can be used in combination. For this reason, it is possible to suppress an increase in circuit scale and power consumption more than necessary by duplicating only logic circuits that require high reliability and not duplicating other logic circuits. In addition, since an already designed logic circuit that is not duplicated can be used, existing design circuit assets can be utilized.
(Seventeenth embodiment)
FIG. 28 is a block diagram showing the configuration of the semiconductor integrated circuit of the seventeenth embodiment.

  In the semiconductor integrated circuit of the seventeenth embodiment, the duplicated storage circuits FF0A and FF0B, the selection circuit S1 that outputs one of the output values of the storage circuit FF0A or FF0B, and the output value of the selection circuit S1 are shown in FIG. And an external output memory circuit FFout for outputting to the outside of the semiconductor integrated circuit shown.

  The output values of the storage circuits FF0A and FF0B are output to the selection circuit S1, and the selection circuit S1 outputs either the output value of the storage circuit FF0A or the output value of the storage circuit FF0B according to a control signal (not shown) as the external output storage circuit FFout. Output to. A clock signal CKA is supplied to the memory circuit FF0A, and a clock signal CKB is supplied to the memory circuit FF0B.

  The external output memory circuit FFout is supplied with a clock signal for holding the value input before the output values of the memory circuits FF0A and FF0B change. For example, in the case where the external output storage circuit FFout is configured to hold an input value in synchronization with the rising edge of the clock signal, the logical output signal of the clock signals CKA and CKB may be supplied to the external output storage circuit FFout.

  FIG. 29 is a timing chart showing the operation of the semiconductor integrated circuit of the seventeenth embodiment.

  In the operation example shown in FIG. 29, the logical input signal (CKA | CKB) of the clock signals CKA and CKB is supplied to the external input memory circuit FFin.

  In this case, the external output storage circuit FFout can hold the input value before the output values of the storage circuits FF0A and FF0B change at the rising edges of the clock signals CKA and CKB.

According to the semiconductor integrated circuit of the seventeenth embodiment, as in the sixteenth embodiment, a duplicated logic circuit and a non-duplicated logic circuit can be connected, and both can be used together. For this reason, it is possible to suppress an increase in circuit scale and power consumption more than necessary by duplicating only logic circuits that require high reliability and not duplicating other logic circuits. In addition, since an already designed logic circuit that is not duplicated can be used, existing design circuit assets can be utilized.
(Eighteenth embodiment)
FIG. 30 is a block diagram showing the configuration of the semiconductor integrated circuit of the eighteenth embodiment.

  As shown in FIG. 30, the semiconductor integrated circuit of the eighteenth embodiment includes a first logic circuit including a memory circuit FF0A, an arithmetic circuit L1A, an arithmetic circuit L2A, a memory circuit FF1A, and a memory circuit FF2A, a memory circuit FF0B, The second logic circuit including the arithmetic circuit L1B, the arithmetic circuit L2B, the memory circuit FF1B, and the memory circuit FF2B, and the comparison result of whether or not the output value of the memory circuit FF0A and the output value of the memory circuit FF0B match. The comparison circuit C0 that outputs, the comparison circuit C1 that outputs the comparison result of whether or not the output value of the storage circuit FF1A and the output value of the storage circuit FF1B match, the output value of the storage circuit FF2A, and the output of the storage circuit FF2B The comparison circuit C2 outputs a comparison result as to whether or not the output value matches. The first logic circuit and the second logic circuit have the same function.

  The output value of the memory circuit FF0A is input to the arithmetic circuits L1A and L2A, the output value of the arithmetic circuit L1A is input to the memory circuit FF1A, and the output value of the arithmetic circuit L2A is input to the memory circuit FF2A. The output value of the memory circuit FF2A is input to the arithmetic circuit L1A.

  The output value of the memory circuit FF0B is input to the arithmetic circuits L1B and L2B, the output value of the arithmetic circuit L1B is input to the memory circuit FF1B, and the output value of the arithmetic circuit L2B is input to the memory circuit FF2B. The output value of the memory circuit FF2B is input to the arithmetic circuit L1B.

  The output values of the storage circuits FF0A and FF0B are input to the comparison circuit C0, the output values of the storage circuits FF1A and FF1B are input to the comparison circuit C1, and the output values of the storage circuits FF2A and FF2B are input to the comparison circuit C2.

  In the semiconductor integrated circuit of the eighteenth embodiment, the clock signal CKA is supplied to the memory circuit FF0A, the clock signal CKA ′ is supplied to the memory circuit FF1A, and the clock signal CKA ″ is supplied to the memory circuit FF2A. Further, the clock signal CKB is supplied to the memory circuit FF0B, the clock signal CKB ′ is supplied to the memory circuit FF1B, and the clock signal CKB ″ is supplied to the memory circuit FF2B.

  The semiconductor integrated circuit according to the eighteenth embodiment has two paths, that is, a case where the arithmetic processing by the arithmetic circuit L2A is executed before execution of the arithmetic processing by the arithmetic circuit L1A and a case where the arithmetic processing is not executed. Further, the semiconductor integrated circuit according to the eighteenth embodiment has two paths, that is, the case where the arithmetic processing by the arithmetic circuit L2B is executed before the arithmetic processing by the arithmetic circuit L1B and the case where the arithmetic processing is not executed.

  FIG. 31 is a timing chart showing the operation of the semiconductor integrated circuit of the eighteenth embodiment.

  As shown in FIG. 31, the clock signal CKA used in this embodiment is a signal that repeats the first period T1A, the second period T2A, and the third period T3A, and the clock signal CKA ′ is the first period T1A ′. , A signal that repeats the second period T2A ′ and the third period T3A ′, and the clock signal CKA ″ has the first period T1A ″, the second period T2A ″, and the third period T3A ″. It is a repeating signal.

  The clock signal CKB is a signal that repeats the first cycle T1B, the second cycle T2B, and the third cycle T3B, and the clock signal CKB ′ is the first cycle T1B ′, the second cycle T2B ′, and the third cycle. The clock signal CKB ″ is a signal that repeats the first cycle T1B ″, the second cycle T2B ″, and the third cycle T3B ″.

  Here, when the condition of T1A <T1A ′ is satisfied, it is possible to detect a delay decreasing fault occurring in the path including the memory circuit FF0A, the arithmetic circuit L1A, and the memory circuit FF1A, and T1A <T1A ″. At this time, it is possible to detect a delay-decreasing fault occurring in a path including the memory circuit FF0A, the arithmetic circuit L2A, and the memory circuit FF2A.

  In addition, when the condition of T1A ″ + T2A ″ <T1A + T2A is satisfied, it is possible to detect a delay decreasing fault occurring in the path including the memory circuit FF2A, the arithmetic circuit L1A, and the memory circuit FF1A.

  Although not illustrated in FIG. 31, the semiconductor integrated circuit of the eighteenth embodiment includes the memory circuit FF0B, the arithmetic circuit L1B, and the memory circuit FF1B when the conditions of T1B <T1B ′ and T1B <T1B ″ are satisfied. It is possible to detect a delay decreasing fault occurring in the path and the path including the memory circuit FF0B, the arithmetic circuit L2B, and the memory circuit FF2B.

In addition, when the condition of T1B ″ + T2B ″ <T1B + T2B is satisfied, it is possible to detect a delay-decreasing fault occurring in the path including the memory circuit FF2B, the arithmetic circuit L1B, and the memory circuit FF1B.
(Nineteenth embodiment)
FIG. 32 is a block diagram showing the configuration of the semiconductor integrated circuit of the nineteenth embodiment.

  As shown in FIG. 32, the semiconductor integrated circuit of the nineteenth embodiment has a clock generation circuit CG and a clock control circuit CC in addition to the semiconductor integrated circuit D shown in the first to eighteenth embodiments. It is.

  The clock control circuit CC refers to the comparison result of the output values of two storage circuits having the same positional relationship among the two logic circuits included in the semiconductor integrated circuit D, that is, the output value of the comparison circuit or the comparison storage circuit, A control signal for controlling the clock generation circuit CG is generated based on the output value.

  The clock generation circuit CG generates a plurality of clock signals CKA, CKA ′, CKB, and CKB ′ having different periods and / or phases from the external clock signal CK. The cycle and phase of the clock signals CKA, CKA ', CKB, and CKB' generated by the clock generation circuit CG are changed according to the control signal output from the clock control circuit CC.

  The clock control circuit CC refers to the output value of the comparison circuit or the comparison storage circuit during and / or before the operation of the semiconductor integrated circuit D. When the output value indicates “mismatch” between the outputs of the two logic circuits, it is determined that the semiconductor integrated circuit D is malfunctioning, and the various conditions shown in the first to eighteenth embodiments. The cause is determined based on the above. Then, a control signal for increasing the period of the plurality of clock signals and / or reducing the phase difference between the plurality of clock signals so as to avoid the malfunction is output to the clock generation circuit CG.

  The clock generation circuit CG changes the period and / or phase of the clock signals CKA, CKA ′, CKB, and CKB ′ according to the control signal output from the clock control circuit CC.

  The clock control circuit CC and the clock generation circuit CG can be realized by, for example, an LSI including various logic gate circuits, a storage circuit, an arithmetic circuit, etc., or a CPU that executes processing according to a program. A plurality of clock signals having different periods and phases can be generated by referring to the non-patent document 2 and the like.

According to the semiconductor integrated circuit of this embodiment, the period and / or phase of the clock signals CKA, CKA ′, CKB, and CKB ′ are changed according to the output value of the comparison circuit or the comparison storage circuit included in the semiconductor integrated circuit D. Thus, malfunction of the semiconductor integrated circuit D can be avoided.
(20th embodiment)
FIG. 33A is a block diagram showing the configuration of the semiconductor integrated circuit of the twentieth embodiment.

  As shown in FIG. 33A, the semiconductor integrated circuit of the twentieth embodiment has a power supply control circuit PM in addition to the semiconductor integrated circuit shown in the nineteenth embodiment.

  The semiconductor integrated circuit D is the semiconductor integrated circuit shown in the first to eighteenth embodiments, and the configurations and operations of the clock control circuit CC and the clock generation circuit CG are the same as those of the nineteenth embodiment. .

  The power supply control circuit PM is a power supply device that supplies a required power supply voltage to the semiconductor integrated circuit D, and changes the power supply voltage supplied to the semiconductor integrated circuit D in accordance with a control signal output from the clock control circuit CC.

The clock control circuit CC refers to the output value of the comparison circuit or comparison memory circuit during and / or before the operation of the semiconductor integrated circuit D, as in the nineteenth embodiment. When the output value indicates “mismatch” between the outputs of the two logic circuits, it is determined that the semiconductor integrated circuit D is malfunctioning, and the various conditions shown in the first to eighteenth embodiments. The cause is determined based on the above. When it is determined that the cause of the malfunction is a setup violation, that is, an increase in the delay time of the arithmetic circuit, the power supply voltage supplied to the semiconductor integrated circuit D is increased by the power supply control circuit PM to increase the circuit speed.
On the other hand, when it is determined that the cause of the malfunction is a violation of hold, that is, a reduction in the delay time of the arithmetic circuit, the power supply voltage supplied to the semiconductor integrated circuit D is lowered by the power supply control circuit PM to reduce the circuit speed.

  FIG. 34 is a flowchart showing the processing procedure of the clock control circuit provided in the semiconductor integrated circuit of the twentieth embodiment.

  As shown in FIG. 34, the clock control circuit CC of the present embodiment first sets the period and phase of each clock signal generated by the clock generation circuit CG. In the clock control circuit CG, even if the output value of the comparison circuit or the comparison memory circuit indicates “mismatch”, a range (maximum of occurrence of “mismatch”) that can be accepted as the semiconductor integrated circuit D (hereinafter referred to as mismatch probability) (maximum) Value and minimum value) are set in advance (step A1).

  When the semiconductor integrated circuit D starts operating, the clock control circuit CC calculates a mismatch probability during operation, and determines whether or not the mismatch probability is within a preset allowable range (step A2). . When the calculated mismatch probability is within an allowable range set in advance, the clock control circuit CC executes the process of step A2 again after a predetermined time has elapsed.

  When the calculated mismatch probability is outside the preset allowable range, the clock control circuit CC determines whether or not the mismatch probability is greater than the maximum value of the preset allowable range (step A3). .

  When the mismatch probability is larger than the preset maximum value of the allowable range, the clock control circuit CC determines that a malfunction has occurred because the circuit speed is low, and supplies the semiconductor integrated circuit D by the power supply control circuit PM. The power supply voltage is increased to increase the circuit speed (step A4).

  On the other hand, when the calculated mismatch probability is smaller than the minimum value of the preset allowable range, the clock control circuit CC determines that the circuit speed can be reduced, and the power supply control circuit PM performs the semiconductor integrated circuit D. The circuit speed is decreased by lowering the power supply voltage supplied to (step A5). And it returns to the process of step A2 and repeats the process of step A2 to A5.

  According to the semiconductor integrated circuit of this embodiment, it is possible to avoid the malfunction by changing the power supply voltage supplied to the semiconductor integrated circuit D according to the cause of the malfunction, and tolerate the semiconductor integrated circuit D. Since the power supply voltage can be lowered within the required range, the power consumption can be reduced while maintaining the circuit speed within the required range.

  In this embodiment, a configuration example in which the power supply control circuit PM is provided inside the semiconductor integrated circuit is shown, but the power supply control circuit PM may be provided independently outside the semiconductor integrated circuit. In this case, the power supply control circuit PM receives the control signal generated by the clock control circuit CC according to the output value of the comparison circuit or the comparison storage circuit, and changes the power supply voltage supplied to the semiconductor integrated circuit D according to the control signal do it.

  In the present embodiment, an example is shown in which the circuit speed is controlled by changing the power supply voltage supplied to the semiconductor integrated circuit D in accordance with the output value of the comparison circuit or the comparison storage circuit. If the circuit performance can be changed, the configuration is not limited to changing the power supply voltage.

  For example, as shown in FIG. 33B, the semiconductor integrated circuit of this embodiment includes a temperature control device TC for controlling the ambient temperature of the semiconductor integrated circuit D in accordance with the output value of the comparison circuit or the comparison storage circuit. Also good.

  In this case, the clock control circuit CC determines that the semiconductor integrated circuit D is malfunctioning in the same manner as described above when the output value of the comparison circuit or the comparison storage circuit indicates “mismatch” between the outputs of the two logic circuits. And determine the cause.

If it is determined that the cause of the malfunction is a setup violation, that is, an increase in the delay time of the arithmetic circuit, the ambient temperature of the semiconductor integrated circuit D is lowered by the temperature control device TC to improve the circuit performance. If it is determined that this is a violation, that is, the delay time of the arithmetic circuit is reduced, the ambient temperature of the semiconductor integrated circuit D may be raised by the temperature control device TC to lower the circuit performance. For the temperature control device TC, for example, a temperature control element such as a Peltier element, a heater, a heat sink, or the like can be used.
(21st embodiment)
FIG. 35 is a block diagram showing the configuration of the semiconductor integrated circuit of the twenty-first embodiment.

  As shown in FIG. 35, the semiconductor integrated circuit of the twenty-first embodiment has a configuration including a nonvolatile memory MEM in addition to the semiconductor integrated circuit of the twentieth embodiment shown in FIG. 33A. The semiconductor integrated circuit D is the semiconductor integrated circuit shown in the first to eighteenth embodiments, and the configurations and operations of the clock control circuit CC, the clock generation circuit CG, and the power supply control circuit PM are the nineteenth embodiment and the twentieth embodiment. This is the same as the semiconductor integrated circuit shown in the embodiment.

  The nonvolatile memory MEM is connected to the clock control circuit CC, and stores control instructions (control contents) for the clock generation circuit CG and the power supply control circuit PM executed by the clock control circuit CC.

The clock control circuit CC stores the control content in the nonvolatile memory MEM during operation and / or before the operation is stopped, and reads the control content stored in the nonvolatile memory MEM before or during the next operation. The clock generation circuit CG and the power supply control circuit PM are controlled according to the contents. By saving the control contents in this way, the clock control circuit CC can generate a clock signal under the same conditions as before the operation stop.
(Twenty-second embodiment)
FIG. 36 is a block diagram showing the configuration of the semiconductor integrated circuit of the twenty-second embodiment.

  When the semiconductor integrated circuits shown in the first to eighteenth embodiments are operated in a situation where high reliability is not required, it is not always necessary to operate both of the duplicated logic circuits.

  The twenty-second embodiment is an example in which the supply of the clock signal and the power supply voltage to one of the two logic circuits provided in the semiconductor integrated circuit D is stopped. The configuration of the semiconductor integrated circuit of this embodiment is the same as that of the twentieth embodiment shown in FIGS. 33A and 33B and the twenty-first embodiment shown in FIG.

  In FIG. 36, a plurality of memory circuits and arithmetic circuits included in each logic circuit are schematically shown by two memory circuits and one arithmetic circuit.

  As shown in FIG. 36, in the semiconductor integrated circuit of the twenty-second embodiment, the clock signals CKA and CKA ′ supplied from the clock generation circuit CG to the memory circuits FF0A and FF1A are stopped and the power supply is controlled by the clock control circuit CC. The power supply supplied from the control circuit PM to the memory circuits FF0A and FF1A and the arithmetic circuit L1A is stopped. In this embodiment, the clock signal and the power supply voltage are stopped, but only one of the clock signal and the power supply voltage may be stopped.

  As in this embodiment, when the clock signal for one of the two logic circuits included in the semiconductor integrated circuit D is stopped, the operation of the memory circuit and the arithmetic circuit included in the logic circuit is stopped. The current consumption of the integrated circuit D can be reduced.

In addition, since the clock signal to the logic circuit is stopped and the power supply voltage to the logic circuit is stopped, the current consumption in the stationary state (the operation is stopped) of the memory circuit and the arithmetic circuit is eliminated. The power consumption of D can be further reduced.
(23rd embodiment)
FIG. 37 is a flowchart showing the test procedure of the semiconductor integrated circuit of the 23rd embodiment.

  The twenty-third embodiment shows an example of a test method for determining whether the setup time and hold time of the semiconductor integrated circuit shown in the nineteenth to twenty-second embodiments satisfy a predetermined specification value.

  As shown in FIG. 37, in this embodiment, the clock control circuit CC shown in the nineteenth embodiment to the twenty-second embodiment is first used to satisfy the specification value of the setup time of the semiconductor integrated circuit to be tested. The signal cycle difference (for example, the difference between the first cycle T1A and the second cycle T2A of the clock signal CKA shown in FIG. 4) is set to a required value. Further, the clock control circuit CC causes the clock signal phase difference (for example, the first cycle T1A of the clock signal CKA shown in FIG. 4 and the clock so as to satisfy the hold time specification value of the semiconductor integrated circuit to be tested). The difference between the signal CKA ′ and the first period T1A ′ is set to a required value (step B1).

  Under this condition, an arbitrary test vector of test patterns created in advance is input to the semiconductor integrated circuit to be tested, and the output value of the comparison circuit or comparison storage circuit is observed by the clock control circuit CC ( Step B2).

  Here, when a value indicating “mismatch” is generated in the output value of the comparison circuit or the comparison storage circuit, the clock control circuit CC causes the malfunction based on the various conditions shown in the first to eighteenth embodiments. Is a setup violation (setup error) (step B3). If the cause is a setup violation, that is, an increase in the delay time of the arithmetic circuit, it can be determined that the semiconductor integrated circuit to be tested does not satisfy the setup time specification value.

  Next, the clock control circuit CC determines whether or not the cause of the malfunction is a hold violation (hold error) based on the various conditions shown in the first to eighteenth embodiments (step B4). If the cause is a hold violation, that is, a decrease in the delay time of the arithmetic circuit, it can be determined that the semiconductor integrated circuit to be tested does not satisfy the hold time specification value.

  When the value indicating “mismatch” does not occur in the output value of the comparison circuit or the comparison storage circuit, the clock control circuit CC determines whether or not the processing for all the test vectors included in the previously created test pattern has been performed. (Step B5). When the processing for all the test vectors is not performed, the processing returns to step B2 and the processing of steps B2 to B5 is repeated.

  When the processing for all test vectors is completed and no value indicating “mismatch” has occurred for all test vector inputs, the semiconductor integrated circuit under test has a setup time specification value and a hold time specification value. It can be determined that each value is satisfied.

  In general, when testing the setup time and hold time of a semiconductor integrated circuit using a dedicated test device, an expensive test device capable of finely setting the cycle and phase of a clock supplied to the semiconductor integrated circuit is required. According to the test method shown in this embodiment, the cycle and phase of the clock signal can be changed using the clock control circuit CC and the clock generation circuit CG provided in advance in the semiconductor integrated circuit. It can be determined whether or not the integrated circuit satisfies a required setup time and hold time.

  Normally, in a semiconductor integrated circuit that does not operate with a plurality of clock signals, the phase difference between the clock signals cannot be controlled, so that the hold time cannot be tested. On the other hand, in the semiconductor integrated circuit of this embodiment, the phase difference between a plurality of clock signals can be controlled, so that the hold time can be tested.

The processing shown in FIG. 37 may be executed by setting the power supply voltage supplied to the semiconductor integrated circuit D by the power supply control circuit PM shown in FIG. 33A, for example, to the minimum voltage or the maximum voltage within the guaranteed operation range. Alternatively, the temperature control device TC shown in FIG. 33B may be executed by setting the ambient temperature of the semiconductor integrated circuit D to the lowest temperature or the highest temperature within the guaranteed operating range. As described above, if the semiconductor integrated circuit D is tested by changing the power supply voltage supplied to the semiconductor integrated circuit D and the ambient temperature of the semiconductor integrated circuit D, the non-test target semiconductor integrated circuit operates at the power supply voltage and temperature. Whether or not to operate within the guaranteed range can also be determined.
(24th embodiment)
FIG. 38 is a flowchart showing the test procedure of the semiconductor integrated circuit of the twenty-fourth embodiment.

  The twenty-fourth embodiment shows an example of a test method for obtaining the setup time and hold time of the semiconductor integrated circuit shown in the nineteenth to twenty-second embodiments.

  As shown in FIG. 38, in this embodiment, first, the clock control circuit CC shown in the nineteenth embodiment to the twenty-third embodiment uses the clock signal cycle difference (for example, the first clock signal CKA shown in FIG. 4). Difference between the period T1A and the second period T2A) and the phase difference between the clock signals (for example, the difference between the first period T1A of the clock signal CKA shown in FIG. 4 and the first period T1A ′ of the clock signal CKA ′). ) Are set to temporary values (step C1). Here, the clock signal period difference is for measuring the setup time of the semiconductor integrated circuit to be tested, and the clock signal phase difference is for measuring the hold time of the semiconductor integrated circuit to be tested. belongs to.

  Under this condition, an arbitrary test vector of test patterns created in advance is input to the semiconductor integrated circuit to be tested, and the output value of the comparison circuit or comparison storage circuit is observed by the clock control circuit CC ( Step C2).

  Here, when a value indicating “mismatch” is generated in the output value of the comparison circuit or the comparison storage circuit, the clock control circuit CC may cause malfunction due to various conditions shown in the first to eighteenth embodiments. It is determined whether or not it is a setup violation (setup error) (step C3). When the cause is a setup violation, that is, an increase in the delay time of the arithmetic circuit, it can be determined that a setup violation occurs with a clock signal having a temporarily set period difference. In that case, the clock control circuit CC reduces the period difference of the plurality of clock signals supplied to the semiconductor integrated circuit to be tested (step C6), returns to the process of step C2, and repeats the processes of steps C2 to C3.

  When the cause of the malfunction is not a setup violation, the clock control circuit CC determines whether the cause of the malfunction is a hold violation (hold error) from the various conditions shown in the first to eighteenth embodiments ( Step C4). When the cause is a hold violation, that is, a reduction in the delay time of the arithmetic circuit, it can be determined that a hold violation occurs in a clock signal having a temporarily set phase difference. In that case, the clock control circuit CC reduces the phase difference of the plurality of clock signals supplied to the semiconductor integrated circuit to be tested (step C7), returns to step C2, and repeats the processing of steps C2 to C4.

  When a value indicating “mismatch” does not occur in the output value of the comparison circuit or the comparison storage circuit, the clock control circuit CC determines whether or not the determination process has been performed for all the test vectors included in the test pattern created in advance. Determine (step C5). If determination processing for all test vectors has not been performed, the process returns to step C2 and the processes of steps C2 to C5 are repeated.

  When the processing of steps C2 to C5 is performed on all test vectors, the clock control circuit CC has a predetermined accuracy (hereinafter referred to as time accuracy) for the period of each clock signal generated by the clock generation circuit CG. Is determined (step C8).

  When each clock signal generated by the clock generation circuit CG satisfies a predetermined time accuracy, the clock control circuit CC ends the process. At this time, the period difference between the plurality of clock signals supplied to the semiconductor integrated circuit under test is the setup time of the semiconductor integrated circuit under test, and the phase difference between the clock signals is the semiconductor integrated circuit under test. Hold time.

  When each clock signal generated by the clock generation circuit CG does not satisfy the predetermined time accuracy, the clock control circuit CC increases the period difference between the plurality of clock signals supplied to the semiconductor integrated circuit to be tested. (Step C9). Further, the clock control circuit CC increases the phase difference between the plurality of clock signals supplied to the semiconductor integrated circuit to be tested (step C10), returns to step C2, and repeats the processing of steps C2 to C10.

  According to the test method shown in the present embodiment, the clock signal cycle and phase can be changed using the clock control circuit CC and the clock generation circuit CG included in the semiconductor integrated circuit. The setup time and hold time of an integrated circuit can be measured.

  Normally, in a semiconductor integrated circuit that does not operate with a plurality of clock signals, the phase difference between the clock signals cannot be controlled, so that the hold time cannot be tested. On the other hand, in the semiconductor integrated circuit of this embodiment, the phase difference between a plurality of clock signals can be controlled, so that the hold time can be tested.

  In the present embodiment, as in the twenty-third embodiment, the processing shown in FIG. 38 is performed within the guaranteed operating range for the power supply voltage supplied to the semiconductor integrated circuit D by the power supply control circuit PM shown in FIG. 33A, for example. The minimum voltage or the maximum voltage may be set, and the temperature control device TC shown in FIG. 33B may be used to set the ambient temperature of the semiconductor integrated circuit D to the minimum or maximum temperature within the guaranteed operating range. May be. As described above, if the semiconductor integrated circuit D is tested by changing the power supply voltage supplied to the semiconductor integrated circuit D and the ambient temperature of the semiconductor integrated circuit D, the non-test target semiconductor integrated circuit operates at the power supply voltage and temperature. Whether or not to operate within the guaranteed range can also be determined.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims priority based on Japanese Patent Application No. 2008-199483 filed on Aug. 1, 2008 and Japanese Patent Application No. 2009-027420 filed on Feb. 9, 2009. Get everything here.

Claims (53)

A first arithmetic circuit that executes predetermined arithmetic processing, a first memory circuit that is connected to an input of the first arithmetic circuit and holds and outputs an input value in synchronization with a first clock signal; and A first logic circuit including a second memory circuit connected to an output of the first arithmetic circuit and holding and outputting an input value in synchronization with a second clock signal;
A second arithmetic circuit that executes the same arithmetic processing as the first arithmetic circuit, and holds and outputs an input value in synchronization with a third clock signal connected to the input of the second arithmetic circuit. A second logic circuit comprising a third memory circuit and a fourth memory circuit connected to the output of the second arithmetic circuit and holding and outputting an input value in synchronization with a fourth clock signal When,
A first comparison circuit that outputs a comparison result as to whether or not the output value of the second storage circuit and the output value of the fourth storage circuit match;
Have
The first, second, third, and fourth clock signals are signals that alternately repeat a first period and a second period, and the start of each of the first periods coincides, and The end of the second cycle coincides,
At least one of the first, second, third, and fourth clock signals has a length different from the first period and the second period, and at least one of the other clock signals and Semiconductor integrated circuit with different signal patterns.   2. The semiconductor integrated circuit according to claim 1, further comprising a first comparison memory circuit that holds and outputs an output value of the first comparison circuit in synchronization with a predetermined clock signal.   3. The semiconductor integrated circuit according to claim 2, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time to the first comparison memory circuit as a clock signal.   3. The semiconductor integrated circuit according to claim 2, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the first comparison memory circuit as a clock signal.   2. The semiconductor integrated circuit according to claim 1, further comprising: a second comparison circuit that outputs a comparison result as to whether or not an output value of the first storage circuit matches an output value of the third storage circuit. A first comparison storage circuit that holds and outputs an output value of the first comparison circuit in synchronization with a predetermined clock signal;
A second comparison storage circuit that holds and outputs an output value of the second comparison circuit in synchronization with a predetermined clock signal;
The semiconductor integrated circuit according to claim 5, further comprising:   And a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time to the first comparison memory circuit and the second comparison memory circuit as a clock signal. Item 7. The semiconductor integrated circuit according to Item 6.   7. The inverter circuit according to claim 6, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the first comparison memory circuit and the second comparison memory circuit as a clock signal. Semiconductor integrated circuit. A first logic circuit including a plurality of first arithmetic circuits that execute predetermined arithmetic processing and a plurality of first memory circuits that are alternately connected to the plurality of first arithmetic circuits;
A second logic circuit including a second arithmetic circuit that executes the same arithmetic processing as the first arithmetic circuit and a plurality of second memory circuits that are alternately connected to the plurality of second arithmetic circuits; ,
A plurality of comparison circuits each outputting a comparison result as to whether or not the output value of the first storage circuit and the output value of the second storage circuit match;
Have
The first clock signal and the second clock signal are alternately supplied to the plurality of first memory circuits,
A third clock signal and a fourth clock signal are alternately supplied to the plurality of second memory circuits,
The first, second, third, and fourth clock signals are signals that alternately repeat a first period and a second period, and the start of each of the first periods coincides, and The end of the second cycle coincides,
At least one of the first, second, third, and fourth clock signals has a length different from the first period and the second period, and at least one of the other clock signals and Semiconductor integrated circuit with different signal patterns.   10. The semiconductor integrated circuit according to claim 9, further comprising a plurality of first comparison memory circuits that hold and output the output value of the comparison circuit in synchronization with a predetermined clock signal.   11. The semiconductor integrated circuit according to claim 10, wherein a scan path is formed by connecting an output of the first comparison storage circuit to an input of a first comparison storage circuit in the next stage.   11. The semiconductor integrated circuit according to claim 10, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time to the first comparison memory circuit as a clock signal.   The semiconductor integrated circuit according to claim 10, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the first comparison memory circuit as a clock signal.   The semiconductor integrated circuit according to claim 9, further comprising a multi-input comparison circuit that outputs a signal indicating a mismatch when at least one output value of the plurality of comparison circuits does not match another output value.   15. The semiconductor integrated circuit according to claim 14, further comprising a second comparison memory circuit that holds an output value of the multi-input comparison circuit.   16. The semiconductor integrated circuit according to claim 15, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time to the second comparison memory circuit as a clock signal.   16. The semiconductor integrated circuit according to claim 15, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the second comparison memory circuit as a clock signal. A first failure determination circuit to which failure diagnosis information, which is information for designating the output value of the first comparison circuit, the failure diagnosis target, and the type of failure cause, is input;
A first failure determination storage circuit that holds and outputs an output value of the first failure determination circuit in synchronization with a predetermined clock signal;
The semiconductor integrated circuit according to claim 1, comprising:   19. The semiconductor integrated circuit according to claim 18, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time to the first failure determination storage circuit as a clock signal.   19. The semiconductor integrated circuit according to claim 18, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the first failure determination storage circuit as a clock signal. A second comparison circuit that outputs a comparison result as to whether or not the output value of the first storage circuit and the output value of the third storage circuit match;
A second failure determination circuit to which a failure diagnosis information input, which is information for designating the output value of the second comparison circuit, the failure diagnosis target, and the type of failure cause, is input;
A second failure determination storage circuit that holds and outputs an output value of the second failure determination circuit in synchronization with a predetermined clock signal;
The semiconductor integrated circuit according to claim 18, further comprising:   The semiconductor integrated circuit according to claim 21, wherein an output value of the second failure determination storage circuit is input to the first failure determination circuit.   According to the output values of the first failure determination storage circuit and the second failure determination storage circuit, the output value of the first arithmetic circuit is output to the second storage circuit and the output of the second arithmetic circuit A value is output to the fourth memory circuit, an output value of the first arithmetic circuit is output to the second memory circuit and the fourth memory circuit, or an output value of the second arithmetic circuit is output. 22. The semiconductor integrated circuit according to claim 21, further comprising a selection circuit that outputs to the second memory circuit and the fourth memory circuit.   A delay circuit for supplying a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time as a clock signal to the first failure determination storage circuit and the second failure determination storage circuit; The semiconductor integrated circuit according to claim 21.   22. An inverting circuit for supplying a signal obtained by inverting the first, second, third, or fourth clock signal to the first failure determination storage circuit and the second failure determination storage circuit as a clock signal. The semiconductor integrated circuit as described. A failure determination circuit to which failure diagnosis information, which is information for designating the output value of the comparison circuit, the failure diagnosis target, and the type of failure cause, is input;
A failure determination storage circuit that holds and outputs an output value of the failure determination circuit in synchronization with a predetermined clock signal;
The semiconductor integrated circuit according to claim 9, further comprising:   27. The semiconductor integrated circuit according to claim 26, wherein a scan path is formed by connecting an output of the failure determination storage circuit to an input of a failure determination storage circuit in the next stage.   27. The semiconductor integrated circuit according to claim 26, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time as a clock signal to the failure determination storage circuit.   27. The semiconductor integrated circuit according to claim 26, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the failure determination storage circuit as a clock signal.   27. The semiconductor integrated circuit according to claim 26, wherein an output value of a next-stage failure determination storage circuit is input to the failure determination circuit.   According to the output value of the failure determination storage circuit, the output value of the first arithmetic circuit is output to the first storage circuit and the output value of the second arithmetic circuit is output to the second storage circuit. The output value of the first arithmetic circuit is output to the first storage circuit and the second storage circuit, or the output value of the second arithmetic circuit is output to the first storage circuit and the second storage circuit. 27. The semiconductor integrated circuit according to claim 26, further comprising a selection circuit for outputting to the memory circuit.   27. The semiconductor integrated circuit according to claim 26, further comprising a delay circuit that supplies a signal obtained by delaying the first, second, third, or fourth clock signal by a predetermined time as a clock signal to the failure determination storage circuit.   27. The semiconductor integrated circuit according to claim 26, further comprising an inverting circuit that supplies a signal obtained by inverting the first, second, third, or fourth clock signal to the failure determination storage circuit as a clock signal. The first cycle of the first clock signal is greater than or equal to the first cycle of the second clock signal, and the first cycle of the third clock signal is the fourth clock. The semiconductor integrated circuit according to any one of claims 1 to 33, which is equal to or longer than the first period of the signal. The first cycle of the first clock signal is longer than the first cycle of the second clock signal, and the first cycle of the third clock signal is the fourth clock. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is longer than the first period of the signal. The first period of the first clock signal is longer than the first period of the third clock signal, and the first period of the second clock signal is the fourth clock 36. The semiconductor integrated circuit according to claim 34 or 35, which is longer than the first period of the signal. The first cycle of the third clock signal is longer than the first cycle of the first clock signal, and the first cycle of the fourth clock signal is the second clock. 36. The semiconductor integrated circuit according to claim 34 or 35, which is longer than the first period of the signal.   34. The semiconductor integrated circuit according to claim 1, wherein the first, second, and third clock signals are the same.   34. The semiconductor integrated circuit according to claim 1, wherein the first and second clock signals are the same, and the third and fourth clock signals are the same.   40. The semiconductor integrated circuit according to claim 38, wherein the first cycle and the second cycle of the first clock signal are different, and the first cycle and the second cycle of the fourth clock signal are different.   41. The semiconductor integrated circuit according to claim 40, wherein the first period of the first clock signal is shorter than the second period, and the first period of the fourth clock signal is longer than the second period. circuit.   42. The semiconductor integrated circuit according to claim 40, wherein the first period of the first clock signal is equal to the second period of the fourth clock signal. A clock generation circuit for generating the first, second, third and fourth clock signals;
In accordance with the comparison result of the outputs of the first logic circuit and the second logic circuit, the clock generation circuit has at least one of the period or phase of the first, second, third and fourth clock signals. A clock control circuit for changing one of them,
43. The semiconductor integrated circuit according to claim 1, further comprising: A power control circuit for supplying a power supply voltage to the first logic circuit and the second logic circuit in a changeable manner;
The clock control circuit includes:
The power supply control circuit is caused to change a power supply voltage supplied to the first logic circuit and the second logic circuit in accordance with a comparison result of outputs of the first logic circuit and the second logic circuit. Item 44. The semiconductor integrated circuit according to Item 43. A temperature control device for changing an ambient temperature of the first logic circuit and the second logic circuit;
The clock control circuit includes:
In accordance with the comparison result of the outputs of the first logic circuit and the second logic circuit, the temperature controller is provided with the ambient temperature of at least one of the first logic circuit or the second logic circuit. 45. The semiconductor integrated circuit according to claim 43 or 44, which is changed.   46. The semiconductor integrated circuit according to any one of claims 43 to 45, further comprising a non-volatile memory for holding control contents by the clock control circuit. The clock control circuit includes:
47. The semiconductor integrated circuit according to claim 46, wherein the control content is stored in the nonvolatile memory during operation or before stopping, and the control content stored in the nonvolatile memory is read before or during the next operation. The clock control circuit includes:
44. The semiconductor integrated circuit according to claim 43, wherein the clock generation circuit stops a clock signal supplied to either the first logic circuit or the second logic circuit. The clock control circuit includes:
45. The semiconductor integrated circuit according to claim 44, wherein the power supply control circuit stops a power supply voltage supplied to either the first logic circuit or the second logic circuit. A test method for measuring a setup time and a hold time of a semiconductor integrated circuit according to any one of claims 43 to 49,
A plurality of clock signals having at least one of a period difference set in accordance with a specification value of a setup time of the semiconductor integrated circuit and a phase difference set in accordance with a specification value of a hold time of the semiconductor integrated circuit To the integrated circuit,
Observing a comparison result of outputs of the first logic circuit and the second logic circuit when a predetermined test pattern is input to the semiconductor integrated circuit;
Whether the semiconductor integrated circuit satisfies the set-up time specification value depending on whether the comparison results of the outputs of the first logic circuit and the second logic circuit match or do not match, or the semiconductor integrated circuit A test method for a semiconductor integrated circuit, which determines whether or not a circuit satisfies a specification value of the hold time. A test method for measuring a setup time and a hold time of a semiconductor integrated circuit according to any one of claims 43 to 49,
A first step of supplying a plurality of clock signals set to a predetermined period difference and a predetermined phase difference to the semiconductor integrated circuit;
A second step of observing a comparison result of outputs of the first logic circuit and the second logic circuit when a predetermined test pattern is input to the semiconductor integrated circuit;
When the comparison result of the outputs of the first logic circuit and the second logic circuit indicates a mismatch, a third difference for resetting the period difference or the phase difference of a plurality of clock signals supplied to the semiconductor integrated circuit Process,
The third step is repeated from the first step until the comparison results of the outputs of the first logic circuit and the second logic circuit match, and when the comparison results match, the period difference is A fourth step of determining the corresponding setup time and the hold time corresponding to the phase difference;
A method for testing a semiconductor integrated circuit comprising:   52. The method for testing a semiconductor integrated circuit according to claim 50 or 51, wherein a power supply voltage supplied to the semiconductor integrated circuit is set to a minimum voltage or a maximum voltage within an operation guarantee range of the semiconductor integrated circuit.   52. The test method for a semiconductor integrated circuit according to claim 50, wherein the ambient temperature of the semiconductor integrated circuit is set to a minimum temperature or a maximum temperature within an operation guarantee range of the semiconductor integrated circuit.

Images