JPWO2009090829A1 - Semiconductor memory device and data reading method in semiconductor memory device - Google Patents

Abstract

In the semiconductor memory device of the present invention, charge is accumulated or removed when data is written, and a cell current corresponding to the charge is read when the data is read, and normal data is stored in the memory cell 11. When the cell current corresponding to the normal data is read and the cell current corresponding to the normal data is read out, the write circuit 12 for writing the reference data to the memory cell 11 and the offset current subtractor for subtracting the offset current from the cell current corresponding to the normal data and outputting 14 and the cell current corresponding to the normal data and the reference data are sequentially read from the memory cell 11, the cell current corresponding to the reference data is set as the reference current, and the current output from the offset current subtracter 14 is compared with the reference current. And a current comparator 13 that determines the value of the normal data.

Description

  The present invention relates to a semiconductor memory device having a memory cell in which charge is accumulated or removed according to a data value when data is written, and a cell current corresponding to the charge is read when data is read. The present invention relates to a data reading method.

  A DRAM (Dynamic Random Access Memory) memory cell widely used in the current semiconductor field is composed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor.

  Since this capacitive element occupies a major area in a DRAM, various capacitive elements have been developed in order to realize a reduction in area in a recent manufacturing process in which miniaturization advances.

  On the other hand, as shown in Non-Patent Document 1, a capacitor is removed by using an SOI (Silicon On Insulator) transistor in a memory cell to improve the area efficiency, and a 1T (Transistor) -DRAM. It is. The 1T-DRAM is characterized in that data is written by charges accumulated on the substrate of the SOI transistor.

  The 1T-DRAM will be described below.

  First, data writing in the 1T-DRAM will be described.

  When data “1” is written, the source of the SOI transistor is grounded and a high potential is applied to the drain. At this time, impact ionization occurs near the drain of the SOI transistor, and charges are accumulated on the substrate. In this way, the state in which charges are accumulated on the substrate is the state in which data “1” is written.

  When writing data ‘0’, the drain potential of the SOI transistor is made lower than the substrate potential, and the pn junction between the substrate and the drain is made a forward bias to remove the substrate charge. Thus, the state in which the charge is removed from the substrate is the state in which the data “0” is written.

  Next, data reading in the 1T-DRAM will be described.

  As described above, since data stored in the SOI transistor substrate changes due to data writing, the substrate potential changes. For this reason, the threshold voltage of the SOI transistor changes due to the substrate effect, and the value of the cell current corresponding to the read data changes when reading data from the SOI transistor. In the 1T-DRAM, it is determined whether the data value is ‘1’ or ‘0’ based on the magnitude of the cell current.

  There is a limitation on the change in the substrate potential of the SOI transistor due to data writing described above. The upper limit of the substrate potential is determined by the substrate potential when the pn junction between the substrate and the source is forward biased. On the other hand, the lower limit of the substrate potential is determined by the substrate potential when the pn junction between the substrate and the drain is forward biased.

When the voltage required to make the pn junction forward bias is V _F and the drain potential when writing data “0” is V _D (V _D <0), the variable range of the substrate potential V _B is V _D + V. It expressed as _F ≦ _{V B} ≦ _{V F.}

In this _case, the data '1' is written in the case of V B = _{V F,} data '0' is written in the case of _{V B = V D + V F} . In the SOI transistor, the voltage V _F required to make the pn junction forward bias is a value inherent to the silicon substrate, and is generally about 0.7V.

  In a 1T-DRAM, data having a value of “1” or “0” written in an SOI transistor that is a memory cell can be classified into two types depending on the application.

  One is normal data called so-called data written in an SOI transistor, which is a memory cell, for storing information.

  The other is reference data used to generate a reference voltage or reference current to be compared when determining the magnitude of the cell current corresponding to the normal data read from the SOI transistor.

  In the 1T-DRAM, one dummy cell (memory cell) in which reference data “1” is written and one dummy cell in which reference data “0” is written are prepared in order to generate a reference voltage or a reference current. Then, voltages or cell currents corresponding to the reference data ‘1’ and the reference data ‘0’ read from them are used as the reference voltage or reference current.

  In a 1T-DRAM that generates a reference voltage from reference data written in a dummy cell, in order to determine the magnitude of the cell current corresponding to the normal data read from the SOI transistor, the cell current corresponding to the normal data is a voltage. And compare with the reference voltage.

  In such a 1T-DRAM, variation in threshold voltage between SOI transistors due to miniaturization is a problem.

  When the threshold voltage varies, the voltage or cell current value corresponding to the normal data “1” and the normal data “0” varies between the SOI transistors, and the reference voltage or reference current value generated from the dummy cell is changed. Variation will also occur. As a result, the threshold voltage variation increases, and the voltage or cell current variation range corresponding to the normal data '1' or the normal data '0' overlaps the reference voltage or reference current variation range. Therefore, it is difficult to determine the value of normal data read from the memory cell.

  Therefore, in order to mitigate the influence of variation in threshold voltage between SOI transistors, Patent Document 1 describes a method using a plurality of dummy cells. In Patent Document 1, a plurality of dummy cells to which reference data ‘1’ and reference data ‘0’ are written are prepared, and a reference voltage is generated by taking an average value of voltages read from the dummy cells. As a result, the threshold voltage variation between the dummy cells is averaged and the reference voltage variation is reduced, so that it is easy to determine the value of the normal data read from the memory cell.

  However, when the threshold voltage variation between SOI transistors further increases and the range of voltage variation corresponding to normal data “1” and normal data “0” overlaps, it is described in Patent Document 1. Even if this method is used, it is impossible to determine the value of normal data.

  The same phenomenon is a problem also in a ferroelectric memory which is an example of a nonvolatile memory.

  As a method for removing the influence of threshold voltage variation between memory cells in a ferroelectric memory, Patent Document 2 discloses a method using a memory cell itself from which normal data is read as a memory cell for generating a reference voltage. Are listed. In this method, data is read twice from the same memory cell, and the voltage corresponding to the first read charge is regarded as the voltage corresponding to the normal data, which corresponds to the charge read for the second time. The reference voltage is obtained by adding the offset voltage to the voltage to be applied. Then, using the sense amplifier, the value of the normal data is determined by comparing the voltage corresponding to the normal data read in the first reading with the reference voltage.

  If this method is used, even if the range of variations in voltage corresponding to normal data '1' and normal data '0' overlaps due to manufacturing variations and changes over time in ferroelectric capacitors used as memory cells. Thus, it is possible to accurately determine whether the value of the normal data written in the ferroelectric capacitor element is “1” or “0” by removing the influence of the variation in the threshold voltage between the memory cells. .

  As described above, in the 1T-DRAM, when the variation in the threshold voltage between the SOI transistors increases, it is determined whether the value of the normal data written in the memory cell is “1” or “0”. The voltage margin will decrease.

  In general, the threshold voltage variation to be taken into account in the memory depends on the memory scale. If the standard deviation of the threshold voltage variation is σ, in a memory of about several tens of Kbits to several Mbits, the variation to be considered is about 4σ to 5σ. Therefore, in such a large-scale memory, the operation must be guaranteed for memory cells in which the threshold voltage varies by about 4σ to 5σ.

  Taking Non-Patent Document 1 as an example, the standard deviation σ of the threshold voltage variation between SOI transistors is about 30 mV. The voltage margin for discriminating “0” is only about 100 mV to 160 mV, and it cannot be said that a sufficient voltage margin is secured.

  In the future, as the miniaturization of 1T-DRAM progresses, the variation in threshold voltage between SOI transistors is expected to increase further than that of the current generation 1T-DRAM. Therefore, the voltage margin for determining the value of normal data read from the memory cell is further reduced from 100 mV to 160 mV, and it becomes more difficult to determine the value of normal data.

  In the method of generating a reference voltage using a plurality of dummy cells as in Patent Document 1, the variation of the reference voltage is an average of the variation of individual dummy cells. For this reason, it is easier to determine the value of the normal data as compared with the method using one dummy cell in which the reference data ‘1’ and the reference data ‘0’ are written one by one. However, if miniaturization progresses, the threshold voltage variation between SOI transistors increases, and the range of voltage variation corresponding to normal data '1' and normal data '0' overlaps, Patent Document 1 Even if the method is used, it is impossible to determine the read normal data value.

  The method of Patent Document 2 is a data reading method in a ferroelectric memory. In this method, in order to generate a reference voltage, an offset voltage is added to a voltage corresponding to reference data ‘1’ or reference data ‘0’ read in advance in the output unit of the reading circuit. This method is suitable for reading data with a voltage signal such as a ferroelectric memory, but is not suitable for reading data with a current signal.

  In 1T-DRAM, as described above, a cell current corresponding to normal data read from an SOI transistor, which is a memory cell, is converted into a voltage and compared with a reference voltage. Is read from the cell current, and data “1” and data “0” are discriminated based on the magnitude of the cell current. Therefore, this corresponds to a case where data is read with a current signal. Therefore, it is difficult to apply the method of Patent Document 2 to 1T-DRAM.

For this reason, in a semiconductor memory device that reads data using a current signal such as a cell current, even if the variation in threshold voltage between memory cells increases, the value of normal data read from the memory cell is “1”. There is a problem that it is necessary to accurately determine whether it is '0' or '0'.
JP 2006-65901 A JP 2005-259296 A Osawa, “An 18.5 ns 128 Mb SOI DRAM with a floating body cell”, ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2005

  An object of the present invention is to provide a semiconductor memory device and a data reading method in the semiconductor memory device that can solve the above-described problems.

In order to achieve the above object, a semiconductor memory device of the present invention provides:
A memory cell in which charge is stored or removed according to the value of the data when data is written, and a cell current corresponding to the charge is read when the data is read;
A write circuit for writing normal data to the memory cell, and writing a reference data to the memory cell after reading a cell current corresponding to the normal data;
An offset current subtracter that subtracts and outputs an offset current from a cell current corresponding to normal data read from the memory cell;
The cell currents corresponding to the normal data and the reference data are sequentially read from the memory cell, the cell current corresponding to the reference data is used as a reference current, and the current output from the offset current subtractor is used as the reference current. And a current comparator for determining the value of the normal data by comparison.

In order to achieve the above object, the data reading method of the present invention comprises:
A data read method performed by a semiconductor memory device having a memory cell in which charge is accumulated or removed according to the value of the data when data is written and cell current corresponding to the charge is read when the data is read There,
A first read step of reading a cell current corresponding to normal data written to the memory cell;
A subtraction step of subtracting an offset current from a cell current corresponding to the normal data;
A writing step of writing reference data to a memory cell from which a cell current corresponding to the normal data is read;
A second reading step of reading a cell current corresponding to the reference data written in the memory cell;
Determination of determining a value of the normal data by comparing a cell current corresponding to the reference data as a reference current and a current obtained by subtracting an offset current from the cell current corresponding to the normal data in the subtraction step with the reference current And a step.

  According to the semiconductor memory device of the present invention, in the write circuit, the reference data is written in the memory cell from which the cell current corresponding to the normal data is read, and in the current comparator, the reference data is read from the memory cell. In this configuration, the value of the normal data is determined by comparing the current obtained by subtracting the offset current from the cell current corresponding to the normal data with the reference current.

  As a result, the reference current used for determining whether the value of the normal data read from the memory cell is “1” or “0” is generated from the memory cell itself that has read the normal data. Can do.

  Therefore, even when the threshold voltage variation between the memory cells increases, the reference current is generated in each memory cell, so that the influence of the threshold voltage variation can be eliminated and the memory cell is read out. There is an effect that it is possible to accurately determine whether the value of the normal data is “1” or “0”.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the specific example 1 of the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the specific example 2 of the 3rd Embodiment of this invention. FIG. 6 is a circuit diagram illustrating a configuration of a circuit configuration example 1 of a specific example 2 illustrated in FIG. 5. FIG. 7 is a block diagram illustrating a configuration example of an offset voltage generator according to the circuit configuration example 1 illustrated in FIG. 6. It is a figure which shows the operation | movement waveform of the circuit structural example 1 shown in FIG. It is a figure explaining the principle of the circuit structural example 1 shown in FIG. FIG. 6 is a circuit diagram illustrating a configuration of a circuit configuration example 2 of the specific example 2 illustrated in FIG. 5. FIG. 6 is a circuit diagram illustrating a configuration of a circuit configuration example 3 of the specific example 2 illustrated in FIG. 5. FIG. 6 is a circuit diagram illustrating a configuration of a circuit configuration example 4 of the specific example 2 illustrated in FIG. 5. FIG. 13 is a block diagram illustrating a configuration example of an offset voltage generator according to the circuit configuration example 4 illustrated in FIG. 12.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device of this embodiment includes a memory cell 11, a write circuit 12, a current comparator 13, and an offset current subtracter 14.

  In the memory cell 11, charge is stored or removed according to the data value when data is written. The memory cell 11 reads a cell current corresponding to the charge when reading data. Therefore, it is possible to determine whether the value of the read data is ‘1’ or ‘0’ based on the magnitude of the cell current corresponding to the data read from the memory cell 11. A plurality of memory cells may exist.

  The write circuit 12 writes normal data to the memory cell 11. Further, when the cell current corresponding to the normal data written in the memory cell 11 is read, the write circuit 12 writes the reference data “0” in the memory cell 11 thereafter.

  The offset current subtracter 14 subtracts the offset current from the cell current corresponding to the normal data read from the memory cell 11 and outputs the result to the current comparator 13.

  The current comparator 13 sequentially reads the cell current corresponding to the normal data and the reference data “0” from the memory cell 11 and outputs the cell current corresponding to the reference data “0” as the reference current from the offset current subtractor 14. The value of normal data is determined by comparing the measured current with a reference current.

  The operation of the semiconductor memory device of the present invention will be described below.

  First, the current comparator 13 reads a cell current corresponding to normal data from the memory cell 11 via the offset current subtracter 14.

  Next, the offset current subtracter 14 subtracts the offset current from the cell current corresponding to the normal data read from the memory cell 11 and outputs the result to the current comparator 13.

  Next, the write circuit 12 writes the reference data “0” to the memory cell 11 from which the normal data has been read.

  Next, the current comparator 13 reads the cell current corresponding to the reference data “0” from the memory cell 11 and sets it as the reference current.

  Thereafter, the current comparator 13 determines the value of the normal data by comparing the current output from the offset current subtracter 14 with the reference current.

  Thereby, the current comparator 14 can determine whether the value of the normal data read from the memory cell 11 is ‘1’ or ‘0’.

  As described above, in the semiconductor memory device of this embodiment, the write circuit 12 writes the reference data “0” to the memory cell 11 from which the cell current corresponding to the normal data is read, and the current comparator 13 The cell current corresponding to the reference data “0” read from the memory cell 11 is used as the reference current, and the value obtained by subtracting the offset current from the cell current corresponding to the normal data is compared with the reference current to obtain the value of the normal data. It is the structure which determines.

  As a result, the reference current used to determine whether the value of the normal data read from the memory cell 11 is “1” or “0” is generated from the memory cell 11 itself that has read the normal data. can do.

  Therefore, even when the threshold voltage variation between the memory cells increases, the reference current is generated in each memory cell, so that the influence of the threshold voltage variation can be removed and read from the memory cell 11. In addition, it is possible to accurately determine whether the value of the normal data is “1” or “0”.

(Second Embodiment)
FIG. 2 is a block diagram showing the configuration of the semiconductor memory device according to the second embodiment of the present invention.

  As shown in FIG. 2, the semiconductor memory device of this embodiment includes a memory cell 21, a write circuit 22, a current selector 23, a current value storage circuit 24, an offset current subtractor 25, and a current comparator 26. And have.

  The present embodiment is different from the first embodiment in that the configuration includes a current selector 23 and a current value storage circuit 24.

  Note that the memory cell 21, the write circuit 22, the offset current subtractor 25, and the current comparator 26 are the memory cell 11 of the first embodiment shown in FIG. This corresponds to the write circuit 12, the offset current subtractor 14, and the current comparator 13.

  Data is written to and read from the memory cell 21 in the same manner as the memory cell 11 shown in FIG. A plurality of memory cells may exist.

  The write circuit 22 writes normal data to the memory cell 21. Further, when the cell current corresponding to the normal data written in the memory cell 21 is read, the write circuit 22 writes the reference data “0” in the memory cell 21 thereafter.

  The current selector 23 conducts the current value storage circuit 24 and the memory cell 21 when normal data is read from the memory cell 21. Further, the current selector 23 conducts the one input terminal of the current comparator 26 and the memory cell 21 when the reference data “0” is read from the memory cell 21. Further, the current selector 23 cuts off the current value storage circuit 24 and the current comparator 26 from the memory cell 21 when writing into the memory cell 21.

  The current value storage circuit 24 stores a cell current corresponding to normal data read from the memory cell 21.

  The offset current subtracter 25 subtracts the offset current from the cell current corresponding to the normal data read from the memory cell 21 stored in the current value storage circuit 24 and outputs the result to the other input terminal of the current comparator 26.

  The current comparator 26 sequentially reads the cell currents corresponding to the normal data and the reference data “0” from the memory cell 21, sets the cell current corresponding to the reference data “0” as the reference current, and the offset current subtracter 25 The value of normal data is determined by comparing the output current with a reference current.

  The operation of the semiconductor memory device of this embodiment will be described below.

  First, in order to read normal data from the memory cell 21, the current selector 23 selects a path so that the memory cell 21 is connected to the current value storage circuit 24, and the memory cell 21 and the current value storage circuit 24 are connected. Conduct.

  Next, the current comparator 26 reads the cell current corresponding to the normal data from the memory cell 21 via the offset current subtracter 25 and the current value storage circuit 24.

  Next, the current value storage circuit 24 stores a cell current corresponding to normal data read from the memory cell 21.

  Next, the offset current subtracter 25 subtracts the offset current from the cell current corresponding to the normal data stored in the current value storage circuit 24 and outputs the result to the other input terminal of the current comparator 26.

  Next, in order to write the reference data “0” to the memory cell 21, the current selector 23 disconnects the current value storage circuit 24 and the current comparator 26 from the memory cell 21.

  Next, the write circuit 22 writes reference data “0” in the memory cell 21.

  Next, in order to read the reference data “0” written in the memory cell 21, the current selector 23 selects a path so that the memory cell 21 is connected to the current comparator 26. One input terminal is electrically connected to the memory cell 21.

  Next, the current comparator 26 reads the cell current corresponding to the reference data “0” from the memory cell 21 and sets it as the reference current.

  At this time, a reference current which is a cell current corresponding to the reference data “0” is input to one input terminal of the current comparator 26, and normal data output from the offset current subtractor 25 is input to the other input terminal. Is obtained by subtracting the offset current from the cell current corresponding to.

  Thereafter, the current comparator 26 determines the value of the normal data by comparing the current output from the offset current subtracter 25 with the reference current.

  Thereby, the current comparator 26 can determine whether the value of the normal data read from the memory cell 21 is ‘1’ or ‘0’.

  As described above, in the semiconductor memory device of this embodiment, the write circuit 22 writes the reference data “0” to the memory cell 21 from which the cell current corresponding to the normal data is read, and the current comparator 26 The cell current corresponding to the reference data “0” read from the memory cell 21 is used as a reference current, and the current obtained by subtracting the offset current from the cell current corresponding to the normal data is compared with the reference current to obtain the value of the normal data. It is the structure which determines.

  Thus, the reference current used for determining whether the normal data read from the memory cell 21 is “1” or “0” is generated from the memory cell 21 that has read the normal data. Can do.

  Therefore, in this embodiment, as in the first embodiment described above, even when the threshold voltage variation between the memory cells increases, the reference current is generated in each memory cell. The effect of variation can be eliminated, and an effect is obtained that it is possible to accurately determine whether the value of the normal data read from the memory cell 21 is “1” or data “0”.

(Third embodiment)
FIG. 3 is a block diagram showing the configuration of the semiconductor memory device according to the third embodiment of the present invention.

  As shown in FIG. 3, the semiconductor memory device of the present embodiment includes a memory cell 31, a write circuit 32, a current value storage circuit 33, an offset current subtractor 34, a first switch 35, and a second switch 36. And a current comparator 37.

  Compared with the second embodiment, the present embodiment is different in configuration in that it includes a first switch 35 and a second switch 36 instead of the current selector 23. Therefore, the memory cell 31 is connected to one input terminal of the current comparator 37 via the first switch 35, and the output terminal of the current comparator 37 is connected to the current value storage circuit 33 via the second switch 36. To do. Therefore, the operation of the current comparator 37 is different from the operation of the current comparator 26.

  Note that the memory cell 31, the write circuit 32, and the offset current subtractor 34 are the memory cell 21, the write circuit 22, and the offset of the second embodiment shown in FIG. Current subtracter 25.

  Data is written to and read from the memory cell 31 in the same manner as the memory cell 21 shown in FIG. A plurality of memory cells may exist.

  The write circuit 32 writes normal data to the memory cell 31. Further, when the cell current corresponding to the normal data written in the memory cell 31 is read, the write circuit 32 writes the reference data “0” in the memory cell 31 thereafter.

  The first switch 35 conducts the one input terminal of the current comparator 37 and the memory cell 31 when reading data from the memory cell 31 and cuts off when writing data.

  The second switch 36 makes the output terminal of the current comparator 37 and the current value storage circuit 33 conductive when reading normal data from the memory cell 31, and cuts off when writing data and reading reference data “0”. .

  The current value storage circuit 33 stores a cell current corresponding to normal data read from the memory cell 31.

  The offset current subtracter 34 subtracts the offset current from the cell current corresponding to the normal data read from the memory cell 31 stored in the current value storage circuit 33 and outputs the result to the other input terminal of the current comparator 37.

  The current comparator 37 reads the cell current corresponding to the normal data from the memory cell 31 and outputs it to the current value storage circuit 33. Thereafter, the current comparator 37 reads the cell current corresponding to the reference data “0” written in the memory cell 31, uses it as a reference current, and compares the current output from the offset current subtractor 34 with the reference current. Determine the value of normal data.

  The operation of the semiconductor memory device of this embodiment will be described below.

  First, in order to read normal data from the memory cell 31, the first switch 35 and the second switch 36 are turned on, and the memory cell 31 is connected to the current value storage circuit 33 via the current comparator 37.

  Next, the current comparator 37 reads the cell current corresponding to the normal data from the memory cell 31 and outputs it to the current value storage circuit 33.

  Next, the current value storage circuit 33 stores the cell current corresponding to the normal data output from the current comparator 37.

  Next, the offset current subtracter 34 subtracts the offset current from the cell current corresponding to the normal data stored in the current value storage circuit 33 and outputs the result to the other input terminal of the current comparator 37.

  Next, the first switch 35 and the second switch 36 are cut off in order to write the reference data “0” into the memory cell 31.

  Next, the write circuit 32 writes the reference data “0” to the memory cell 31.

  Next, the first switch 35 is turned on again to read the reference data “0” written in the memory cell 31. At this time, the second switch 36 is kept off.

  Next, the current comparator 37 reads the cell current corresponding to the reference data “0” from the memory cell 31 and sets it as the reference current.

  At this time, a reference current which is a cell current corresponding to the reference data “0” is input to one input terminal of the current comparator 37, and normal data output from the offset current subtractor 34 is input to the other input terminal. Is obtained by subtracting the offset current from the cell current corresponding to.

  Thereafter, the current comparator 37 determines the value of the normal data by comparing the current output from the offset current subtractor 34 with the reference current.

  Thereby, the current comparator 37 can determine whether the value of the normal data read from the memory cell 31 is ‘1’ or ‘0’.

  As described above, in the semiconductor memory device of the present embodiment, the write circuit 32 writes the reference data “0” to the memory cell 31 from which the cell current corresponding to the normal data is read, and the current comparator 37 The cell current corresponding to the reference data “0” read from the memory cell 31 is used as a reference current, and the current obtained by subtracting the offset current from the cell current corresponding to the normal data is compared with the reference current to obtain the value of the normal data. It is the structure which determines.

  As a result, the reference current used to determine whether the value of the normal data read from the memory cell 31 is “1” or “0” is generated from the memory cell 31 that has read the normal data. can do.

  Therefore, in this embodiment, as in the first and second embodiments described above, the reference current is generated in each memory cell even when the variation in the threshold voltage between the memory cells increases. The influence of the variation in threshold voltage can be eliminated, and an effect is obtained that it is possible to accurately determine whether the value of the normal data read from the memory cell 31 is “1” or data “0”.

[Specific Example 1]
FIG. 4 is a circuit diagram showing a configuration when the 1T-DRAM described in [Background Art] is assumed as a specific example 1 of the third embodiment of the present invention.

  As shown in FIG. 4, the semiconductor memory device of this specific example includes a memory cell 41, a write circuit 42, a first switch 43, a bit line potential holding circuit 44, a voltage control current source 45, and a current value storage. An element 46, an offset voltage subtractor 47, a second switch 48, and a current comparator 49 are included.

  Memory cell 41 is formed of one SOI transistor, and data is written and read in the same manner as memory cell 31 shown in FIG. A plurality of memory cells may exist.

  The write circuit 42 writes normal data to the memory cell 41. Further, when the cell current corresponding to the normal data written in the memory cell 41 is read, the write circuit 42 writes the reference data “0” in the memory cell 41 thereafter.

  The first switch 43 makes the bit line potential holding circuit 44 and the memory cell 41 conductive when reading data from the memory cell 41 and shuts off when writing data.

  The bit line potential holding circuit 44 is disposed between the first switch 43 and one input terminal of the current comparator 49, and holds the bit line potential of the memory cell 41 when reading data from the memory cell 41.

  The second switch 48 conducts the output terminal of the current comparator 49 and the current value storage element 46 when reading normal data from the memory cell 41, and cuts off when writing data and reading reference data “0”. .

  The current value storage element 46 corresponds to the current value storage circuit 33 shown in FIG. 3 and converts the cell current corresponding to the normal data read from the memory cell 41 into a voltage and stores it.

  The offset voltage subtracter 47 subtracts the offset voltage from the voltage stored in the current value storage element 46 and outputs it to the voltage controlled current source 45.

  The voltage control current source 45 is controlled by the voltage output from the offset voltage subtractor 47, and converts the voltage into a current obtained by subtracting the offset current from the cell current corresponding to the normal data read from the memory cell 41. Output to the other input terminal of the current comparator 49.

  In this specific example, the offset current subtracter 34 shown in FIG. 3 has the offset voltage subtractor 47 and the voltage control current source 45 described above.

  The current comparator 49 uses the cell current corresponding to the reference data “0” read from the memory cell 41 as a reference current, and compares the current output from the voltage control current source 45 with the reference current to thereby compare the normal data. Determine the value.

  The operation of the semiconductor memory device of this specific example will be described below.

  First, in order to read normal data from the memory cell 41, the first switch 43 is turned on, and the memory cell 41 and the bit line potential holding circuit 44 are connected.

  Next, the bit line potential holding circuit 44 holds the bit line potential of the memory cell 41 at a fixed potential.

  When normal data is read from the memory cell 41 in this state, a cell current corresponding to the normal data flows through the bit line and is input to one input terminal of the current comparator 49 via the bit line potential holding circuit 44.

  At the same time, the second switch 48 is turned on to connect the output terminal of the current comparator 49 and the current value storage element 47.

  At this time, the cell current corresponding to the normal data output from the current comparator 49 is converted into a voltage and stored in the current value storage element 47.

  Next, the offset voltage subtracter 46 subtracts the offset voltage from the voltage stored in the current value storage element 47 and outputs the result to the voltage controlled current source 45.

  Next, the voltage control current source 45 is controlled by the voltage output from the offset voltage subtractor 46, and subtracts the offset current from the cell current corresponding to the normal data read from the memory cell 41, which is converted from the voltage. Output current.

  Next, the first switch 43 and the second switch 48 are cut off in order to write the reference data “0” to the memory cell 41.

  Next, the write circuit 42 writes the reference data “0” in the memory cell 41.

  Next, the first switch 43 is turned on again, and the cell current corresponding to the reference data “0” is read from the memory cell 41. At this time, the second switch 48 is kept off.

  At this time, the cell current corresponding to the reference data “0” read from the memory cell 41 flows as a reference current through one input terminal of the current comparator 49. Further, a current obtained by subtracting the offset current from the cell current corresponding to the normal data read from the memory cell 41 output from the voltage control current source 45 flows through the other input terminal of the current comparator 49.

  Thereafter, the current comparator 49 determines the value of the normal data by comparing the current output from the voltage controlled current source 45 with the reference current.

  Thereby, the current comparator 49 can determine whether the value of the normal data read from the memory cell 41 is ‘1’ or ‘0’.

  As described above, in the semiconductor memory device of this specific example, the write circuit 42 writes the reference data “0” to the memory cell 41 from which the cell current corresponding to the normal data is read, and the current comparator 49 The cell current corresponding to the reference data “0” read from the memory cell 41 is used as a reference current, and the value obtained by subtracting the offset current from the cell current corresponding to the normal data is compared with the reference current to obtain the value of the normal data. It is the structure which determines.

  Thereby, the reference current used for determining whether the value of the normal data read from the memory cell 41 is “1” or “0” is generated from the memory cell 41 that has read the normal data. can do.

  Therefore, in this specific example, even if the threshold voltage variation between the memory cells increases, the reference current is generated in each memory cell, so that the influence of the threshold voltage variation can be eliminated. There is an effect that it is possible to accurately determine whether the value of the normal data read from the cell is “1” or data “0”.

[Specific Example 2]
FIG. 5 is a circuit diagram showing another configuration when the 1T-DRAM described in [Background Art] is assumed as a specific example 2 of the third embodiment of the present invention.

  As shown in FIG. 5, the semiconductor memory device of this example includes a memory cell 501, a write circuit 502, a first switch 503, a bit line potential holding circuit 504, a current mirror circuit 505, and a voltage controlled current source. 506, an offset voltage subtracter 507, a current value storage circuit 508, a second switch 509, and a current comparator 510.

  In this specific example, the current mirror circuit 505 is used as compared with the above-described specific example 1, so that a current equal to the cell current corresponding to the data read from the memory cell 501 is generated, whereby the memory cell 501 is generated. The current path is different from the current path on the current comparator 510 side.

  Note that the memory cell 501, the write circuit 502, the first switch 503, the bit line potential holding circuit 504, the voltage control current source 506, the offset voltage subtractor 507, the current value storage element 508, and the second switch 509 and the current comparator 510 are the memory cell 41, the write circuit 42, the first switch 43, the bit line potential holding circuit 44, and the voltage control of the specific example 1 shown in FIG. This corresponds to the current source 45, the offset voltage subtractor 46, the current value storage element 47, the second switch 48, and the current comparator 49.

  Memory cell 501 is composed of one SOI transistor, and data is written and read in the same manner as memory cell 41 shown in FIG. A plurality of memory cells may exist.

  The write circuit 502 writes normal data to the memory cell 501. Further, when the cell current corresponding to the normal data written in the memory cell 501 is read, the writing circuit 502 writes the reference data “0” in the memory cell 501 thereafter.

  The first switch 503 makes the bit line potential holding circuit 504 and the memory cell 501 conductive when reading data from the memory cell 501 and shuts off when writing data.

  The bit line potential holding circuit 504 is arranged between the first switch 503 and the current mirror circuit 505, and holds the bit line potential when reading data from the memory cell 501.

  The current mirror circuit 505 is disposed between the bit line potential holding circuit 504 and one input terminal of the current comparator 510. The current mirror circuit 505 generates a current equal to the cell current corresponding to the data input from the memory cell 501 via the bit line potential holding circuit 504 when reading data from the memory cell 501, and Output to one input terminal.

  The second switch 509 conducts the output terminal of the current comparator 510 and the current value storage element 508 when reading normal data from the memory cell 501, and cuts off when writing data and reading reference data “0”. .

  The current value storage element 508 converts a current corresponding to normal data out of the current output from the current mirror circuit 505 into a voltage and stores it.

  The offset voltage subtracter 507 subtracts the offset voltage from the voltage stored in the current value storage element 508 and outputs the result to the voltage controlled current source 506.

  The voltage control current source 506 is controlled by the voltage output from the offset voltage subtractor 507, and converts the voltage into a current obtained by subtracting the offset current from the current corresponding to normal data, and the other input terminal of the current comparator 510. Output to.

  Also in this specific example, the offset current subtracter 34 illustrated in FIG. 3 includes the above-described offset voltage subtracter 507 and the voltage control current source 506.

  The current comparator 510 normally uses the current output from the current mirror circuit 505 corresponding to the reference data “0” as a reference current, and compares the current output from the voltage controlled current source 506 with the reference current. Determine the value of the data.

  The operation of the semiconductor memory device of this specific example will be described below.

  First, in order to read normal data from the memory cell 501, the first switch 503 is turned on to connect the memory cell 501 and the bit line potential holding circuit 504.

  Next, the bit line potential holding circuit 504 holds the bit line potential of the memory cell 501 at a fixed potential.

  When normal data is read from the memory cell 501 in this state, a cell current corresponding to the normal data flows through the bit line and is input to the current mirror circuit 505 through the bit line potential holding circuit 504.

  At this time, the current mirror circuit 505 generates a current equal to the cell current corresponding to the input normal data and outputs it to one input terminal of the current comparator 510.

  At the same time, the second switch 509 is turned on to connect the output terminal of the current comparator 510 and the current value storage element 508.

  At this time, the current corresponding to the normal data output from the current comparator 510 is converted into a voltage and stored in the current value storage element 508.

  Next, the offset voltage subtracter 507 subtracts the offset voltage from the voltage stored in the current value storage element 508 and outputs the result to the voltage controlled current source 506.

  Next, the voltage controlled current source 506 is controlled by the voltage output from the offset voltage subtracter 507, and outputs a current obtained by subtracting the offset current from the current corresponding to the normal data obtained by converting the voltage.

  Next, the first switch 503 and the second switch 509 are disconnected in order to write the reference data “0” to the memory cell 501.

  Next, the write circuit 502 writes reference data “0” in the memory cell 501.

  Next, the first switch 503 is turned on again, and the cell current corresponding to the reference data “0” is read from the memory cell 501. At this time, the second switch 509 is kept off.

  Next, the current mirror circuit 505 generates a current equal to the cell current corresponding to the reference data “0”, and outputs the current to one input terminal of the current comparator 510.

  At this time, a current corresponding to the reference data “0” output from the current mirror circuit 505 flows through one input terminal of the current comparator 510 as a reference current. In addition, a current obtained by subtracting the offset current from the current corresponding to the normal data output from the voltage control current source 506 flows through the other input terminal of the current comparator 510.

  Thereafter, the current comparator 510 determines the value of the normal data by comparing the current output from the voltage controlled current source 506 with the reference current.

  Accordingly, the current comparator 510 can determine whether the value of the normal data read from the memory cell 501 is ‘1’ or ‘0’.

  As described above, in the semiconductor memory device of this specific example, the write circuit 502 writes the reference data “0” to the memory cell 501 from which the cell current corresponding to the normal data is read, and the current comparator 510 A current equal to the cell current corresponding to the reference data “0” read from the memory cell 501 is set as a reference current, and a current obtained by subtracting the offset current from a current equal to the cell current corresponding to the normal data is compared with the reference current. Thus, the value of normal data is determined.

  As a result, a reference current used for determining whether the value of the normal data read from the memory cell 501 is “1” or “0” is generated from the memory cell 501 that has read the normal data. can do.

  Therefore, in this specific example, as in the first specific example, even when the variation in threshold voltage between the memory cells increases, the reference current is generated in each memory cell. As a result, it is possible to accurately determine whether the value of data read from the memory cell is “1” or “0”.

[Circuit configuration example 1]
FIG. 6 is a circuit configuration example 1 of the second specific example of the third embodiment of the present invention, in which a gate potential control type offset subtraction method for controlling a gate potential of a current source 607 described later is used as an offset voltage subtraction method. It is a circuit diagram which shows the structure in the case of having met.

  As shown in FIG. 6, the semiconductor memory device of this circuit configuration example includes a memory cell 601, a write circuit 602, a first transfer gate 603, a cascode transistor 604, a bias voltage source 605, a current mirror circuit 606, and the like. , A current source 607, a capacitive element 608, an offset voltage generator 609, a second transfer gate 610, and an output inverter 611.

The memory cell 601 includes one SOI transistor, and data is written and read in the same manner as the memory cell 501 shown in FIG. As shown in FIG. 6, in the SOI transistor constituting the memory cell 601, the gate terminal is connected to the word line WL, the drain terminal is connected to the bit line BL, and the source terminal is connected to the ground GND. Further, the substrate potential is a floating potential, expressed as V _B. A plurality of memory cells may exist.

  The write circuit 602 writes normal data to the memory cell 601. Further, when the cell current corresponding to the normal data written in the memory cell 601 is read, the write circuit 602 writes the reference data “0” in the memory cell 601 after that.

  The first transfer gate 603 corresponds to the first switch 503 shown in FIG. 5, and the memory cell 601 and the cascode transistor 604 are connected to the data from the memory cell 601 by the write control signals (external control signals) WE and WEB. Conducts when reading, and shuts off when writing data.

  The cascode transistor 604 holds the bit line potential when reading data from the memory cell 601.

  The bias voltage source 605 applies a bias voltage to the gate terminal of the cascode transistor 604 and controls it.

  In this circuit configuration example, the bit line potential holding circuit 504 shown in FIG. 5 includes the cascode transistor 604 and the bias voltage source 605 described above.

  The current mirror circuit 606 generates and outputs a current equal to the cell current of data input from the memory cell 601 via the cascode transistor 604 when reading data from the memory cell 601. As shown in FIG. 6, the current mirror circuit 606 of this circuit configuration example has two transistors, an input-side transistor Mp1 and an output-side transistor Mp2.

  The capacitive element 608 corresponds to the current value storage element 508 shown in FIG. 5, and in order to store a voltage obtained by converting a current corresponding to normal data out of the current output from the current mirror circuit 606, a charge is stored. Hold. As shown in FIG. 6, in this circuit configuration example, the capacitive element 608 is connected to a gate terminal of a current source 607, which will be described later, and operates as a gate potential holding capacitor.

The offset voltage generator 609 is connected to one terminal of the capacitive element 608 and outputs an offset voltage −V _OS having a negative value in order to subtract the offset voltage from the voltage stored in the capacitive element 608.

  FIG. 7 shows a configuration example of the offset voltage generator 609 used in this circuit configuration example.

As shown in FIG. 7, the offset generator 609 includes a negative power supply for supplying a negative offset voltage −V _OS , a ground GND for applying a potential of 0 V, an external control signal EN, and its inverted signal. Pass transistors 701 and 702 controlled by.

When the external control signal EN = 0 (= V _SS ), the pass transistor 701 is cut off and the pass transistor 702 is turned on, so that the ground GND is selected and the output voltage of the offset voltage generator 609 becomes 0V.

On the other hand, when the external control signal EN = 1 (= V _DD ), the pass transistor 701 is turned on and the pass transistor 702 is cut off, so that the negative power supply is selected and the output voltage of the offset voltage generator 609 is −V _OS. It becomes.

  Further, in this circuit configuration example, as shown in FIG. 6, the drain terminal is connected to the output side transistor Mp2 of the current mirror circuit 606, the substrate terminal and the source terminal are connected to the ground GND, the gate terminal is connected to the second transfer gate 610 and the capacitor. Each node between the element 608 has nMOS transistors connected thereto.

  In this circuit configuration example, the offset voltage subtracter 507 shown in FIG. 5 uses the capacitive element 608 in common, and includes the above-described nMOS transistor and the offset voltage generator 609.

  Further, the current source 607 uses the above-described nMOS transistor in common.

  A current corresponding to the normal data output from the current mirror circuit 606 flows through the current source 607 when normal data is read from the memory cell 601. At this time, since the gate-source voltage necessary for maintaining the current flowing through the current source 607 is applied to the capacitor 608, a current corresponding to normal data is stored in the capacitor 608 as a voltage.

  Further, since the offset voltage generator 609 outputs the offset voltage after the reference data “0” is read, the voltage obtained by subtracting the offset voltage from the voltage stored in the capacitor 608 by capacitive coupling via the capacitor 608. Is added to the gate terminal of the current source 607. As a result, a current obtained by subtracting the offset current from the current corresponding to the normal data flows through the current source 607.

  In the circuit configuration example, the current comparator 510 shown in FIG. 5 uses the output side transistor Mp2 of the current mirror circuit 606 and the nMOS transistor as the current source 607 in common. The current comparator according to this circuit configuration example subtracts the offset current from the current corresponding to the normal data flowing to the current source 607 using the current equal to the cell current corresponding to the reference data '0' flowing through the transistor Mp2 as the reference current. The value of normal data is determined by comparing the current with a reference current.

  The second transfer gate 610 corresponds to the second switch 509 shown in FIG. 5, and the transistor Mp2 on the output side of the current mirror circuit 606 and the capacitor 608 are connected to the memory cell 601 by an external control signal φ and its inverted signal. It is turned on when normal data is read from and is cut off when data is written and when reference data “0” is read.

  The output inverter 611 is connected to a node between the transistor Mp2 on the output side of the current mirror circuit 606 and the current source 607. The output inverter 611 determines the value of the normal data read from the memory cell 601 (determined by the current comparator formed by using the current source 607 in common with the output-side transistor Mp2 of the current mirror circuit 606 described above. '1' or '0') is output.

  The operation of the semiconductor memory device of this circuit configuration example will be described below with reference to FIG. FIG. 8 is a diagram illustrating operation waveforms of each control signal in this circuit configuration example.

  As shown in FIG. 8, in the semiconductor memory device of this circuit configuration example, normal data is read from the memory cell 601 in the first cycle.

First, the write control signal WEB = 1 (V _DD ) and the first transfer gate 603 is turned on. At this time, the bit line potential is held by a bit line potential holding circuit including the cascode transistor 604 and the bias voltage source 605.

  In this state, when the word line WL is selected in the memory cell 601, a cell current corresponding to normal data written in the memory cell 601 flows through the bit line.

  Next, the current mirror circuit 606 generates and outputs a current equal to the cell current corresponding to the normal data flowing in the bit line.

Simultaneously with the selection of the word line WL in the memory cell 601, the external control signal φ = 1 (= V _DD ) is set to make the second transfer gate 610 conductive. At this time, the offset voltage generator 609 is disabled by setting the external control signal EN = 0 (= V _SS ). Therefore, the output of the offset voltage generator 609 is 0V. At this time, _VSS is a voltage having a negative value.

  By making the second transfer gate 610 conductive, a current corresponding to normal data output from the transistor Mp 2 on the output side of the current mirror circuit 606 flows to the current source 607. At this time, a gate-source voltage necessary for maintaining a current corresponding to normal data flowing in the current source 607 is applied to the capacitor 608.

  That is, a current corresponding to normal data flowing in the current source 607 is stored in the capacitor 608 as a voltage.

  In the next cycle, reference data “0” is written into the memory cell 601.

First, the external control signal φ = 0 (= GND) is set, and the second transfer gate 609 is cut off. Further, the first transfer gate 603 is cut off by setting the write control signal WEB = 0 (= V _SS ).

  Next, the write circuit 602 writes the reference data “0” to the memory cell 601 from which the normal data is read in the first cycle.

In the next cycle, the first transfer gate 603 is turned on again by setting the write control signal WEB = 1 (= V _DD ), and the reference data “0” is read from the memory cell 601. As a result, the cell current corresponding to the reference data “0” is input to the current mirror circuit 606, and an equal current is generated and output. At this time, the current source 607 maintains a current corresponding to normal data.

In the next cycle, the external control signal EN = 1 (= V _DD ) and the offset voltage generator 609 is activated. As a result, an offset voltage −V _OS having a negative value is generated at the output of the offset voltage generator 609.

At this time, a voltage obtained by subtracting the absolute value V _{OS of the} offset voltage from the voltage stored in the capacitor 608 is applied to the gate terminal of the current source 607 by capacitive coupling via the capacitor 608.

  Therefore, a current obtained by subtracting the offset current from the current corresponding to the normal data flows through the current source 607.

  Therefore, the current corresponding to the reference data “0” output from the current mirror circuit 606 is set as the reference current, and the current obtained by subtracting the offset current from the current corresponding to the normal data flowing through the current source 607 is compared with the reference current. The value of normal data can be determined.

  When the reference current is larger than the current flowing through the current source 607, the drain potential of the current source 607 rises, is inverted and amplified by the output inverter 611, and data “0” is output. This corresponds to reading of data “0”.

  When the reference current is smaller than the current flowing through the current source 607, the drain potential of the current source 607 drops, is inverted and amplified by the output inverter 611, and data “1” is output. This corresponds to reading of data “1”.

  Thereafter, the normal data value is output from the output inverter 611, and at the same time, the memory cell 601 is rewritten.

  Since rewriting to the memory cell 601 is the same as the writing operation of a normal 1T-DRAM, description thereof is omitted.

  FIG. 9 shows the operation principle of the semiconductor memory device of this circuit configuration example.

As shown in FIG. 9, in this circuit configuration example, the cell current I Cell — 0 corresponding to the reference data “0” read from the memory cell 601 is _set as the reference current I _ref, and the normal data read from the memory cell 601 is obtained. _Is compared with a current obtained by subtracting the offset current from the cell current corresponding to (I _{cell — 1} −I _OS1 or I _{cell — 0} −I _OS0 ). At this time, since the reference current I _ref is generated from each memory cell from which data is read, the value of the reference current is always the cell current corresponding to the normal data “1” and the normal data “0” in each memory cell. _Becomes a value in the vicinity of the intermediate value of the current obtained by subtracting the offset current from (I _{cell — 1} −I _OS1 and I _{cell — 0} −I _OS0 ). Therefore, in this circuit configuration example, whether or not the value of the normal data read from the memory cell 601 is “1” or “0” even when the threshold voltage variation between the memory cells increases. It can be determined accurately.

  As described above, in the semiconductor memory device of this circuit configuration example, a current equal to the cell current corresponding to the normal data read from the memory cell 601 is converted into a voltage and stored in the capacitor 608. Further, by controlling the offset voltage generator connected to the gate terminal of the current source 607 via the capacitive element 608, a current obtained by subtracting the offset current from the current corresponding to the normal data flows to the current source 607. Can do. Therefore, the current equal to the cell current corresponding to the reference data “0” is set as the reference current, and the value of the normal data is determined by comparing the current obtained by subtracting the offset current from the current corresponding to the normal data with the reference current. it can.

  Thereby, the reference current used for determining whether the value of the normal data read from the memory cell 601 is “1” or “0” is generated from the memory cell 601 itself that has read the normal data. can do.

  Therefore, even when the threshold voltage variation between the memory cells (SOI transistor cells) increases, the reference current is generated in each memory cell, so that the influence of the threshold voltage variation can be eliminated. As a result, it is possible to accurately determine whether the value of the normal data read from 601 is “1” or “0”.

[Circuit configuration example 2]
FIG. 10 is a circuit configuration example 2 of the second specific example of the third embodiment of the present invention, in which a gate potential control type offset subtraction method for controlling the gate potential of a current source 1007 described later is used for the offset voltage subtraction method. It is a circuit diagram which shows the other structure when there exists.

  As shown in FIG. 10, the semiconductor memory device of this circuit configuration example includes a memory cell 1001, a write circuit 1002, a first transfer gate 1003, a reference voltage source 1004, an operational amplifier 1005, and a current mirror circuit 1006. , A current source 1007, a capacitive element 1008, an offset voltage generator 1009, a second transfer gate 1010, and an output inverter 1011.

  This circuit configuration example is different from the circuit configuration example 1 described above in that a reference voltage source 1004 and an operational amplifier 1005 are provided instead of the cascode transistor 604 and the bias voltage source 605.

  Note that the memory cell 1001, the write circuit 1002, the first transfer gate 1003, the current mirror circuit 1006, the current source 1007, the capacitor element 1008, the offset voltage generator 1009, the second transfer gate 1010, and the output Regarding the inverter 1011, the memory cell 601, the write circuit 602, the first transfer gate 603, the current mirror circuit 606, the current source 607, and the capacitor element of the circuit configuration example 1 illustrated in FIG. 6, respectively. 608, an offset voltage generator 609, a second transfer gate 610, and an output inverter 611.

  The memory cell 1001 includes one SOI transistor, and data is written and read in the same manner as the memory cell 601 shown in FIG. A plurality of memory cells may exist.

  The write circuit 1002 writes normal data to the memory cell 1001. Further, when the cell current corresponding to the normal data written in the memory cell 1001 is read, the writing circuit 1002 writes the reference data “0” in the memory cell 1001 thereafter.

  The first transfer gate 1003 makes the memory cell 1001 and the current mirror circuit 1006 conductive when reading data from the memory cell 1001 and shuts off when writing data by the write control signals WE and WEB.

  The current mirror circuit 1006 generates and outputs a current equal to the cell current corresponding to the data flowing in the bit line when reading data from the memory cell 1001. Also in this circuit configuration example, the current mirror circuit 1006 includes two transistors, an input-side transistor Mp1 and an output-side transistor Mp2.

The reference voltage source 1004 applies the reference voltage V _ref to the operational amplifier 1005 and controls it.

In this circuit configuration example, the bit line potential holding circuit 504 shown in FIG. 5 uses the transistor Mp1 on the input side of the current mirror circuit 1006 in common, and the operational amplifier 1005, the reference voltage source 1004, ,have. In this circuit configuration example, since the bit line potential can be controlled to be equal to the output voltage V _ref of the reference voltage source 1004 by the negative feedback composed of the operational amplifier 1005 and the transistor Mp1, the bit line potential is maintained. be able to.

  The capacitive element 1008 holds electric charge in order to store a voltage obtained by converting a current corresponding to normal data out of the current output from the current mirror circuit 1006.

The offset voltage generator 1009 is connected to one terminal of the capacitive element 1008 and outputs an offset voltage −V _OS having a negative value in order to subtract the offset voltage from the voltage stored in the capacitive element 1008.

  Also in this circuit configuration example, as shown in FIG. 10, the drain terminal is the output side transistor Mp2 of the current mirror circuit 1006, the substrate terminal and the source terminal are the ground GND, the gate terminal is the second transfer gate 1010 and the capacitive element. The nMOS transistors connected to each other are connected to the nodes 1008 and 1008, respectively.

  Also in this circuit configuration example, similarly to the circuit configuration example 1, the offset voltage subtracter 507 shares the capacitive element 1008 and includes the above-described nMOS transistor and the offset voltage generator 1009. Yes.

  In addition, the current source 1007 shares the above-described nMOS transistor.

  A current corresponding to normal data output from the current mirror circuit 1006 flows through the current source 1007 when data is read from the memory cell 1001.

  In addition, since the offset voltage generator 1009 outputs an offset voltage after reading the reference data “0”, a voltage obtained by subtracting the offset voltage from the voltage stored in the capacitor element 1008 by capacitive coupling via the capacitor element 1008. Is added to the gate terminal of the current source 1007. As a result, a current obtained by subtracting the offset current from the current corresponding to the normal data flows through the current source 1007.

  Also in this circuit configuration example, the current comparator 510 uses the output side transistor Mp2 of the current mirror circuit 1006 and the nMOS transistor as the current source 1007 in common.

  The second transfer gate 1010 conducts the transistor Mp2 on the output side of the current mirror circuit 1006 and the capacitive element 1008 when the normal data is read from the memory cell 1001 by the external control signal φ and its inverted signal, and writes the data. And when reading reference data '0'.

  The output inverter 1011 is connected to a node between the transistor Mp2 on the output side of the current mirror circuit 1006 and the current source 1007, and the value of the normal data ('1' or '0') determined by the current comparator described above. Is output.

  As described above, the circuit configuration example is different from the circuit configuration example 1 only in the configuration of the bit line potential holding circuit that holds the bit line potential. The operation of holding the bit line potential is not the essence of the present invention, and the operations of the other components are the same as those in the circuit configuration example 1, and thus the description thereof is omitted here.

  As described above, in the semiconductor memory device of this circuit configuration example, the bit line potential holding circuit includes the negative feedback including the transistor Mp1 and the operational amplifier 1005, and the reference voltage source 1004. Therefore, this circuit configuration example has a configuration suitable for low-voltage operation by reducing the number of vertically stacked transistors between the power source and the ground, compared with the configuration of circuit configuration example 1 shown in FIG.

[Circuit Configuration Example 3]
FIG. 11 is a circuit configuration example 3 of the second specific example of the third embodiment of the present invention, in which a substrate potential control type offset subtraction method for controlling a substrate potential of a current source 1107 to be described later is used as an offset voltage subtraction method. It is a circuit diagram which shows the structure at the time of using.

  As shown in FIG. 11, the semiconductor memory device of this circuit configuration example includes a memory cell 1101, a write circuit 1102, a first transfer gate 1103, a reference voltage source 1104, an operational amplifier 1105, a current mirror circuit 1106, , A current source 1107, a capacitor element 1108, an offset voltage generator 1109, a second transfer gate 1110, and an output inverter 1111.

  These components are the memory cell 1001, the write circuit 1002, the first transfer gate 1003, the reference voltage source 1004, the operational amplifier 1005, and the current of the circuit configuration example 2 shown in FIG. This corresponds to the mirror circuit 1006, the current source 1007, the capacitive element 1008, the offset voltage generator 1009, the second transfer gate 1010, and the output inverter 1011.

  However, in this circuit configuration example, the offset voltage generator 1109 is connected to the substrate terminal of the current source 1107 and one terminal of the capacitive element 1108 is grounded to the ground GND, compared to the circuit configuration example 2 described above. It is different from the point.

  The memory cell 1101 includes one SOI transistor, and data is written and read in the same manner as the memory cell 1001 shown in FIG. A plurality of memory cells may exist.

  The write circuit 1102 writes normal data to the memory cell 1101. Further, when the cell current corresponding to the normal data written in the memory cell 1101 is read, the write circuit 1102 writes the reference data “0” in the memory cell 1101 thereafter.

  The first transfer gate 1103 conducts the memory cell 1101 and the current mirror circuit 1106 when data is read from the memory cell 1101 and shuts off when data is written by the write control signals WE and WEB.

  The current mirror circuit 1106 generates and outputs a current equal to the cell current corresponding to the data flowing through the bit line when reading data from the memory cell 1101. Also in this circuit configuration example, the current mirror circuit 1106 includes two transistors, an input-side transistor Mp1 and an output-side transistor Mp2.

The reference voltage source 1104 applies a reference voltage V _ref to the operational amplifier 1105 to control it.

In this circuit configuration example, the bit line potential holding circuit 504 shown in FIG. 5 uses the transistor Mp1 on the input side of the current mirror circuit 1106 in common, and the operational amplifier 1105, the reference voltage source 1104, ,have. In this circuit configuration example, the bit line potential can be controlled to be equal to the output voltage V _ref of the reference voltage source 1104 by the negative feedback comprising the operational amplifier 1105 and the transistor Mp1, so that the bit line potential is maintained. be able to.

  The capacitive element 1108 holds electric charge in order to store a voltage obtained by converting a current corresponding to normal data out of the current output from the current mirror circuit 1106.

The offset voltage generator 1109 is connected to the substrate terminal of the current source 1107, and outputs an offset voltage −V _OS having a negative value in order to increase the threshold voltage of the current source 1107.

In this circuit configuration example, the configuration of the offset voltage generator 609 shown in FIG. 7 can be used as the offset voltage generator 1109. However, the set value of the output voltage −V _OS of the negative power source is different between the circuit configuration example and the circuit configuration examples 1 and 2 using the gate potential control type offset subtraction method.

  Further, in this circuit configuration example, as shown in FIG. 11, the drain terminal is the output side transistor Mp2 of the current mirror circuit 1106, the substrate terminal is the offset voltage generator 1109, the source terminal is the ground GND, and the gate terminal is Each node between the second transfer gate 1110 and the capacitive element 1108 has nMOS transistors connected to each other.

  Also in this circuit configuration example, similarly to the circuit configuration example 1, the offset voltage subtracter 507 shares the capacitive element 1108, and includes the above-described nMOS transistor and the offset voltage generator 1109. Yes.

  In addition, the current source 1107 shares the above-described nMOS transistor.

  A current corresponding to normal data output from the current mirror circuit 1106 flows through the current source 1107 when data is read from the memory cell 1101.

  Further, after the reference data “0” is read, the offset voltage generator 1109 outputs the offset voltage, so that the threshold voltage increases due to the substrate bias effect. As a result, the current source 1107 corresponds to the normal data. A current obtained by subtracting the offset current from the current flows.

  Also in this circuit configuration example, the current comparator 510 uses the transistor Mp2 on the output side of the current mirror circuit 1106 and the current source 1107 in common.

  The second transfer gate 1110 conducts the transistor Mp2 on the output side of the current mirror circuit 1106 and the capacitive element 1108 when reading normal data from the memory cell 1101 by the external control signal φ and its inverted signal, and writes data. And when reading reference data '0'.

  The output inverter 1111 is connected to a node between the transistor Mp2 on the output side of the current mirror circuit 1106 and the current source 1107, and the value of the normal data ('1' or '0') determined by the current comparator described above. Is output.

  The operation of the semiconductor memory device of this circuit configuration example is the same as that of the circuit configuration example 1 or the circuit configuration example 2 using the gate potential control type offset subtraction method, except for the cycle operation for subtracting the offset voltage. Therefore, only the operation of the cycle for subtracting the offset voltage will be described here.

In this circuit configuration example, in the cycle of subtracting the offset voltage, the external control signal EN = 1 (= V _DD ), the offset voltage generator 1109 is activated, and the offset having a negative value at the substrate terminal of the current source 1107 Apply voltage -V _OS .

  As a result, a substrate bias effect occurs in the current source 1107, and the threshold voltage of the current source 1107 increases.

  Therefore, a current obtained by subtracting the offset current from the current corresponding to the normal data flows through the current source 1107.

  On the other hand, the current mirror circuit 1106 outputs a current corresponding to the reference data “0”.

  Therefore, the current value corresponding to the reference data “0” output from the current mirror circuit 1106 is set as a reference current, and the value of the normal data can be determined by comparing the current flowing through the current source 1107 with the reference current.

  When the reference current is larger than the current flowing through the current source 1107, the drain potential of the current source 1107 rises and is inverted and amplified by the output inverter 1111 to output data '0'. This corresponds to reading of data “0”.

  When the reference current is smaller than the current flowing through the current source 1107, the drain potential of the current source 1107 drops and is inverted and amplified by the output inverter 1111 to output data '1'. This corresponds to reading of data “1”.

  As described above, also in the semiconductor memory device of this circuit configuration example, the reference current used for determining whether the value of the normal data read from the memory cell 1101 is “1” or “0” is used as the normal data. Can be generated from the memory cell 1101 itself that has read the data.

  Therefore, similarly to the circuit configuration examples 1 and 2 using the gate potential control type offset subtraction method, even when the variation in the threshold voltage between the memory cells (SOI transistor cells) increases, the reference current is applied to each memory cell. Therefore, it is possible to eliminate the influence of threshold voltage variation and to accurately determine whether the value of data read from the memory cell 1101 is “1” or “0”. can get.

[Circuit Configuration Example 4]
FIG. 12 is a circuit configuration example 4 of the second specific example of the third embodiment of the present invention. As a subtraction method of an offset voltage, a source potential control type offset subtraction that controls the potential of a source terminal of a current source 1207 described later. It is a circuit diagram which shows the structure at the time of using a system.

  As shown in FIG. 12, the semiconductor memory device of this circuit configuration example includes a memory cell 1201, a write circuit 1202, a first transfer gate 1203, a reference voltage source 1204, an operational amplifier 1205, a current mirror circuit 1206, , A current source 1207, a capacitive element 1208, an offset voltage generator 1209, a second transfer gate 1210, and an output inverter 1211.

  These components are the memory cell 1001, the write circuit 1002, the first transfer gate 1003, the reference voltage source 1004, the operational amplifier 1005, and the current of the circuit configuration example 2 shown in FIG. This corresponds to the mirror circuit 1006, the current source 1007, the capacitive element 1008, the offset voltage generator 1009, the second transfer gate 1010, and the output inverter 1011.

  However, in this circuit configuration example, as compared with the above-described circuit configuration example 2, the offset voltage generator 1209 is connected to the source terminal of the current source 1207 and one terminal of the capacitor 1208 is connected to the ground GND. It is different from the grounding point.

  Memory cell 1201 is formed of one SOI transistor, and data is written and read in the same manner as memory cell 1101 shown in FIG. A plurality of memory cells may exist.

  The write circuit 1202 writes normal data to the memory cell 1201. In addition, when the cell current corresponding to the normal data written in the memory cell 1201 is read, the write circuit 1202 writes the reference data “0” in the memory cell 1201 thereafter.

  The first transfer gate 1203 makes the memory cell 1201 and the current mirror circuit 1206 conductive when reading data from the memory cell 1201 and shuts off when writing data by the write control signals WE and WEB.

  The current mirror circuit 1206 generates and outputs a current equal to the cell current corresponding to the data flowing through the bit line when reading data from the memory cell 1201. Also in this circuit configuration example, the current mirror circuit 1206 includes two transistors, an input-side transistor Mp1 and an output-side transistor Mp2.

The reference voltage source 1204 applies a reference voltage V _ref to the operational amplifier 1205 and controls it.

In this circuit configuration example, the bit line potential holding circuit 504 shown in FIG. 5 uses the transistor Mp1 on the input side of the current mirror circuit 1206 in common, and the operational amplifier 1205, the reference voltage source 1204, ,have. In this circuit configuration example, since the bit line potential can be controlled to be equal to the output voltage V _ref of the reference voltage source 1204 by the negative feedback composed of the operational amplifier 1205 and the transistor Mp1, the bit line potential is maintained. be able to.

  The capacitive element 1208 holds electric charge in order to store a voltage obtained by converting a current corresponding to normal data out of the current output from the current mirror circuit 1206.

An offset voltage generator 1209 is connected to the source terminal of the current source 1207 and increases the threshold voltage of the current source 1207 and an offset having a positive value to decrease the gate-source voltage of the current source 1207. A voltage _VOS is generated.

  FIG. 13 shows a configuration example of the offset voltage generator 1209 used in this circuit configuration example.

As shown in FIG. 13, the offset generator 1209 includes a positive power supply for _supplying an offset voltage V _OS having a positive value, a ground GND for applying a potential of 0 V, an external control signal EN, and its inverted signal. A pass transistor 1301 and a transfer gate 1302 to be controlled are included.

When the external control signal EN = 0 (= V _SS ), the transfer gate 1302 is cut off and the pass transistor 1301 is turned on, so that the ground GND is selected, and the output voltage of the offset voltage generator 1209 becomes 0V.

When the external control signal EN = 1 (= V _DD ), the transfer gate 1302 is turned on and the pass transistor 1301 is cut off, so that the positive power supply V _OS is selected, and the output voltage of the offset voltage generator 1209 is V _OS and Become.

  In this circuit configuration example, as shown in FIG. 12, the drain terminal is the output side transistor Mp2 of the current mirror circuit 1206, the substrate terminal is the ground GND, the source terminal is the offset voltage generator 1209, and the gate terminal is the second. Each node between the transfer gate 1210 and the capacitor 1208 has nMOS transistors connected thereto.

  Also in this circuit configuration example, similarly to the circuit configuration example 1, the offset voltage subtracter 507 shares the capacitor element 1208 and includes the above-described nMOS transistor and the offset voltage generator 1209. .

  The current source 1207 shares the above-described nMOS transistor.

  A current corresponding to the normal data output from the current mirror circuit 1206 flows through the current source 1207 when normal data is read from the memory cell 1201.

  In addition, after the reference data “0” is read, the offset voltage generator 1209 outputs the offset voltage, so that the threshold voltage increases due to the substrate bias effect, and the gate-source voltage decreases. A current obtained by subtracting an offset current from a current corresponding to normal data flows through the current source 1207.

  Also in this circuit configuration example, the current comparator 510 uses the transistor Mp2 on the output side of the current mirror circuit 1206 and the current source 1207 in common.

  The second transfer gate 1210 conducts the transistor Mp2 on the output side of the current mirror circuit 1206 and the capacitive element 1208 when the normal data is read from the memory cell 1201 by the external control signal φ and its inverted signal, and writes the data. And when reading reference data '0'.

  The output inverter 1211 is connected to an intermediate node between the transistor Mp2 on the output side of the current mirror circuit 1206 and the current source 1207, and the normal data value ('1' or '0') determined by the current comparator described above is used. Output.

  The operation of the semiconductor memory device of this circuit configuration example is the same as that of the circuit configuration example 1 or the circuit configuration example 2 using the gate potential control type offset subtraction method, except for the operation of the cycle for subtracting the offset voltage. Therefore, only the operation of the cycle for subtracting the offset voltage will be described here.

In this circuit configuration example, in the cycle of subtracting the offset voltage, the external control signal EN = 1 (= V _DD ), the offset voltage generator 1209 is activated, and the offset having a positive value at the source terminal of the current source 1207 applying a voltage _{V OS.}

  As a result, a substrate bias effect occurs in the current source 1207, and the threshold voltage of the current source 1207 increases. In addition, when the source potential of the current source 1207 increases, the gate-source voltage for driving the current source 1207 decreases.

  Therefore, a current obtained by subtracting the offset current from the current corresponding to the normal data flows through the current source 1207.

  On the other hand, a current corresponding to the reference data “0” is output from the current mirror circuit 1206 at this time.

  Therefore, the current value corresponding to the reference data “0” output from the current mirror circuit 1206 is used as a reference current, and the value of the normal data can be determined by comparing the current flowing through the current source 1207 with the reference current.

  When the reference current is larger than the current flowing through the current source 1207, the drain potential of the current source 1207 rises and is inverted and amplified by the output inverter 1211 to output data '0'. This corresponds to reading of data “0”.

  When the reference current is smaller than the current flowing through the current source 1207, the drain potential of the current source 1207 drops and is inverted and amplified by the output inverter 1211 to output data '1'. This corresponds to reading of data “1”.

  As described above, also in this circuit configuration example, the reference current used to determine whether the value of the normal data read from the memory cell 1201 is “1” or “0” is used as the normal data read. Can be generated from the memory cell 1201 itself.

  Therefore, the threshold voltage between the memory cells (SOI transistor cells) is similar to the circuit configuration examples 1 and 2 using the gate potential control type offset subtraction method and the circuit configuration example 3 using the substrate potential control type offset subtraction method. Since the reference current is generated in each memory cell even when the variation of the memory cell increases, the influence of the variation of the threshold voltage can be eliminated, and the value of the normal data read from the memory cell 1201 is “1”. It is possible to obtain an effect that it is possible to accurately determine whether it is “0” or “0”.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-007873 for which it applied on January 17, 2008, and takes in those the indications of all here.

Claims (12)

A memory cell in which charge is stored or removed according to the value of the data when data is written, and a cell current corresponding to the charge is read when the data is read;
A write circuit for writing normal data to the memory cell, and writing a reference data to the memory cell after reading a cell current corresponding to the normal data;
An offset current subtracter that subtracts and outputs an offset current from a cell current corresponding to normal data read from the memory cell;
The cell currents corresponding to the normal data and the reference data are sequentially read from the memory cell, the cell current corresponding to the reference data is used as a reference current, and the current output from the offset current subtractor is used as the reference current. A semiconductor memory device comprising: a current comparator that determines the value of the normal data by comparing. A current value storage circuit for storing a cell current corresponding to the normal data;
The current value storage circuit and the memory cell are electrically connected when reading the normal data, the one input terminal of the current comparator is electrically connected and the memory cell when the reference data is read, and the data cell is written when the data is written. A current selector that shuts off the current value storage circuit and the current comparator from the memory cell,
2. The semiconductor according to claim 1, wherein the offset current subtracter subtracts an offset current from a cell current corresponding to the normal data stored in the current value storage circuit, and outputs the subtracted current to the other input terminal of the current comparator. Storage device. A current value storage circuit for storing a cell current corresponding to the normal data;
A first switch that conducts the one input terminal of the current comparator and the memory cell at the time of reading the data and cuts off at the time of writing the data;
A second switch that conducts the output terminal of the current comparator and the current value storage circuit when reading the normal data, and shuts off when writing the data and reading the reference data;
2. The semiconductor according to claim 1, wherein the offset current subtracter subtracts an offset current from a cell current corresponding to the normal data stored in the current value storage circuit, and outputs the subtracted current to the other input terminal of the current comparator. Storage device. A bit line potential holding circuit which is arranged between the first switch and one input terminal of the current comparator and holds the bit line potential of the memory cell at the time of reading the data;
The current value storage circuit includes a current value storage element that converts a cell current corresponding to the normal data into a voltage and stores the voltage.
The offset current subtractor is
An offset voltage subtracter that subtracts and outputs an offset voltage from the voltage stored in the current value storage element;
Voltage control that is controlled by the voltage output from the offset voltage subtractor and outputs a current obtained by subtracting the offset current from the cell current corresponding to the normal data obtained by converting the voltage to the other input terminal of the current comparator The semiconductor memory device according to claim 3, further comprising: a current source. A cell current corresponding to the data, which is arranged between the bit line potential holding circuit and one input terminal of the current comparator, and is input via the bit line potential holding circuit when reading the data; A current mirror circuit that generates an equal current and outputs the current to one input terminal of the current comparator;
The current comparator converts the current corresponding to the normal data out of the current output from the current mirror circuit into a voltage by the current value storage element and stores the voltage, and stores the current output from the current mirror circuit. 5. The semiconductor memory according to claim 4, wherein a current corresponding to the reference data is set as the reference current, and a value of the normal data is determined by comparing a current output from the voltage control current source with the reference current. apparatus. Each of the first and second switches includes first and second transfer gates that are turned on and off by an external control signal, respectively.
The bit line potential holding circuit includes:
A cascode transistor that holds a bit line potential;
A bias voltage source for applying and controlling a bias voltage to the gate terminal of the cascode transistor,
The current mirror circuit has two transistors on the input side and the output side,
The current storage element is composed of a capacitive element that holds a charge,
The offset voltage subtracter
The capacitive element is shared and used.
An offset voltage generator connected to one terminal of the capacitive element and outputting an offset voltage having a negative value;
An nMOS transistor having a drain terminal connected to the transistor on the output side of the current mirror circuit, a substrate terminal and a source terminal connected to the ground, and a gate terminal connected to a node between the second transfer gate and the capacitive element; Have
The voltage controlled current source uses the nMOS transistor in common,
The current comparator is
A transistor on the output side of the current mirror circuit;
The nMOS transistor is shared and used.
6. The semiconductor memory according to claim 5, further comprising an output inverter connected to an intermediate node between the output-side transistor of the current mirror circuit and the nMOS transistor and outputting the value of the normal data determined by the current comparator. apparatus. Each of the first and second switches includes first and second transfer gates that are turned on and off by an external control signal, respectively.
The current mirror circuit has two transistors on the input side and the output side,
The bit line potential holding circuit includes:
The transistor on the input side of the current mirror circuit is shared and used,
An operational amplifier;
A reference voltage source for applying and controlling a voltage to the operational amplifier, and
The current storage element is composed of a capacitive element that holds a charge,
The offset voltage subtracter
The capacitive element is shared and used.
An offset voltage generator connected to one terminal of the capacitive element and outputting an offset voltage having a negative value;
An nMOS transistor having a drain terminal connected to the transistor on the output side of the current mirror circuit, a substrate terminal and a source terminal connected to the ground, and a gate terminal connected to a node between the second transfer gate and the capacitive element; Have
The voltage controlled current source uses the nMOS transistor in common,
The current comparator is
A transistor on the output side of the current mirror circuit;
The nMOS transistor is shared and used.
6. The semiconductor according to claim 5, further comprising an output inverter connected to a node between an output-side transistor of the current mirror circuit and the nMOS transistor and outputting the value of the normal data determined by the current comparator. Storage device. Each of the first and second switches includes first and second transfer gates that are turned on and off by an external control signal, respectively.
The current mirror circuit has two transistors on the input side and the output side,
The bit line potential holding circuit includes:
The transistor on the input side of the current mirror circuit is shared and used,
An operational amplifier;
A reference voltage source for applying and controlling a reference voltage to the operational amplifier, and
The current storage element is composed of a capacitive element that holds a charge,
The offset voltage subtracter
The capacitive element is shared and used.
An offset voltage generator that outputs an offset voltage having a negative value;
The drain terminal is the transistor on the output side of the current mirror circuit, the substrate terminal is the offset voltage generator, the source terminal is the ground, and the gate terminal is the node between the second transfer gate and the capacitive element, respectively. NMOS transistors connected to each other,
The voltage controlled current source uses the nMOS transistor in common,
The current comparator is
A transistor on the output side of the current mirror circuit;
The nMOS transistor is shared and used.
6. The semiconductor according to claim 5, further comprising an output inverter connected to a node between an output-side transistor of the current mirror circuit and the nMOS transistor and outputting the value of the normal data determined by the current comparator. Storage device. Each of the first and second switches includes first and second transfer gates that are turned on and off by an external control signal, respectively.
The current mirror circuit has two transistors on the input side and the output side,
The bit line potential holding circuit includes:
The transistor on the input side of the current mirror circuit is shared and used,
An operational amplifier;
A reference voltage source for applying and controlling a reference voltage to the operational amplifier, and
The current storage element is composed of a capacitive element that holds a charge,
The offset voltage subtracter
The capacitive element is shared and used.
An offset voltage generator for outputting an offset voltage having a positive value;
The drain terminal is a transistor on the output side of the current mirror circuit, the substrate terminal is ground, the source terminal is the offset voltage generator, and the gate terminal is a node between the second transfer gate and the capacitive element, respectively. NMOS transistors connected to each other,
The voltage controlled current source uses the nMOS transistor in common,
The current comparator is
A transistor on the output side of the current mirror circuit;
The nMOS transistor is shared and used.
6. The semiconductor according to claim 5, further comprising an output inverter connected to a node between an output-side transistor of the current mirror circuit and the nMOS transistor and outputting the value of the normal data determined by the current comparator. Storage device.   The semiconductor memory device according to claim 1, wherein the memory cell includes an SOI transistor. A data read method performed by a semiconductor memory device having a memory cell in which charge is accumulated or removed according to the value of the data when data is written and cell current corresponding to the charge is read when the data is read There,
A first read step of reading a cell current corresponding to normal data written to the memory cell;
A subtraction step of subtracting an offset current from a cell current corresponding to the normal data;
A writing step of writing reference data to a memory cell from which a cell current corresponding to the normal data is read;
A second reading step of reading a cell current corresponding to the reference data written in the memory cell;
Determination of determining a value of the normal data by comparing a cell current corresponding to the reference data as a reference current and a current obtained by subtracting an offset current from the cell current corresponding to the normal data in the subtraction step with the reference current And a data reading method comprising: steps. Storing a cell current corresponding to the normal data;
12. The data reading method according to claim 11, wherein in the subtracting step, an offset current is subtracted from a cell current corresponding to the normal data stored in the storing step.

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