JPWO2006103853A1 - Semiconductor device using titanium dioxide as active layer and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using titanium dioxide as an active layer and a manufacturing method thereof. A semiconductor device of the present invention includes TiO2 as an active layer. The semiconductor device 10 of the present invention includes a gate electrode 20, a TiO2 layer 12 that functions as a semiconductor active layer and forms a channel, a source electrode 14 and a drain electrode 16 that are electrically connected to the TiO2 layer 12, a gate, An insulating film 18 formed between the electrode 20 and the TiO 2 layer 12 is included. The TiO 2 layer 12 can be a single crystal substrate including a rutile or anatase structure having a step-terrace structure. The TiO 2 layer 12 can be a vapor deposition film of TiO 2. Furthermore, the present invention provides a method for manufacturing a semiconductor device including TiO 2 as an active layer. [Selection] Figure 1

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device using titanium dioxide (TiO ₂ ) as an active layer and a method for manufacturing the same.

  2. Description of the Related Art In recent years, field effect type semiconductor devices have been used to provide a display device by configuring an active matrix type array in addition to a logical operation device of an information processing device. Conventionally, materials having semiconductor activity such as amorphous silicon, single crystal silicon, and zinc oxide (ZnO) are known as active layers of field effect semiconductor devices. Semiconductor materials such as amorphous silicon, single crystal silicon, and ZnO have a property of generating photocarriers by absorbing light of a predetermined wavelength in addition to a voltage, and thus provide good field effect characteristics. For this purpose, it is necessary to form a light shielding film and optically shield the active layer.

  In order to provide a semiconductor device, the mobility of carriers in the active layer is considered to function sufficiently even if the mobility is not necessarily as high as that of ZnO. The above-described amorphous silicon, single crystal silicon, ZnO, and the like are formed as active layers by various deposition methods. However, a manufacturing process is required in that a light-shielding film is required to suppress the photocarriers. In terms of increasing the area, the ease of increasing the area, and the environmental burden due to the use of heavy metals, it is not always sufficient from the viewpoint of manufacturability, cost, large area adaptability, and the environmental viewpoint. There is no such thing.

On the other hand, titanium dioxide (TiO ₂ ) does not contain heavy metals and does not have a large environmental load. In recent years, titanium dioxide (TiO ₂ ) has been applied to large-area members such as building materials using its photocatalytic properties. Although TiO ₂ is known to generate optical carriers, TiO ₂ has lower optical carrier generation efficiency than silicon, ZnO, and the like, and TiO ₂ is used as an active layer of a field effect semiconductor device. If possible, it will be possible to provide a displayable structural member such as a novel glass or panel containing a large-area field-effect semiconductor, or a large-area display. In addition, the field effect semiconductor device using TiO ₂ can be expected to function well without forming a light-shielding layer. It will be possible to provide structural members.

The inventors of the present invention have so far studied the film formation and characteristics of TiO _2. For example, in Japanese Patent Application Laid-Open No. 2004-288767 (Patent Document 1), the surface at the atomic level of a single crystal substrate of TiO ₂ A control technique is disclosed. On the other hand, although many studies have been made on the use of TiO ₂ as a photocatalyst, the possibility of applying the semiconductor characteristics of TiO ₂ to the active layer of a field effect type semiconductor device has been mostly studied so far. It was not done. Japanese Unexamined Patent Publication No. 2002-198539 (Patent Document 2) discloses a thin film field effect transistor using an organic-inorganic hybrid semiconductor. Patent Document 2 discloses that an organic-inorganic hybrid semiconductor is formed from an organometallic compound containing tin, and discloses that TiO ₂ is used as a gate insulator, but TiO ₂ itself is used as a semiconductor. There is no disclosure of the points to do.
JP 2004-288767 A JP 2002-198539 A

The present invention has been made in view of the above prior art, and an object of the present invention is to provide a field effect semiconductor device including TiO ₂ as an active layer and a method for manufacturing the same.

In view of the above prior art, the present inventors have focused on the TiO ₂ semiconductor active, using TiO ₂ as an active layer forming a channel, if it is possible to control the electrical characteristics by the electric field, in larger area Therefore, investigations have been made based on the idea that structural elements with better optical properties can be provided at a lower cost. As a result, the present inventors have found that semiconductor properties of the TiO ₂ is found to depend largely on the surface of the TiO _2, by controlling the surface properties of TiO ₂ at the atomic level, the electric field of the carrier concentration of TiO ₂ Thus, the present invention has been found out that control is possible. Furthermore, the inventors have found that the characteristics of a semiconductor device using TiO ₂ as an active layer largely depend on the insulating layer, and that the characteristics can be controlled in response to the composition of the insulating layer, leading to the present invention.

That is, according to the first configuration of the present invention,
A field effect semiconductor device containing TiO ₂ as an active layer, wherein the semiconductor device is
A gate electrode;
A TiO ₂ layer forming a channel;
A source electrode and a drain electrode electrically connected to the TiO ₂ layer;
A semiconductor device including an insulating film formed between the gate electrode and the TiO ₂ layer can be provided.

According to the present invention, the TiO ₂ layer preferably includes a rutile or anatase structure having a step-terrace structure, or a rutile or anatase structure having an ultra-smooth surface. The TiO ₂ layer may be a TiO ₂ vapor deposition film. The gate insulating film of the present invention may be formed of a plurality of oxide layers having different oxygen content ratios, and an oxide layer having a low oxygen content ratio may be formed adjacent to the TiO ₂ layer.

According to the second configuration of the present invention,
A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Applying a surface treatment to the semiconductor layer containing TiO ₂ ;
Forming a source electrode and a drain electrode electrically connected to the surface-treated semiconductor layer;
Forming an insulating film on the semiconductor layer;
And a step of forming a gate electrode on the insulating film.

  In the present invention, the insulating film includes a plurality of oxide layers having different oxygen content ratios, and the step of forming the insulating film forms an oxide layer having a low oxygen content ratio in contact with the semiconductor layer. Steps may be included. In the present invention, it is preferable that the step of performing the surface treatment includes a step of providing a step-terrace structure to the semiconductor layer.

According to the third configuration of the present invention,
A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Depositing a semiconductor layer containing TiO ₂ on the substrate;
Forming a source electrode and a drain electrode electrically connected to the semiconductor layer;
Forming an insulating film on the semiconductor layer;
And a step of forming a gate electrode on the insulating film.

  In the present invention, the insulating film includes a plurality of oxide layers having different oxygen content ratios, and the step of forming the insulating film forms an oxide layer having a low oxygen content ratio in contact with the semiconductor layer. Steps may be included.

According to the fourth configuration of the present invention,
A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Forming a source electrode and a drain electrode on a dielectric substrate; forming a semiconductor layer containing TiO ₂ electrically connected to the source electrode and the drain electrode;
Forming a gate insulating film in contact with the semiconductor layer;
And a step of forming a gate electrode on the insulating film.

According to the present invention, the film forming step in the manufacturing method may include a step of intermittently changing the oxygen partial pressure in the step of forming the semiconductor layer containing TiO ₂ . The step of depositing TiO ₂ under the condition of low oxygen partial pressure in the step of intermittently changing the oxygen partial pressure, and the condition of high oxygen partial pressure in the step of intermittently changing the oxygen partial pressure Annealing the deposited TiO ₂ .

Hereinafter, the present invention will be described with reference to embodiments shown in the drawings, but the present invention is not limited to the embodiments described below. FIG. 1 is a diagram showing the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view, and FIG. 1B is a top view. The cross section in FIG. 1A corresponds to the cross sectional structure in which the semiconductor device is cut along the cutting line AA in FIG. The semiconductor device 10 according to the first embodiment of the present invention includes a substrate 12, a source electrode 14 formed on the substrate 12, a drain electrode 16, and a gate insulation formed on the source electrode 14 and the drain electrode 16. A film 18 and a gate electrode 20 formed on the gate insulating film 18 are included. The substrate 12 provides a TiO ₂ layer. Specifically, in the first embodiment of the present invention, a TiO ₂ single crystal substrate is used. A single crystal substrate having a rutile crystal structure and having a crystal plane of (110) can be used.

In addition to (110), (100), (001), (111), or (101) can be used as the crystal plane, and the crystal plane is not limited to a specific crystal plane. In the present invention, when a commercially available single crystal substrate is used, it is necessary to use a commercially available single crystal substrate with an improved surface state by treating it with an etchant. As an etchant that can be used in the present invention, any etchant capable of etching TiO ₂ such as hydrofluoric acid, diluted hydrofluoric acid solution, and hydrofluoric acid-phosphoric acid-nitric acid mixed solution may be used. Any etchant known up to can be used.

  The source electrode 14 and the drain electrode 16 can be formed by using physical deposition methods such as photolithography, vapor deposition using an appropriate mask, sputtering, and laser ablation. As electrode materials, Al, W, Ti, Ni, Mo Or any of these alloys can be used. The film thicknesses of the source electrode 14 and the drain electrode 16 are preferably in the range of 10 nm to 20 nm. In the first embodiment shown in FIG. The present invention is not particularly limited and any thickness can be used as long as it provides an appropriate connection. In the first embodiment of the present invention shown in FIG. 1, particularly for achieving ohmic contact between the source electrode 14 and the drain electrode 16 and the substrate 12 adjacent to the source electrode 14 and the gate insulating film 18 described later. Although the ohmic contact layer is not formed, the ohmic contact layer can be appropriately used in the present invention in relation to a specific electrode material.

A gate insulating film 18 is formed on the source electrode 14 and the drain 16. In the first embodiment of the present invention, a film in which amorphous LaAlO ₃ is deposited by a pulse laser deposition (PLD) method is formed. in use. As a material for forming the gate insulating film 18 used in the present invention, magnesium oxide (MgO), silicon nitride, LaAlO ₃ , tantalum pentoxide, yttrium trioxide, silicon dioxide, aluminum oxide, calcium oxide, diboron trioxide. , Beryllium oxide, barium oxide, or a mixture thereof can be used, and as a deposition method, a laser ablation method, a CVD method, or a sputtering method can also be used. In the first embodiment shown in FIG. 1, the gate insulating film 18 has a thickness of about 450 nm. In the present invention, the gate insulating film has a thickness of about 200 nm to about 1000 nm. More preferably, it can be set in the range of about 300 nm to about 900 nm. Furthermore, in the present invention, the thickness of the gate insulating film can be changed within a range of, for example, about 50 nm to 10 μm, depending on the dielectric material used and device characteristics.

  A gate electrode 20 formed by a masking method is formed on the gate insulating film 18. The gate electrode 20 is formed with a thickness of about 15 nm from Al in the first embodiment of the present invention. However, a metal containing Al, W, Ti, Ni, Mo or any alloy of these metals can be used, and the film thickness should be in the range of about 10 nm to about 20 nm. Can do. Further, the semiconductor device of the present invention is a passivation formed of a material such as polymethyl methacrylate, polystyrene, polycarbonate, silicone, silicon dioxide, or silicon nitride in order to protect each element shown in FIG. 1 from humidity. You may have a film.

  FIG. 1B is a top view of the semiconductor device according to the first embodiment of the present invention. The size of the gate insulating film 18 of the semiconductor device 10 is approximately 700 μm × 1100 μm, the distance between the source and drain electrodes is 200 μm, and the length of the sides of the source electrode 14 and the drain electrode facing each other is 500 μm. Has been. Each structure is formed by a vacuum evaporation method using a mask and a PLD method.

  FIG. 2 shows a second embodiment of the semiconductor device of the present invention. FIG. 2A is a diagram showing a cross-sectional structure, and FIG. 2B is a top view. The cross-sectional structure is a cross-sectional structure cut along a cutting line AA in FIG. In the second embodiment of the semiconductor device of the present invention shown in FIG. 2, in order to improve the insulation of the gate insulating film 18, the gate insulating film 18 is formed by laminating a plurality of materials. Since it has the same configuration as described in FIG. 1, the configuration of the gate insulating film 18 will be described in detail below. The gate insulating film 18 of the semiconductor device 10 shown in FIG. 2 is formed of a first insulating film 18a and a second insulating film 18b. The oxide film described above can be used for both the first insulating film and the second insulating film, and the thickness of the first insulating film is 1 nm to 50 nm, more preferably 1 nm to 30 nm, and still more preferably. It can be 1 nm to 20 nm. In the specific embodiment of the present invention, the first insulating film 18a can be deposited using a laser ablation method. However, as long as an oxide can be deposited, the CVD (Chemical Vapor) can be used. Deposition) can also be used, but the present invention is not limited to the above-described film thickness.

  The second insulating film 18b according to the second embodiment of the present invention can be formed using an oxide that forms the first insulating film. However, in the present invention, it is preferable that the oxygen content (molar ratio) of the oxide forming the first insulating film is lower than the oxygen content of the oxide forming the second insulating film. A favorable trend was seen to give properties. The film thickness of the second insulating film can be used in the range of 300 nm to 1000 nm, and more preferably in the range of 300 nm to 900 nm. The total thickness of the first insulating film and the second insulating film can be about 300 nm to about 1000 nm.

FIG. 3 is a diagram showing a third embodiment of the semiconductor device of the present invention. Similar to FIGS. 1 and 2, FIG. 3A corresponds to a cross-sectional structure taken along the cutting line AA in the top view of FIG. 3B. In the embodiment shown in FIG. 3, a TiO ₂ film 22 is deposited on the substrate 12 using PVD, laser ablation, or CVD methods. At this time, the substrate 12 can be subjected to a treatment with an etchant or a heat treatment in a range of 500 ° C. to 900 ° C. As the substrate 12, a LaAlO ₃ single crystal substrate can be used in the embodiment shown in FIG. In the embodiment shown in FIG. 3, in addition to the LaAlO ₃ single crystal substrate, as the substrate 12, soda lime glass, borosilicate glass, aluminoborosilicate glass, low alkali borosilicate glass, quartz, and quartz with a silicer layer are formed. Glass, glass such as fused silica, silicon wafer, GaAs wafer, TiO ₂ single crystal substrate, and the like can be used, and the substrate 12 is not particularly limited as long as TiO ₂ can be formed satisfactorily. Further, in case of forming a TiO ₂ film by vapor deposition method, the thickness of the TiO ₂ can be in the range of 10 nm to 1 m, more preferably, it may be 10 nm to 50 nm. Further, as described with reference to FIG. 2, a plurality of gate insulating films can be formed on the TiO ₂ film formed by the vapor deposition method to form a semiconductor device.

FIG. 4 is a diagram showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. In the manufacturing method of the present invention shown in FIG. 4, first, a TiO ₂ single crystal substrate is prepared (FIG. 4A), and in the case of processing with an etchant, after processing with the etchant, the source electrode 14 and the drain An electrode 16 is deposited on the substrate 12 using an appropriate mask or photolithography method (FIG. 4B). Thereafter, the gate insulating film 18 is similarly formed using a mask or a photolithography method (FIG. 4C). Thereafter, the semiconductor device of the present invention is manufactured by depositing the gate electrode 20 on the gate insulating film 18 using a similar film forming method. Thereafter, a passivation film is formed as necessary, and the semiconductor device of the present invention can be manufactured.

FIG. 5 is a diagram showing a second embodiment of a method for manufacturing a semiconductor device of the present invention. In the second embodiment of the manufacturing method of the present invention, after etching the TiO ₂ single crystal substrate as necessary (FIG. 5 (a)), the source electrode 14 and the drain electrode 16 are placed in an appropriate mask or It forms using a photolithographic method (FIG.5 (b)). Thereafter, a first insulating film 18a is deposited (FIG. 5C), and further a second insulating film is deposited (FIG. 5D). Thereafter, a gate electrode is formed on the formed second insulating film 18b to form a semiconductor structure (FIG. 5E).

In the present invention, the source electrode and the drain electrode can also be formed below the TiO ₂ layer. When manufacturing a semiconductor structure having this configuration, first, soda-lime glass, borosilicate glass, aluminoborosilicate glass, low alkali borosilicate glass, quartz glass, fused silica, A source electrode and a drain electrode are formed from a conductive material such as a metal material on a dielectric substrate such as a wafer or LaAlO _3, and a semiconductor layer made of TiO ₂ is formed thereon. Thereafter, the gate insulating film can be formed as described above, and the gate electrode can be formed on the formed gate insulating film. Such patterning can be performed using a method using a contact mask known so far or photolithography. Since TiO ₂ used in the present invention has a low degree of photocarrier generation, even a semiconductor device having a positive staggered structure can provide semiconductor activity without using a light shielding layer.

FIG. 6 shows a third embodiment of the method for manufacturing a semiconductor device of the present invention. In the manufacturing method shown in FIG. 3, first, a TiO ₂ film is formed on the substrate 12 to form an active layer (FIG. 6A). In this embodiment, as described above, the substrate is a LaAlO ₃ single crystal substrate, and the substrate 12 is a soda-lime glass, a borosilicate glass, an aluminoborosilicate glass, a low alkali borosilicate glass in which a silylesta layer is formed. Glass such as quartz glass and fused silica, silicon wafer, GaAs wafer, TiO ₂ single crystal substrate, and the like can be used.

In the present invention, when a TiO ₂ film is deposited, the channel characteristics of TiO ₂ can be improved by forming the film while modulating the oxygen partial pressure from a low pressure to a high pressure in order to improve oxygen vacancies in the TiO ₂ film. It was found that it was possible. In the intermittent oxygen modulation deposition method of the present invention, TiO ₂ is deposited under a low oxygen partial pressure, and the deposited TiO ₂ film is annealed under a higher oxygen partial pressure. Then, continuously annealed TiO ₂ film of TiO ₂ is deposited. The pressure corresponding to the low oxygen partial pressure can be in the range of 1.33 × 10 ⁻⁷ Pa to 1.33 Pa, and the pressure corresponding to the high oxygen partial pressure is 1.3 × 10 ⁻⁴ Pa. To 1.33 × 10 ³ Pa, and more suitably 1.33 × 10 ⁻⁴ Pa to 1.3 Pa as the low oxygen partial pressure, and 0.013 as the high oxygen partial pressure. The pressure can be in the range of ˜13 Pa. More preferably, the high oxygen partial pressure can be in the range of 0.013 to 1.3 Pa.

  The low oxygen partial pressure period and the high oxygen partial pressure period depend on the deposition efficiency, but the low oxygen partial pressure period: the high oxygen partial pressure period (3: 5) is 10: The range can be in the range of 1: 1 to 1:10. If the film formation rate is taken into consideration, the range can be in the range of 1: 1 to 1: 5. If the film quality and production efficiency are further taken into consideration, the range is 1: 1 to 1. : 3 range.

Thereafter, the source electrode 14 and the drain electrode are formed on the formed TiO ₂ film (FIG. 6B), and the gate insulating film 18 is formed (FIG. 6C). In the third embodiment of the present invention, as described with reference to FIG. 5, the gate insulating film 18 can be formed by stacking a plurality of insulating films. Thereafter, as shown in FIG. 6D, a gate electrode 20 is formed on the formed gate insulating film 18 to form the semiconductor structure of the present invention.

Hereinafter, the present invention will be described based on specific embodiments, but the present invention is not limited to the examples described below.
(Example 1)
A commercially available polished rutile TiO ₂ single crystal substrate (Shinko Co., Ltd., crystal plane (110)) was heated in the atmosphere at 700 ° C. for 1 hour to obtain a substrate. The surface characteristics of the obtained substrate were observed using an atomic force microscope (AFM: manufactured by Seiko Instruments Inc., SPI3700 and SPA300). FIG. 7 shows the result. As shown in FIG. 7, a step and a terrace surface were observed on the surface of the TiO ₂ single crystal substrate used in Example 1. In addition, as shown in FIG. 7, although the step edge has a rough structure, a step height of 0.32 nm and a flat surface at the atomic level were obtained.

Using a vacuum deposition apparatus (ULVAC VPC260, ultimate vacuum (2.6 × 10 ⁻⁴ Pa) on the obtained TiO ₂ substrate, using a vacuum deposition method using a contact mask, a source electrode having a thickness of 15 nm and A drain electrode was formed, Al was used as the electrode material, and then the target was a LaAlO ₃ single crystal substrate (manufactured by Shinko Co., Ltd.) using a pulsed laser deposition (PLD) method. An amorphous LaAlO ₃ insulating layer was deposited using the following conditions: PLD conditions: deposition temperature = room temperature, oxygen partial pressure = 1.3 Pa, and pulse laser = KrF excimer laser (248 nm, manufactured by Lambda Physics, COMPEX102). , 4 Hz, laser output = 2.8 J / cm ^2, and the number of laser pulses = 60000. the resulting absolute On the layer, an Al electrode having a thickness of 15 nm was formed by vapor deposition using a mask to manufacture a field effect transistor, which has a structure of 90 ° in order to study the mobility anisotropy. A plurality of source electrodes and drain electrodes were formed in different directions.

FIG. 8 shows the characteristics of the obtained field effect transistor at room temperature. FIG. 8A is a plot showing the current (Ids) flowing between the source and the drain with respect to the voltage applied between the source and the drain at various gate voltages, and FIG. 5 is a plot showing a current (Ids) flowing between the source and the drain when V is changed. As shown in FIG. 8A, it was shown that the source-drain current Ids was clearly modulated by the application of the gate voltage (Vg). Further, as shown in FIG. 8 (b), in response to on-off switching operation of the gate voltage, Ids represents the 10 ² or more ON / OFF ratio was found to be clearly have transistor operation . In addition, as shown in FIG. 8B, TiO ₂ functions as a typical n-channel active layer because the channel conductivity is increased by applying a positive bias to the gate electrode. I understand that. Furthermore, when Vg = 0, a relatively large value of Id of 10 ⁻⁸ A was obtained. For this reason, it can be said that the field effect transistor obtained in Example 1 shows normally-on characteristics. Further, from the Vg-Id characteristics shown in FIG. 8A, the mobility in the saturation region was obtained as μ ^sat = 0.03 cm ² / Vs.

(Example 2: Effect of HF surface treatment)
Using the commercially available polished rutile TiO ₂ single crystal substrate used in Experimental Example 1, using a 40% concentration hydrofluoric acid solution (Wako Pure Chemical Industries, reagent special grade), JP 2004-288767 A The substrate surface was etched under the described conditions, and then heat-treated at 700 ° C. for 1 hour to be used as a substrate. In FIG. 9, the result of having observed the surface characteristic of the obtained board | substrate using the atomic force microscope is shown. As shown in FIG. 9, it can be seen that the surface of TiO ₂ exhibits a well-defined linear step and terrace structure and is smoothed at the atomic level. On the obtained TiO ₂ substrate, a field effect transistor structure having a gate insulating film having a thickness of 750 nm made of an amorphous LaAlO ₃ film was produced in the same manner as in Experimental Example 1.

FIG. 10 shows the characteristics of the field-effect transistor obtained in Experimental Example 2 at room temperature. Among the characteristics shown in FIG. 10, (a) and (b) are data of a field effect transistor in which the channel is formed in the direction of the [001] crystal axis, and (c) and (d) are [ -110] shows data when a channel is formed in the direction of the crystal axis. In either case, the on / off ratio of Ids is observed to be about 10 ² or more, and Igs increases as the gate potential Vg increases. In addition, from the value of Ids when Vg = 0, it was shown that normally-on transistor characteristics were shown. When the mobility in the saturation region is calculated from the data in FIGS. 10A and 10C, the mobility is 0.08 cm ² / Vs in the field effect transistor in which the channel is formed in the direction of [001]. When a channel was formed in the [−110] direction, a mobility of 0.03 cm ² / Vs was obtained, and anisotropy was observed in the mobility.

FIG. 11 shows the results obtained for a plurality of formed field effect transistors with respect to mobility in each channel direction. In FIG. 11, the horizontal axis indicates a device number when a plurality of semiconductor devices having different crystal directions are formed using a contact mask, and the vertical axis indicates mobility. As shown in FIG. 11, it can be said that the mobility has significant anisotropy. This mobility anisotropy is considered to reflect the difference in effective mass of electrons expected from the band structure of the rutile structure, and the surface state becomes super flat, so that the band structure of TiO ₂ is It was shown that it is reflected more. In Experimental Example 1, no anisotropy was observed in the channel formation direction, and the mobility in the [001] direction in Experimental Example ₂ was [110] of TiO ₂ obtained in Experimental Example 1. It has been found that the semiconductor characteristics of TiO ₂ are largely dependent on the surface treatment since it is improved by a factor of 2 or more compared to Experimental Example 1 using a substrate.

(Experimental example 3: dependence of transistor characteristics on gate insulating film)
A source electrode and a drain electrode having a film thickness of 15 to 20 nm were formed on the rutile TiO ₂ single crystal (110) ultra-flattened in the same manner as in Example 2 by vacuum deposition of Al in the same manner as in Experimental Example 1. . A gate insulating layer was then deposited using the PLD method. In the PLD method, the gate insulating layer is first irradiated with 500 pulses at a deposition temperature = room temperature, oxygen partial pressure = 1.3 × 10 ⁻³ Pa, laser = KrF excimer laser, output 3 J / cm ² with MgO as a target. Then, a first gate insulating layer (insulating buffer layer) made of MgO and having a thickness of 1 nm was deposited. Thereafter, using a LaAlO ₃ (LaAlO ₃ single crystal, manufactured by Shinko Co., Ltd.) target, deposition temperature = room temperature, oxygen partial pressure = 1.3 Pa, laser = KrF excimer laser, output 2.8 J / cm ² , repetitive By irradiation with 40000 pulses at a frequency of 4 Hz, a second gate insulating layer made of amorphous LaAlO ₃ and having a thickness of 300 nm was formed.

FIG. 12 shows the characteristics of the field-effect transistor manufactured in Experimental Example 3. 12A shows Ids with respect to the source-gate potential, and FIG. 12B shows Ids with respect to the source-drain potential. As shown in FIG. 12A, it was shown that the off current can be reduced to 10 ⁻¹² to 10 ⁻¹¹ A by using the first insulating layer. Further, under the condition that the gate bias is 0 V, the value of Ids is 10 ⁻¹² to 10 ⁻¹¹ , indicating normally-off characteristics. Also, looking at the switching behavior of the transistor, the on / off ratio of the current of Ids obtained exceeding the threshold potential is about 10 ⁴ or more, which is compared with Experimental Example 1 and Experimental Example 2. It was improved by about 10 ^2. The result obtained in Experimental Example 3 is that the MgO buffer layer is inserted between the TiO ₂ layer and the amorphous LaAlO ₃ layer to suppress the charge transfer at the interface between the amorphous LaAlO ₃ and TiO _2. This indicates that it was possible. Further, the mobility at the saturation voltage was 0.05 cm ² / Vs, which was almost the same value as in Experimental Example 2.

(Experimental example 5: Examination of TiO ₂ deposited film)
An anatase TiO ₂ film having a film thickness of 25 nm was formed on a commercially available LaAlO ₃ single crystal substrate (manufactured by Shinko Co., Ltd., crystal plane (001)) using the PLD method. PLD film formation conditions are as follows.

<TiO ₂ (anatase) film>
Target = TiO ₂ powder sintered body (manufactured by Koyo Chemical Co., Ltd., 3N) Deposition substrate temperature = 650 ° C.
Oxygen partial pressure = 1.3 × 10 ⁻⁴ Pa,
KrF excimer laser = output 1.5 J / cm ² , repetition frequency 2 Hz, 10000 pulses.
After the film formation, it was annealed at 400 ° C. for 2 hours in an O ₂ environment of 101.3 kPa and used as a substrate.

Thereafter, an Al source electrode and an Al drain electrode are formed in the same manner as in Experimental Example 1, a LaAlO ₃ film (240 nm) is formed by the PLD method, and an Al gate electrode is formed in the same manner as in Experimental Example 1. A field effect transistor was manufactured. The conditions of the PLD method in forming the LaALO ₃ film are as follows.

<LaAlO ₃ film>
Target = LaALO ₃ single crystal substrate (manufactured by Shinko Co., Ltd.)
Oxygen partial pressure = 1.3Pa
KrF excimer laser = output 2.5 J / cm ² , repetition frequency 10 Hz, 230000 pulses.

FIG. 13 shows an AFM image of the manufactured TiO ₂ (anatase: (001)) film. When the manufactured TiO ₂ (anatase: (001)) film was confirmed by reflection high-energy electron diffraction (RHEED) image, a diffraction image having a fourfold period was clearly confirmed, and an ultra-smooth single crystal anatase ( 001) It was found that a thin film was obtained. FIG. 14 shows the characteristics of the obtained field effect transistor. FIG. 14A is a plot showing the current (Ids) flowing between the source and the drain with respect to the voltage applied between the source and the drain at the gate voltage, and FIG. 14B shows the gate voltage (Vg). ) Is a plot showing the current (Ids) flowing between the source and the drain when changing. As shown in FIG. 14A, the mobility of the carrier in the linear region was about 1 cm ² / Vs, which was a relatively high value. The off-state current is as high as 10 ⁻⁵ A, indicating normally-on characteristics. However, the gate current can be applied to modulate the drain current by one digit or more, and the transistor operation is confirmed even with an anatase TiO ₂ film. I was able to.

(Experimental example 6: Effect of heat treatment on TiO ₂ deposited film)
An anatase TiO ₂ film having a film thickness of 25 nm was formed on a commercially available LaAlO ₃ single crystal substrate (001) in the same manner as in Experimental Example 5 using the PLD method. Thereafter, heat treatment was further performed in the air in an electric furnace at 800 ° C. for 2 hours. As for the crystallinity of TiO ₂ , it was confirmed that an anatase single crystal film was obtained because a diffraction image having a period of 4 times was clearly observed using an RHEED image. Next, a source electrode and a drain electrode having a film thickness of 20 nm are deposited using Al, and a 2 nm MgO film and a 900 nm LaAlO ₃ film are deposited in the same manner as in Experimental Example 3, and a gate having a total film thickness of about 900 nm is deposited. An insulating layer was formed. Further, after that, a gate electrode having a thickness of 20 nm was formed using Al, and a field effect transistor using a TiO ₂ film as a channel layer was manufactured.

FIG. 15 shows the obtained transistor characteristics. FIG. 15A is a plot showing the current (Ids) flowing between the source and the drain with respect to the voltage applied between the source and the drain at the gate voltage, and FIG. It is the plot which showed the electric current (Ids) which flows between source-drain at the time of changing _g ). As shown in FIG. 15B, the field effect transistor obtained in Experimental Example 6 has an on / off current ratio of about 10 ³ or more. Further, as shown in FIG. 15 (b), pinch-off clearly appears, indicating that normally-off transistor operation is exhibited although the off-current is as high as 10 ⁻⁹ A. Further, the mobility in the saturation region was 0.06 cm ² / Vs.

(Experimental example 7: Study on rutile TiO ₂ (100) single crystal substrate)
Using a commercially available rutile TiO ₂ (100) single crystal substrate, HF treatment and annealing treatment were performed in the same manner as in Example 1 to form a surface having a step-terrace structure. FIG. 16 shows an AFM image of the surface of the rutile TiO ₂ (100) single crystal substrate obtained in Experimental Example 7. As shown in FIG. 16, the rutile TiO ₂ (100) single crystal substrate obtained in Experimental Example 7 is also formed with a good step-terrace structure.

A source electrode and a drain electrode having a thickness of 20 nm were formed on a rutile TiO ₂ (100) single crystal substrate having a step-terrace structure by vacuum deposition using a mask in the same manner as in Example 1. Thereafter, a KrF excimer laser, ² J / cm ² , 4 Hz, 100,000 pulses of PLD were applied, and a LaAlO ₃ insulating layer having a thickness of 480 nm was deposited under the condition of a deposition rate of 0.0048 nm / pulse. A gate electrode was formed on the deposited LaAlO ₃ insulating layer using a mask method to produce an inverted staggered field effect transistor.

FIG. 17 shows the characteristics of the field effect transistor obtained in Experimental Example 7. FIG. 17A is a graph plotting Ids (× 10 ⁻⁶ A) (left scale) and Vd (V) (right scale) with Vd (V) as the horizontal axis. FIG. 17B shows mobility when a channel is formed in a direction along the crystal axis [010] or [001]. As shown in FIG. 17A, when rutile TiO ₂ is used, the on / off ratio is about 10 and the mobility is about 0.06 cm ² / Vs, giving semiconductor characteristics. It was found.

In addition, field effect transistors were manufactured by changing the channel formation direction to be parallel to the rutile TiO ₂ crystal axes [010] and [001], and the mobility of each field effect transistor was measured. The result is shown in FIG. As shown in FIG. 17B, the channel mobility of each field effect transistor was found to exhibit a clear anisotropy, indicating that semiconductor characteristics were developed.

(Experimental example 8: Study on rutile TiO ₂ (101) single crystal substrate)
The same examination as in Experimental Example 7 was performed using rutile TiO ₂ (101) as a single crystal substrate. The result is shown in FIG. FIG. 18A is a graph plotting Ids (× 10 ⁻⁶ A) (left scale) and Vd (V) (right scale) with Vd (V) as the horizontal axis. FIG. 18B shows the mobility when a channel is formed in the direction along the crystal axis [010] or [−101]. As shown in FIG. 18A, when rutile TIO ₂ was used as a channel, an on / off characteristic of 10 ² or more was obtained. On the other hand, the mobility was lower than the rutile TIO ₂ (100) shown in FIG. 17, and was a value of about 0.01 cm ² / Vs. Further, as shown in FIG. 18B, no significant difference was observed in the mobility in the channel direction with respect to the crystal plane direction. The reason is considered that the absolute value of mobility is small.

(Experimental example 9: Examination of oxygen partial pressure modulation film formation)
A field effect transistor using an anatase TiO ₂ thin film as a channel was manufactured as follows.

<Board>
LaAlO ₃ single crystal substrate (001)
<Anatase TiO ₂ (001)>
Deposition temperature Ts: 650 ° C.
Oxygen partial pressure PO ₂ : 0.133 Pa (1 × 10 ⁻³ Torr, during annealing,
5 min) /1.33×10 ⁻⁴ Pa (1 × 10 ⁻⁶ To
rr, during deposition, 3 min):
Oxygen partial pressure modulation film formation, deposition / annealing is one cycle
Total 20 cycles
Laser conditions: KrF excimer laser, 1.5 J / c
m ² , 1 Hz, 6000 pulses,
Film thickness: 20 nm
HF treatment: same as Experimental Example 1,
Annealing after film formation: oxygen pressure = 101.325 kPa, 700 ° C., 2 hours

FIG. 19 shows a time chart of oxygen partial pressure modulation film formation used in Experimental Example 9 and conditions of film formation speed. During the deposition period shown in FIG. 19, the TiO ₂ film was grown at a deposition rate of 1 nm (about 0.333 nm / min).

FIG. 20 shows a reflection high-energy electron diffraction (RHEED) image (a) and an AFM image (b) of the surface of anatase TiO ₂ (100) obtained by oxygen partial pressure modulation film formation. As shown in FIG. 20 (a), the manufactured TiO ₂ film clearly showed a diffraction pattern having a fourfold period peculiar to anatase TiO ₂ (001). Further, as a result of surface observation by AFM, as shown in FIG. 20B, it was found that an ultra-smooth and ultra-smooth single crystal anatase (001) thin film having a step-terrace structure was obtained. .

<Field effect transistor>
A 15 nm Al film was deposited on the anatase TiO ₂ (001) single crystal film by using a mask method to manufacture a source electrode and a drain electrode. A LaAlO ₃ / MgO gate insulating layer was formed on the formed source electrode and drain electrode under the following conditions, and a 15 nm gate electrode was formed in a gate insulating layer using a mask method.
Laser conditions: KrF excimer laser, ² J / cm ² ,
Deposition temperature = room temperature
Oxygen partial pressure = 1.33 Pa,
MgO: 10 Hz, 10,000 pulses,
LaAlO ₃ : 15 Hz, 200000 pulses,
Gate insulating layer thickness: 600 nm,

<Characteristics of field effect transistor>
The characteristics of the manufactured field effect transistor were measured in the same manner as in Experimental Example 1. The result is shown in FIG. FIG. 21A shows the Ids-Vgs characteristic, FIG. 21B shows the Ids-Vgs characteristic, and FIG. 21C shows the Ids-Vgs characteristic. As shown in FIG. 21, the manufactured field-effect transistor was normally off and showed a good on / off characteristic exceeding 10 ⁵ , and its mobility was 0.37 cm ² / Vs. That is, the anatase type TiO 2 ₍₀₀₁₎ single crystal film, by intermittently annealed at different oxygen partial pressure, it is possible to improve the channel characteristics of anatase TiO 2 ₍₀₀₁₎ single crystal film It was found. The reason is considered to be that a TiO ₂ single crystal film with improved crystallinity and few oxygen vacancies could be manufactured by intermittently modulating the oxygen partial pressure during film formation.

(Experimental example 10: Comparative example)
A field effect transistor was manufactured and evaluated in the same manner as in Experimental Example 1 using a rutile-type TiO ₂ single crystal substrate (a substrate in which a step structure was not observed by AFM) that was polished only. Transistor operation could not be confirmed.

As described above, it has been shown that TiO ₂ functions sufficiently as an active layer of a field effect transistor by performing a surface treatment. In addition, as described in the experimental example, since the transistor effect could not be observed in the TiO ₂ substrate that was not subjected to the surface treatment at all, TiO ₂ changed its characteristics by the surface treatment, and no response was obtained depending on the gate insulating layer. It has been shown to give both mullion or normally-off characteristics. Further, by adopting a film forming method in which the oxygen partial pressure is intermittently modulated so as to reduce oxygen vacancies when forming the TiO ₂ film, the characteristics of the semiconductor device using the TiO ₂ film as a channel can be improved. It was shown that it can be done.

In FIG. 22, the result obtained about Experimental example 1-Experimental example 9 is shown collectively. As shown in FIG. 22, the field effect transistor using TiO ₂ as an active layer according to the present invention can be driven with good field effect, and when an anatase TiO ₂ film is used as a channel, Approximately 10 or more on / off characteristics were exhibited. As for mobility, it was shown that a value of about 1 cm ² / Vs was obtained with anatase TiO ₂ . Further, it has been found that the off-current varies depending on the type of the insulating film, but varies depending on the characteristics of the insulating film from a value that provides normally-off characteristics to a value that provides normally-on characteristics. Note that the present invention can be applied to both the forward stagger type and the reverse stagger type device structures.

As described above, the present invention can provide a field effect semiconductor device using TiO ₂ and a method for manufacturing the same, and can expect to obtain field effect characteristics without the need for a light shielding film. Therefore, it is considered that a semiconductor device having a novel structure that can be widely applied to applications requiring optical characteristics can be provided.

The figure which showed the structure of 1st Embodiment of the semiconductor device of this invention. The figure which showed 2nd Embodiment of the semiconductor device of this invention. The figure which showed 3rd Embodiment of the semiconductor device of this invention. The figure which showed 1st Embodiment of the manufacturing method of the semiconductor device of this invention. The figure which showed 2nd Embodiment of the manufacturing method of the semiconductor device of this invention. The figure which showed 3rd Embodiment of the manufacturing method of the semiconductor device of this invention. It shows an AFM image of the surface of the TiO ₂ single crystal substrate. The figure which showed the characteristic at room temperature of the field effect transistor obtained by this invention. The figure which showed the AFM image of the board | substrate containing the step-terrace shape obtained by this invention. The figure which showed the characteristic in the room temperature of the field effect transistor obtained by this invention. The figure which showed the result obtained about the field effect transistor which formed the mobility about each channel direction in duplicate. The figure which showed the characteristic of the field effect transistor obtained by this invention. TiO ₂ prepared (anatase: 001) shows an AFM image of the film. It shows the characteristics of the field effect transistor obtained using TiO ₂ deposition film (anatase) as the semiconductor layer. Using the anatase type TiO ₂ film, showing characteristics of a field effect transistor using the laminated film of MgO and LaAlO ₃ as a gate insulating film FIG. It shows an AFM image of the surface of the rutile _TiO 2 (100) single crystal substrate obtained in Experimental Example 7. The figure which showed the characteristic of the field effect transistor obtained in Experimental example 7. FIG. Shows the characteristics of the field effect transistors fabricated using the rutile TiO 2 ₍₁₀₁₎ as the single crystal substrate. The figure which showed the time chart of the oxygen partial pressure modulation film-forming of this invention, and the conditions of film-forming speed | rate. It shows an AFM image of the reflection high energy electron diffraction (RHEED) images and the surface of the oxygen partial pressure modulation formed by obtained anatase type _TiO 2 (001). Shows the characteristics of the field effect transistor using the oxygen partial pressure modulation anatase resulting was prepared by depositing TiO 2 ₍₀₀₁₎ film as a channel. The figure which showed the characteristic of the semiconductor device obtained by this invention.

Explanation of symbols

10 ... semiconductor device, 12 ... substrate, 14 ... Source electrode, 16 ... drain electrode, 18, 18a, 18b ... gate insulating film, 20 ... gate electrode, 22 ... TiO ₂ film

Claims (12)

A field effect semiconductor device containing TiO ₂ as an active layer, wherein the semiconductor device is
A gate electrode;
A TiO ₂ layer forming a channel;
A source electrode and a drain electrode electrically connected to the TiO ₂ layer;
A semiconductor device including an insulating film formed between the gate electrode and the TiO ₂ layer. The semiconductor device according to claim 1, wherein the TiO ₂ layer includes a rutile or anatase structure having a step-terrace structure, or a rutile or anatase structure having an ultra-smooth surface. The semiconductor device according to claim 1, wherein the TiO ₂ layer is a vapor deposition film of TiO ₂ . The gate insulating film is formed from a plurality of oxide layers having different oxygen content ratios, and an oxide layer having a low oxygen content ratio is formed adjacent to the TiO ₂ layer. 2. A semiconductor device according to item 1. A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Applying a surface treatment to the semiconductor layer containing TiO ₂ ;
Forming a source electrode and a drain electrode electrically connected to the surface-treated semiconductor layer;
Forming an insulating film on the semiconductor layer;
Forming a gate electrode on the insulating film. A method for manufacturing a semiconductor device.   The insulating film includes a plurality of oxide layers having different oxygen content ratios, and the step of forming the insulating film includes a step of forming an oxide layer having a low oxygen content ratio in contact with the semiconductor layer. Item 6. The manufacturing method according to Item 5.   The manufacturing method according to claim 5, wherein the surface treatment includes a step of providing a step-terrace structure to the semiconductor layer. A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Depositing a semiconductor layer containing TiO ₂ on the substrate;
Forming a source electrode and a drain electrode electrically connected to the semiconductor layer;
Forming an insulating film on the semiconductor layer;
Forming a gate electrode on the insulating film. A method for manufacturing a semiconductor device.   The insulating film includes a plurality of oxide layers having different oxygen content ratios, and the step of forming the insulating film includes a step of forming an oxide layer having a low oxygen content ratio in contact with the semiconductor layer. Item 9. The manufacturing method according to Item 8. A method of manufacturing a field effect semiconductor device including TiO ₂ as an active layer,
Forming a source electrode and a drain electrode on a dielectric substrate; forming a semiconductor layer containing TiO ₂ electrically connected to the source electrode and the drain electrode;
Forming a gate insulating film in contact with the semiconductor layer;
Forming a gate electrode on the insulating film. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the semiconductor layer containing TiO ₂ includes a step of intermittently changing an oxygen partial pressure. The step of depositing TiO ₂ under the condition of low oxygen partial pressure in the step of intermittently changing the oxygen partial pressure, and the condition of high oxygen partial pressure in the step of intermittently changing the oxygen partial pressure The method of manufacturing a semiconductor device according to claim 11, further comprising: annealing the TiO ₂ deposited in step 1.

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