JPWO2005104540A1 - Receiving device, receiving system using the receiving device, and receiving method thereof - Google Patents

Abstract

In receiving apparatus 100, demodulating sections 101 and 102 that receive the received signals of each broadcasting system as input and output demodulated data and timing clocks synchronized with the demodulated data, and two timing clocks output from demodulating sections 101 and 102, high-speed timing A clock generation unit 103 that outputs a clock and a low-speed timing clock to the AV decoder 107 and outputs a control signal for multiplexing the two demodulated data output from the demodulation units 101 and 102, and 2 based on this control signal. The AV decoder 107 includes a multiplexing unit 104 that multiplexes the demodulated data and outputs the multiplexed data to the AV decoder 107. The AV decoder 107 receives the multiplexed data output from the receiving apparatus 100 and the timing clock, and processes the video / audio signals of each broadcast.

Description

  The present invention relates to a receiving apparatus for receiving a plurality of digital broadcasts of different broadcasting systems or the same broadcasting system, such as satellite digital broadcasting and terrestrial digital broadcasting, a receiving system using the receiving apparatus, and a receiving method thereof.

  In recent years, with the advancement of digital transmission technology and semiconductor integrated technology, digitization of broadcasting and communication has been promoted.

  A receiving device and a receiving system that simultaneously receive a plurality of broadcasts are a plurality of demodulation units that perform demodulation in accordance with each broadcast method of a received signal, a multiplexing unit that multiplexes and outputs demodulated data output from each demodulation unit, It comprises a multiplexed data separator that separates and outputs demodulated data to be decoded from the multiplexed demodulated data, and a decoder that decodes and outputs the demodulated data separated by the multiplexed data separator.

  An example of such a digital broadcast receiving apparatus is disclosed in Japanese Patent Application Laid-Open No. 11-122556.

  In order to receive a plurality of broadcasting systems simultaneously, this known digital broadcast receiving apparatus receives a plurality of demodulating units according to each broadcasting system and demodulated data output from the plurality of demodulating units in units of transport packets, A multiplexing unit that multiplexes in units of transport packets at a rate equal to or higher than the total transport packet transmission rate of the broadcasting system, and a multiplexed data separation unit that separates and outputs the demodulated data decoded from the multiplexed demodulated data ing.

  However, in a known digital broadcast receiving apparatus, demodulated data output from a plurality of demodulator units corresponding to each broadcast method is multiplexed at a rate equal to or higher than the total transport packet transmission rate of each broadcast method in units of transport packets. However, a large-scale storage circuit such as a memory for delaying each demodulated data is required, and the circuit scale increases, so that there is a problem that it becomes expensive. Further, a publicly known digital broadcast receiver has not disclosed a specific method for multiplexing demodulated data.

  Therefore, the present invention provides an inexpensive receiving device that can multiplex two demodulated data without adding a large-scale memory and adding a small circuit, a receiving system using the receiving device, and a receiving method thereof. It is intended to do.

  In order to achieve this object, the present invention provides, in the receiving apparatus, two demodulating units that receive the received signals of each broadcasting system and output demodulated data and timing clocks synchronized with the demodulated data, and output from these demodulating units. A clock generation unit that outputs two timing clocks as a high-speed timing clock and a low-speed timing clock to the AV decoder, and outputs a control signal for multiplexing the two demodulated data output from the demodulation unit, and based on the control signal And a multiplexing unit that multiplexes the two demodulated data and outputs the multiplexed data to the AV decoder. In the AV decoder, the video / audio signals of each broadcast are processed with the multiplexed data output from the receiving device and the timing clock as inputs.

  With the above configuration, the present invention makes it possible to multiplex two demodulated data with the addition of a small circuit without using a large-scale memory, thereby realizing cost reduction and low power consumption by reducing the circuit scale. It is possible to synchronize the timing clock synchronized with the multiplexed demodulated data with a single timing clock such as a high-speed timing clock or a higher-speed internal timing clock. It is possible to relax the timing constraints of the apparatus, and it is possible to construct a cheaper system.

It is a block diagram of the receiver in Example 1 of this invention. It is a block diagram of the clock generation part of the receiver. It is a block diagram of the speed determination part of the receiver. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 2 of this invention. It is a block diagram of the clock generation part of the receiver. It is a block diagram of the multiplexing part of the receiver. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 3 of this invention. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 4 of this invention. It is a block diagram of the receiver in Example 5 of this invention. It is a flowchart of the receiving method of the receiving apparatus.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of a receiving apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 100 denotes a receiving device. The receiving device 100 receives two received signals A and B of different broadcast systems or digital broadcasts of the same broadcast method, and multiplex data obtained by multiplexing respective demodulated data outputs. The high-speed timing clock and the low-speed timing clock synchronized with the multiplexed data are output. Reference numeral 107 denotes an AV decoder (an example of a video signal processing device). The AV decoder 107 receives the multiplexed data, the high-speed timing clock, and the low-speed timing clock output from the receiving device 100 as input, and converts the multiplexed data into two demodulated data. In this case, one or both of the two demodulated data are used as received data and processed into video / audio signals for each broadcast.

  The receiving apparatus 100 includes first and second demodulation units 101 and 102, a speed determination unit 105, a first selection unit 106, a clock generation unit 103, and a multiplexing unit 104.

  The first and second demodulating sections 101 and 102 receive two received signals A and B, respectively, output demodulated data D1 and D2 to the first selecting section 106, and timing clocks T1 and T2 synchronized therewith, respectively. T2 is output to the first selection unit 106 and the speed determination unit 105.

  The speed determination unit 105 receives the two timing clocks T1 and T2 output from the demodulation units 101 and 102, compares the respective speeds, determines which clock is higher, and the determination result. Is output to the first selection unit 106 as the control signal C3.

  Based on the control signal C3 (determination result) output from the speed determination unit 105, the first selection unit 106 is one of timing clocks T1 and T2 output from the first and second demodulation units 101 and 102. One is selected as the high-speed timing clock TH and output to the clock generation unit 103, the other is output as the low-speed timing clock TL to the clock generation unit 103, and output from the first and second demodulation units 101 and 102. One of the demodulated data D1 and D2 is selected as the high-speed demodulated data DH and output to the multiplexing unit 104, and the other is output to the multiplexing unit 104 as the low-speed demodulated data DL.

  The clock generation unit 103 receives the high-speed timing clock TH and the low-speed timing clock TL output from the first selection unit 106 (based on the two timing clocks output from the demodulation units 101 and 102), A timing clock for multiplexed demodulated data DH and DL, that is, a high-speed timing clock for high-speed demodulated data DH and a low-speed timing clock for low-speed demodulated data DL are generated and output to the AV decoder 107 and two demodulated data DH and DL are generated. A control signal for multiplexing is output to multiplexing section 104.

  The multiplexing unit 104 multiplexes the demodulated data DH and DL output from the first selection unit 106 in units of bytes based on the control signal output from the clock generation unit 103, and outputs the multiplexed data to the AV decoder 107. .

  Note that the first and second demodulation units 101 and 102 are demodulation units adapted to the broadcast systems of the received signals A and B.

  A more specific circuit configuration of the clock generator 103 is shown in FIG.

  The clock generation unit 103 receives the high-speed timing clock TH and the low-speed timing clock TL output from the first selection unit 106, and as shown in FIG. The data is output to the decoder 107.

  As illustrated in FIG. 2, the clock generation unit 103 includes a delay unit 201, an edge detection unit 202, a second selection unit 203, and a control signal generation unit 204.

  The delay unit 201 inputs a low-speed timing clock TL, delays it, and outputs the timing clock TLD to the second selection unit 203.

  The edge detection unit 202 receives the high-speed timing clock TH and the low-speed timing clock TL as inputs, detects the simultaneous rising of the timing clock, and sends the selection signal SL to the second selection unit 203 when the rising is at the same time. A logical value “1” (an example of a second logical value) is output, and if different, a logical value “0” (an example of an inverted value of the second logical value) is output.

  The second selection unit 203 receives the low-speed timing clock TL and the timing clock TLD output from the delay unit 201, and selects two timing clocks based on the selection signal SL. That is, the selection signal SL has a logical value “ The delayed timing clock TLD is selected when it is “1”, the low-speed timing clock TL is selected when it is the logical value “0”, and is output to the control signal generator 204 and the AV decoder 107 as the low-speed timing clock.

  The control signal generation unit 204 receives the low-speed timing clock and the high-speed timing clock TH output from the second selection unit 203, and uses the multiplexing unit as a control signal for identifying the demodulated data DH and DL selected by the multiplexing unit 104. When the high-speed timing clock TH rises to 104, the logic value “1” (an example of the third logic value) is output. When the low-speed timing clock rises, the logic value “0” (the inverted value of the third logic value) Example) is output, and the value is held if there is no rising edge.

  A more specific circuit configuration of the speed determination unit 105 is shown in FIG.

  As shown in FIG. 3, the speed determination unit 105 includes first and second clock counting units 301 and 302 and an identification unit 303.

  The first and second clock counting units 301 and 302 receive two timing clocks T1 and T2 output from the first and second demodulation units 101 and 102, respectively, and the clocks of the timing clocks T1 and T2 are input. The number of rising edges (the number of clocks) N1 and N2 is counted, and the (self) initialization signal is output to the identification unit 303 as the control signals C1 and C2 at a predetermined cycle n, and either one of the control signals (initialization) Signals) are initialized by the outputs of C1 and C2.

  The identification unit 303 receives the control signals C1 and C2 output from the first and second clock counting units 301 and 302, respectively, and identifies a speed determination result and outputs a control signal (identification) to the first selection unit 106. When the control signal C1 is input to the first selection unit 106 first or simultaneously as the signal C3, “1” (an example of the first logical value) is output, and the control signal C2 is input first. In this case, “0” (an example of the inverted value of the first logic value) is output.

  As shown in FIG. 3, the count values N1 and N2 of the first and second clock counters 301 and 302 and their control signals (initialization signals) C1 and C2 are output.

  The operation of the receiving apparatus configured as described above will be described. FIG. 4 is a timing chart of each unit in the receiving apparatus 100 of FIG.

  The first demodulator 101 performs demodulation processing in conformity with the broadcasting system, outputs a timing clock T1 and demodulated data D1 (A [1], A [2], A [3],...) Synchronized therewith, The second demodulator 102 performs a demodulation process in conformity with the broadcasting system and outputs a timing clock T2 and demodulated data D2 (B [1], B [2], B [3],...) Synchronized therewith. .

  The clock counting units 301 and 302 of the speed determination unit 105 count the rising edges of the timing clocks T1 and T2, and the count value outputs N1 and N2 increase as shown in FIG. Further, since the predetermined cycle is n, when N1 and N2 are equal to the cycle n (time 1 and time 2 in the figure), control signals (initialization signals) C1, C1 for initializing the clock counting units 301 and 302 are initialized. A logical value “1” is output as C2. Further, when either one of the clock counting units 301 and 302 reaches the cycle n, both the clock counting units 301 and 302 are initialized.

  The identification unit 305 of the speed determination unit 105 determines which clock counting unit 301, 302 has reached the predetermined period n first, that is, which of the control signals C1, C2 has the logical value “1” first. Thus, a high-speed output clock is identified from among the timing clocks T1 and T2, and a control signal C3 indicating the result is output. In the first embodiment, as the control signal C3, when the timing clock T1 is high speed, that is, when the control signal C1 is input first or simultaneously, “1” is output, and the timing clock T2 is high speed, that is, the control signal C2 is first. When “0” is input, “0” is output.

  As shown in FIG. 4, when the logical value of the control signal C3 is “1”, the first selection unit 106 outputs the timing locks T1 and T2 as a high-speed timing clock TH and a low-speed timing clock TL, respectively. Demodulated data D1 and D2 are output as high-speed demodulated data DH and low-speed demodulated data DL, respectively. When the logical value of the control signal C3 is “0”, the opposite is true.

  The clock generation unit 103 outputs the input high-speed timing clock TH as it is to the AV decoder 107 as a high-speed timing clock.

  The delay unit 201 of the clock generation unit 103 delays the low-speed timing clock TL and outputs the timing clock TLD. The edge detection unit 202 compares the timing clocks TH and TL, and outputs a logical value “1” when the rising edge is the same time as the selection signal SL, and outputs a logical value “0” when they are different. The second selection unit 203 selects the delayed timing clock TLD when the selection signal SL is a logical value “1”, selects the timing clock TL when the selection signal SL is a logical value “0”, and selects an AV decoder as a low-speed timing clock. It outputs to 107.

  The control signal generation unit 204 of the clock generation unit 103 outputs a logical value “1” as the control signal output to the multiplexing unit 104 when the high-speed timing clock rises, and outputs a logical value “0” when the low-speed timing clock rises. If there is no rising edge, the value is held.

  Multiplexer 104 selects high-speed demodulated data DH when the control signal output from control signal generator 204 has a logical value “1”, and selects low-speed demodulated data DL when the logical value is “0”. As shown in FIG. 4, multiplexed data is generated from the demodulated data DH and DL and output to the AV decoder 107.

  As described above, according to the first embodiment, a small circuit is added without using a storage unit (large-scale memory) that stores the two demodulated data D1 and D2 output from the two demodulation units 101 and 102. Thus, the two demodulated data D1 and D2 can be multiplexed, and the circuit scale and cost can be reduced by downsizing the receiving apparatus 100. At the same time, by reducing the number of output pins through multiple outputs, the cost can be reduced by downsizing the receiving apparatus. Further, since demodulated data is sequentially output without being stored in a memory or the like, it is possible to avoid deterioration of jitter performance and to avoid an increase in response time.

  Further, according to the first embodiment, even when the speed of the demodulated data D1 and D2 is changed or unknown (when the synchronized timing clocks T1 and T2 are changed or unknown), the speed determination unit 105 performs high-speed timing. Based on this, the first selection unit 106 selects one of the timing clocks T1 and T2 output from the demodulation units 101 and 102 as a high-speed timing clock TH and outputs the selected one. One of the demodulated data D1 and D2 output from the first and second demodulation units 101 and 102 is selected and output as the high-speed demodulated data DH, and the other is output as the low-speed timing clock TL. By being output as demodulated data DL, one system multiplexer 104 and clock generator 103 It becomes possible to sense, it is possible to reduce the circuit scale.

  Further, according to the first embodiment, by using the clock counting units 301 and 302 as the speed determining unit 105, the timing clocks T1 and T2 can be easily compared with a small circuit.

  According to the first embodiment, when the two timing clocks T1 and T2 rise simultaneously, the timing clock TLD delayed by the delay unit 201 is selected as the low-speed timing clock, and the rising timing of the low-speed timing clock is delayed, The two demodulated data D1 and D2 can be multiplexed without being lost, and the reliability can be improved.

  Note that the jitter performance can be improved by changing the predetermined period n according to the frequency of the clock timings T1 and T2, and the clock counters 301 and 302 can be improved by setting the period n to a multiplier of 2. The generation unit of the initialization signals (control signals C1 and C2) can be simplified, and the circuit can be further downsized.

  In addition, when the speeds of the timing clocks T1 and T2 are known in advance, the circuit can be further downsized by removing the speed determination unit 105 and the first selection unit 106. Needless to say, if the speed of the timing clocks T1 and T2 can be identified from the outside, the circuit can be downsized by removing only the speed determination unit 105.

  Further, the polarity and logical value of the control signal shown in the first embodiment are not limited to this.

  Hereinafter, the receiving apparatus and the receiving method according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the first embodiment shown in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof is omitted.

  In the second embodiment, a clock generation unit 501 is provided instead of the clock generation unit 103 of the first embodiment, and a multiplexing unit 503 is provided instead of the multiplexing unit 104.

  The clock generation unit 501 according to the second embodiment receives the count values N1, N2, the control signals (initialization signals) C1, C2, and the control signal (identification signal) C3 from the speed determination unit 105, and receives the control signal (identification signal) C3. A high-speed timing clock TH is input, a high-speed timing clock TH is output as a high-speed timing clock, and a clock that is synchronized with the other low-speed timing clock TL and an average frequency equal to the high-speed timing clock TH is generated as a low-speed timing clock. And output.

  In addition, the multiplexing unit 503 according to the second embodiment inputs the high-speed demodulated data DH, the low-speed demodulated data DL, and the low-speed timing clock TL from the first selection unit 106, and inputs the low-speed timing clock from the clock generation unit 501. Based on the low-speed timing clock, the high-speed demodulated data DH and the low-speed demodulated data DL are selected to generate multiplexed data in units of bytes.

  A specific circuit configuration of the clock generator 501 is shown in FIG.

  As shown in FIG. 6, the clock generation unit 501 includes a third selection unit 601, a storage unit 602, a mask signal generation unit 603, a mask unit 604, and a logic inversion circuit 605.

  The third selection unit 601 receives the count values N1 and N2 and the control signal C3 from the speed determination unit 105. When the control signal C3 is a logical value “1”, that is, when the timing clock T1 is high speed, When the count value N1 of the clock counting unit 301 is selected and the control signal C3 is a logical value “0”, that is, when the timing clock T2 is high speed, the count value N2 of the second clock counting unit 302 is selected as the count value NH. And output to the mask signal generator 603.

  The storage unit 602 receives the count values N1 and N2, the control signals (initialization signals) C1 and C2 and the control signal C3 from the speed determination unit 105, and when the control signals (initialization signals) C1 and C2 are input. In addition, when the control signal C3 is the logical value “1” (when the timing clock T1 is high speed), the count value N2 output from the second clock counter 302 connected to the low speed timing clock T2 is used as the control value M. When the control signal C3 is a logical value “0” (when the timing clock T2 is high speed), the count value N1 output from the first clock counter 301 connected to the low speed timing clock T1 is controlled. The value M is stored and output to the mask signal generation unit 603.

  The mask signal generation unit 603 receives the count value NH output from the third selection unit 601 and the control value M output from the storage unit 602, and the count value NH of the third selection unit 601 is used as the mask signal. When the value is equal to or less than the control value M, “1” (an example of the fourth logical value) is output to the mask unit 604, and when the count value NH of the third selection unit 604 is greater than the control value M, “0” (the first value) 4) is output to the mask unit 604.

  The mask unit 604 receives the high-speed timing clock TH output from the first selection unit 106 and the mask signal output from the mask signal generation unit 603, and outputs the low-speed timing clock to the AV decoder 107 and the multiplexing unit 503. When the mask signal is “1”, a high-speed timing clock TH is output. When the mask signal is “0”, a logical value “L” is output.

  The logic inversion circuit 605 logically inverts the high-speed timing clock TH output from the first selection unit 106 and outputs the result to the AV decoder 107 as a high-speed timing clock.

  A specific circuit configuration of the multiplexing unit 503 is shown in FIG.

  As illustrated in FIG. 7, the multiplexing unit 503 includes a FIFO unit 701 and a fourth selection unit 702.

  The FIFO unit 701 sequentially writes the low-speed demodulated data DL input from the first selection unit 106 at the timing of the low-speed timing clock TL input from the first selection unit 106, and the low-speed timing clock output from the clock generation unit 501 And output to the fourth selection unit 702.

  The fourth selection unit 702 selects the low-speed demodulated data DL output from the FIFO unit 701 when the low-speed timing clock output from the clock generation unit 501 is a logical value “1”, and selects the low-speed demodulated data DL when the logical value is “0”. Selects the high-speed demodulated data DH to generate multiplexed data and outputs it to the AV decoder 107.

  The operation of the receiving apparatus configured as described above will be described with reference to FIG.

  The storage unit 602 stores the count output N2 of the second clock counter 302 connected to the low-speed timing clock T2 when the count output N1 of the counter 301 at time 1 or time 2 reaches a predetermined period n. Is stored as a control value M. In the case of FIG. 8, m is stored. The storage unit 602 is updated in accordance with the control signal C1 (initialization timing) of the first clock counting unit 301.

  In the third selection unit 601, the count value N1 of the first clock counting unit 301 connected to the high-speed timing clock T1 is selected by the control signal C3 and output as the count value NH.

  In the mask signal generation unit 603, the count value NH that changes in synchronization with the high-speed timing clock T1 output from the selection unit 601 is compared with the control value M stored in the storage unit 602, and the count value NH is the control value M. In the following cases, a logical value “1” is output as a mask signal, and when it is greater than the control value M, a logical value “0” is output. In the case of FIG. 8, the logical value is “1” until the count value NH reaches m. The mask unit 604 outputs a high-speed timing clock TH as a low-speed timing clock when the mask signal is a logical value “1”, and a logical value “L” when the mask signal is a logical value “0”. The logic inversion circuit 605 logically inverts the high-speed timing clock TH and outputs it as a high-speed timing clock.

  The low-speed demodulated data DL is written in the FIFO unit 701 at the timing of the low-speed timing clock TL, delayed by a predetermined time, and then read out at the timing of the low-speed timing clock, so that the output of the FIFO unit 701 is as shown in FIG. A number equal to the control value M is output in bursts in synchronization with the low-speed timing clock. The fourth selection unit 702 outputs the multiplexed data by selecting the output of the FIFO unit 701 when the low-speed timing clock is a logical value “1”, and selecting the high-speed demodulated data DH when the logical value is “0”. To do.

  As described above, according to the second embodiment, the two demodulated data DH and DL output from the two demodulating units 101 and 102 are synchronized with a single timing clock synchronized with a high-speed timing clock, and the multiplexed output timing is synchronized. Are equal intervals, signal processing for processing multiple outputs becomes easy, and the configuration of the entire receiving apparatus can be simplified. In addition, since the timing restrictions of the AV decoder 107 at the subsequent stage can be relaxed, an inexpensive one can be used, and the entire receiving system can be provided at a low cost.

  Further, according to the second embodiment, a low-speed timing clock having the same average frequency as that of the low-speed timing clock can be generated by a small circuit with reference to the high-speed timing clock.

  Further, according to the second embodiment, even if the speeds of the two demodulated data DH and DL output from the two demodulating units 101 and 102 and the two timing clocks TH and TL synchronized therewith are unknown, the speed determination is performed. Can be selected.

  In the second embodiment, the clock generation unit 501 uses the count values N1, N2, the control signals (initialization signals) C1, C2, and the control signal C3 obtained by the speed determination unit 105, and the storage unit 602 Although the control value M is obtained, a high-speed timing clock TH and a low-speed timing clock TL are input from the first selection unit 106, and an initialization signal is output at a cycle n that counts the number of high-speed timing clocks TH. A third clock counter that is initialized together with a fourth clock counter that counts the number of clocks of the low-speed timing clock TL and that is initialized by an initialization signal of the third clock counter. The output of the fourth clock counter may be stored as the control value M by the initialization signal of the third clock counter. At this time, the mask signal generation unit 603 receives the control value M of the storage unit 602 and the count value of the third clock counter, and the count value of the third clock counter is equal to or less than the control value M. Outputs “1” (fourth logic value) as a mask signal, and when the count value of the third clock counter is larger than the control value M, “0” (inversion of the fourth logic value) Value) as a mask signal. Further, the clock generation unit 501 receives the high-speed timing clock TH and the low-speed timing clock TL from the selection unit 106, and the low-speed timing clock whose average frequency is equal to the other low-speed timing clock TL from the input high-speed timing clock TH. And outputs a high-speed timing clock and a low-speed timing clock.

  Hereinafter, the receiving apparatus according to the third embodiment of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the structure same as the structure of Example 1 of FIG. 1, and description is abbreviate | omitted.

  FIG. 9 is a configuration diagram of a receiving device according to the third embodiment of the present invention.

  The receiving apparatus 100 includes demodulation units 101 and 102, first and second data decompression units 901 and 902, a control signal generation unit 903, a multiplexing unit 904, a clock generation unit 905, and a clock generation unit 906. It is configured.

  The first and second data decompression units 901 and 902 receive demodulated data D1 and D2 and timing clocks T1 and T2 synchronized therewith from the demodulating units 101 and 102, respectively, and the timing clocks T1 and T2 each have one cycle. By alternately outputting in units, it is divided into timing clocks T1a, T1b, T2a, T2b and output, and further, demodulated data D1 synchronized with the rise of each of the timing clocks T1a, T1b is latched and used as timing clocks T1a, T1b. The demodulated data D1a and D1b synchronized with each other are generated, the demodulated data D2 synchronized with the rise of each of the timing clocks T2a and T2b are latched, and the demodulated data D2a and D2b synchronized with the timing clocks T2a and T2b are generated and output. I.e. each odd number Eyes of the timing clock and the odd-numbered demodulated data synchronized thereto, and outputs the even-numbered timing clock and two systems of even-numbered demodulated data synchronized therewith.

  The control signal generator 903 includes a control timing clock Tp having a short period T that is shorter than or equal to the shortest period of the timing clocks T1 and T2, and four demodulation timing clocks output from the first and second data decompressors 901 and 902. (Timing clocks T1a, T1b, T2a, T2b) are input, the rising edges of the four demodulation timing clocks are detected by using the control timing clock Tp, and the rising edges are detected within the control timing clock period T [N]. A data control signal (T1a or T1b or T2a or T2b; identification control signal) for sequentially identifying a timing clock whose rising edge has been detected in the next control timing clock cycle T [N + 1] is sequentially output. Is output.

  The multiplexing unit 904 synchronizes with the data control signal based on the data control signal (T1a or T1b or T2a or T2b) output from the control signal generation unit 903, and the demodulated data output from the data decompression units 901 and 902 D1a, D1b, D2a, and D2b are selected to generate multiplexed data and output to the AV decoder 107.

  The clock generation unit 905 receives the control timing clock Tp and the timing clocks T1a and T1b output from the first data decompression unit 901. By using the control timing clock Tp, the clock generation unit 905 uses the control timing clock cycle T to generate the timing clock T1a. , T1b is detected, and when one of the rising edges is detected within the control timing clock period T [N], the first one having a rising edge during the output period of the data control signal within the next period T [N + 1]. Multiple timing clock Ta is generated and output to AV decoder 107.

  The clock generation unit 906 receives the control timing clock Tp and the timing clocks T2a and T2b output from the second data decompression unit 902, and uses the control timing clock Tp to generate the timing clock T2a at the control timing clock cycle T. , T2b is detected, and when one of the rising edges is detected within the control timing clock period T [N], a second one having a rising edge during the output period of the data control signal within the next period T [N + 1]. Multiple timing clock Tb is generated and output to AV decoder 107.

  The operation of the receiving apparatus 100 configured as described above will be described with reference to FIG.

  The first data decompression unit 901 outputs the timing clock T1 divided into timing clocks T1a and T1b by alternately outputting the timing clock T1 in units of one cycle. Further, the demodulated data D1 synchronized with the rising edges of the timing clocks T1a and T1b is latched to generate demodulated data D1a and D1b synchronized with the timing clocks T1a and T1b, respectively. Similarly, the second data decompression unit 902 outputs timing clocks T2a and T2b, and generates demodulated data D2a and D2b synchronized with the timing clocks T2a and T2b, respectively.

  The control signal generation unit 903 detects rising edges of the four demodulation timing clocks (timing clocks T1a, T1b, T2a, T2b) by using the control timing clock Tp that is equal to or shorter than the shortest cycle of the timing clocks T1, T2. If a rising edge is detected within a certain control timing clock period T [N], a data control signal for identifying a timing clock whose rising edge has been detected in the next period T [N + 1] is sequentially output. If no rising edge is detected, data control is performed. Hold the signal and output.

  In the case of FIG. 10, since the timing clocks T1a and T2a rise in the cycle T [1], the data control signal sequentially outputs T1a and T2a in the cycle T [2]. Since the timing clocks T1a and T2b rise in the period T [3], the data control signal sequentially outputs T1a and T2b in the period T [4]. Since no timing clock rises in the period T [4], the data control signal holds the immediately preceding T2b.

  Multiplexer 904 generates and outputs multiplexed data by selecting demodulated data D1a, D1b, D2a, and D2b according to the data control signal. In FIG. 10, since the data control signal of period T [2] indicates T1a and T2a, the contents A0 and B0 of D1a and D2a corresponding to each are output as multiplexed data.

  The first clock generation unit 905 detects the rising edge of the timing clocks T1a and T1b in the control timing clock period T, and when one of the rising edges is detected in the control timing clock period T [N], the first period T [N + 1] The first multiple timing clock Ta having a rising edge during the output period of the data control signal is generated and output. In FIG. 10, since the timing clock T1a rises at the cycle T [1], the first multiple timing clock Ta is generated so that the data control signal of the cycle T [2] has a rise during the period T1a.

  Similarly to the first clock generation unit 905, the second clock generation unit 906 also detects the rising edge of the timing clocks T2a and T2b at the control timing clock cycle T [N], thereby generating the next cycle T [N + 1]. A second multiple timing clock Tb is generated and output.

  As described above, according to the third embodiment, the data is expanded using the control timing clock Tp faster than the timing clocks T1 and T2 without detecting the speeds of the first and second demodulated data D1 and D2. As a result, the two demodulated data D1 and D2 that operate asynchronously can be easily made into multiplexed data synchronized with a single clock, and the circuit scale and design man-hours can be reduced.

  The control timing clock period T is set to 1 / m of the timing clock T1 or T2 (m is a natural number of 2 or more), so that synchronous design is possible, and design efficiency can be further improved. .

  Further, the data decompression units 901 and 902 may hold demodulated data when the timing clocks T1 and T2 rise or fall.

  Hereinafter, a receiving apparatus according to Embodiment 4 of the present invention will be described with reference to FIG. In FIG. 11, the same components as those in FIG. 1 are denoted by the same reference numerals and a and b identifying the two systems, and the description thereof is omitted.

  The receiving apparatus according to the fourth embodiment of the present invention receives 4n types of received signals (n is a positive integer greater than or equal to 1; in FIG. 11, four received signals A, B, C, and D having different broadcasting systems). 2n receivers 100 shown in the first embodiment are arranged in parallel (two in FIG. 11), and 4n types of timing clocks and 2n types of multiplexed data are generated and output to the AV decoder 107. ing. A demodulator is provided in accordance with the broadcast system of each received signal.

  As described above, according to the fourth embodiment, when 4n types of received signals are received, 2n types of reception devices illustrated in the first embodiment are provided in parallel, and can be output as 2n types of multiplexed data. In addition, it is possible to multiplex two demodulated data without using a large-scale memory, which is easy to design and avoids an increase in the board area on which the receiver is mounted. Can be provided at low cost.

  In addition, although the configuration of the receiving device described in the first embodiment is provided as the receiving device in the fourth embodiment, the configuration of the receiving device described in the second or third embodiment may be used.

  Further, although two pairs of demodulating units are provided as the demodulating units, a demodulating unit of each broadcasting system may be provided in combination.

  In addition, 4n types of received signals are received signals A, B, C, and D having four different broadcasting systems. However, the 4n types of received signals are all of the same broadcasting system or a mixture of different broadcasting systems. It doesn't matter.

  Hereinafter, the reception method according to the fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 12 is a configuration diagram of a processor that executes the receiving method according to the fifth embodiment.

  In FIG. 12, reference numerals 1201 and 1202 denote input I / Fs for receiving reception signals A and B of each broadcasting system. Reference numeral 1203 denotes a general-purpose internal memory. Reference numeral 1204 denotes a CPU that performs control and calculation, and 1205 denotes a ROM that stores a control program and the like. Reference numeral 1207 denotes an output I / F that outputs to the AV decoder 107 a timing clock synchronized with each of the multiplexed data obtained by multiplexing the demodulated data obtained by demodulating each received signal and the multiplexed demodulated data. The input I / Fs 1201 and 1202, the built-in memory 1203, the CPU 1204, the ROM 1205, and the output I / F 1207 are connected by a bus 1208.

A reception method by the CPU 1204 will be described with reference to the flowchart of FIG.
Step-S1 (demodulation step)
First, the received signals A and B are demodulated on the basis of the respective systems, the demodulated data D1 and D2 are generated in units of bytes, and the timing clocks T1 and T2 synchronized therewith are generated.
Step-S2 (speed judgment step)
Next, the speed determination processing of the two timing clocks T1 and T2 generated in step -S1 is performed, and the two timing clocks T1 and T2 are output as the high-speed timing clock TH and the low-speed timing clock TL. Further, the two demodulated data D1 and D2 generated in step -S1 are output as the high-speed demodulated data DH and the low-speed demodulated data DL synchronized with the high-speed timing clock TH and the low-speed timing clock TL.
Step-S3 (clock generation step)
Next, a low-speed timing clock having the same average frequency as the low-speed timing clock TL is generated in synchronization with the high-speed timing clock TH.

More specifically, the clock generation step S3 includes the following steps -S4 to S6.
Step-S4 (memory step)
The count value of the low-speed timing clock TL counted every predetermined cycle n of the high-speed timing clock TH is stored as the control value M.
Step-S5 (mask signal generation processing step)
Next, if the count value of the high-speed timing clock TH is equal to or less than the control value M, a logical value “1” is output as a mask signal.
Step-S6 (mask processing step)
Next, when the mask signal output from step S5 is the logical value “1”, the high-speed timing clock TH is output as the low-speed timing clock, and when the logical value is “0”, the logical value “L” is output as the low-speed timing clock.
Step-S7 (multiple processing step)
Following the clock generation step S3 (S4 to S6), the low-speed demodulated data DL is selected and output when the low-speed timing clock has a logical value “1”, and the high-speed demodulated data DH is output when the logical value is “0”. Select and output.

  As described above, according to the fifth embodiment, it is possible to multiplex two demodulated data D1 and D2 in byte units with a general-purpose processor configuration, and it is possible to greatly reduce the capacity of the general-purpose memory 1203. The cost of the receiving apparatus can be reduced, and at the same time, the timing constraint of the connected AV decoder 107 is relaxed by synchronizing the timing clock output to the AV decoder 107 with the high-speed timing clock. Can be used to reduce the cost of the entire system. Even if the two demodulated data D1 and D2 output by the two demodulation processes and the two timing clocks T1 and T2 synchronized with the demodulated data are inferior in speed, the two demodulated data D1 and D2 can be multiplexed. It becomes.

  The receiving apparatus according to the present invention can multiplex two demodulated data by adding a small circuit without using a large-scale memory, thereby realizing cost reduction and low power consumption by reducing the circuit scale. In addition, it is possible to synchronize the timing clock synchronized with the multiplexed demodulated data with a single timing clock such as a high-speed timing clock or a higher-speed internal timing clock. Because it has the effect of being able to relax and building a cheaper system, it can be applied to applications such as systems that receive multiple broadcasts at a single location and distribute received data widely in remote locations. it can.

  The present invention relates to a receiving apparatus for receiving a plurality of digital broadcasts of different broadcasting systems or the same broadcasting system, such as satellite digital broadcasting and terrestrial digital broadcasting, a receiving system using the receiving apparatus, and a receiving method thereof.

In recent years, with the advancement of digital transmission technology and semiconductor integrated technology, digitization of broadcasting and communication has been promoted.
A receiving device and a receiving system that simultaneously receive a plurality of broadcasts are a plurality of demodulation units that perform demodulation in accordance with each broadcast method of a received signal, a multiplexing unit that multiplexes and outputs demodulated data output from each demodulation unit, It comprises a multiplexed data separator that separates and outputs demodulated data to be decoded from the multiplexed demodulated data, and a decoder that decodes and outputs the demodulated data separated by the multiplexed data separator.

An example of such a digital broadcast receiving apparatus is disclosed in Japanese Patent Application Laid-Open No. 11-122556.
In order to receive a plurality of broadcasting systems simultaneously, this known digital broadcast receiving apparatus receives a plurality of demodulating units according to each broadcasting system and demodulated data output from the plurality of demodulating units in units of transport packets, A multiplexing unit that multiplexes in units of transport packets at a rate that is equal to or higher than the total transport packet transmission rate of the broadcasting system, and a multiplexed data separation unit that separates and outputs demodulated data to be decoded from the multiplexed demodulated data are provided. .
JP-A-11-122556

  However, in a known digital broadcast receiving apparatus, demodulated data output from a plurality of demodulator units corresponding to each broadcast method is multiplexed at a rate equal to or higher than the total transport packet transmission rate of each broadcast method in units of transport packets. However, a large-scale storage circuit such as a memory for delaying each demodulated data is required, and the circuit scale increases, so that there is a problem that it becomes expensive. Further, a publicly known digital broadcast receiver has not disclosed a specific method for multiplexing demodulated data.

  Therefore, the present invention provides an inexpensive receiving device that can multiplex two demodulated data without adding a large-scale memory and adding a small circuit, a receiving system using the receiving device, and a receiving method thereof. It is intended to do.

  In order to achieve this object, the present invention provides, in the receiving apparatus, two demodulating units that receive the received signals of each broadcasting system and output demodulated data and timing clocks synchronized with the demodulated data, and output from these demodulating units. A clock generation unit that outputs two timing clocks as a high-speed timing clock and a low-speed timing clock to the AV decoder, and outputs a control signal for multiplexing the two demodulated data output from the demodulation unit, and based on the control signal And a multiplexing unit that multiplexes the two demodulated data and outputs the multiplexed data to the AV decoder. In the AV decoder, the video / audio signals of each broadcast are processed with the multiplexed data output from the receiving device and the timing clock as inputs.

  With the above configuration, the present invention makes it possible to multiplex two demodulated data with the addition of a small circuit without using a large-scale memory, thereby realizing cost reduction and low power consumption by reducing the circuit scale. It is possible to synchronize the timing clock synchronized with the multiplexed demodulated data with a single timing clock such as a high-speed timing clock or a higher-speed internal timing clock. It is possible to relax the timing constraints of the apparatus, and it is possible to construct a cheaper system.

Embodiments of the present invention will be described below with reference to the drawings.
[Example 1]
FIG. 1 is a configuration diagram of a receiving apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 100 denotes a receiving device. The receiving device 100 receives two received signals A and B of different broadcasting systems or digital broadcasting of the same broadcasting system, and multiplex data obtained by multiplexing respective demodulated data outputs. The high-speed timing clock and the low-speed timing clock synchronized with the multiplexed data are output. Reference numeral 107 denotes an AV decoder (an example of a video signal processing apparatus). The AV decoder 107 receives the multiplexed data, the high-speed timing clock, and the low-speed timing clock output from the receiving apparatus 100 as input, and converts the multiplexed data into two demodulated data. In this case, one or both of the two demodulated data are used as received data and processed into video / audio signals for each broadcast.

The receiving apparatus 100 includes first and second demodulation units 101 and 102, a speed determination unit 105, a first selection unit 106, a clock generation unit 103, and a multiplexing unit 104.
The first and second demodulating sections 101 and 102 receive two received signals A and B, respectively, output demodulated data D1 and D2 to the first selecting section 106, and timing clocks T1 and T2 synchronized therewith, respectively. T2 is output to the first selection unit 106 and the speed determination unit 105.

  The speed determination unit 105 receives the two timing clocks T1 and T2 output from the demodulation units 101 and 102, compares the respective speeds, determines which clock is higher, and the determination result. Is output to the first selection unit 106 as the control signal C3.

  Based on the control signal C3 (determination result) output from the speed determination unit 105, the first selection unit 106 is one of timing clocks T1 and T2 output from the first and second demodulation units 101 and 102. One is selected as the high-speed timing clock TH and output to the clock generation unit 103, the other is output as the low-speed timing clock TL to the clock generation unit 103, and output from the first and second demodulation units 101 and 102. One of the demodulated data D1 and D2 is selected as the high-speed demodulated data DH and output to the multiplexing unit 104, and the other is output to the multiplexing unit 104 as the low-speed demodulated data DL.

  The clock generation unit 103 receives the high-speed timing clock TH and the low-speed timing clock TL output from the first selection unit 106 (based on the two timing clocks output from the demodulation units 101 and 102), A timing clock for multiplexed demodulated data DH and DL, that is, a high-speed timing clock for high-speed demodulated data DH and a low-speed timing clock for low-speed demodulated data DL are generated and output to the AV decoder 107 and two demodulated data DH and DL are generated. A control signal for multiplexing is output to multiplexing section 104.

  The multiplexing unit 104 multiplexes the demodulated data DH and DL output from the first selection unit 106 in units of bytes based on the control signal output from the clock generation unit 103, and outputs the multiplexed data to the AV decoder 107. .

Note that the first and second demodulation units 101 and 102 are demodulation units adapted to the broadcast systems of the received signals A and B.
A more specific circuit configuration of the clock generator 103 is shown in FIG.

  The clock generation unit 103 receives the high-speed timing clock TH and the low-speed timing clock TL output from the first selection unit 106, and as shown in FIG. The data is output to the decoder 107.

As illustrated in FIG. 2, the clock generation unit 103 includes a delay unit 201, an edge detection unit 202, a second selection unit 203, and a control signal generation unit 204.
The delay unit 201 inputs a low-speed timing clock TL, delays it, and outputs the timing clock TLD to the second selection unit 203.

  The edge detection unit 202 receives the high-speed timing clock TH and the low-speed timing clock TL as inputs, detects the simultaneous rising of the timing clock, and sends the selection signal SL to the second selection unit 203 when the rising is at the same time. A logical value “1” (an example of a second logical value) is output, and if different, a logical value “0” (an example of an inverted value of the second logical value) is output.

  The second selection unit 203 receives the low-speed timing clock TL and the timing clock TLD output from the delay unit 201, and selects two timing clocks based on the selection signal SL. That is, the selection signal SL has a logical value “ The delayed timing clock TLD is selected when it is “1”, the low-speed timing clock TL is selected when it is the logical value “0”, and is output to the control signal generator 204 and the AV decoder 107 as the low-speed timing clock.

  The control signal generation unit 204 receives the low-speed timing clock and the high-speed timing clock TH output from the second selection unit 203, and uses the multiplexing unit as a control signal for identifying the demodulated data DH and DL selected by the multiplexing unit 104. When the high-speed timing clock TH rises to 104, the logic value “1” (an example of the third logic value) is output. When the low-speed timing clock rises, the logic value “0” (the inverted value of the third logic value) Example) is output, and the value is held if there is no rising edge.

A more specific circuit configuration of the speed determination unit 105 is shown in FIG.
As shown in FIG. 3, the speed determination unit 105 includes first and second clock counting units 301 and 302 and an identification unit 303.

  The first and second clock counting units 301 and 302 receive two timing clocks T1 and T2 output from the first and second demodulation units 101 and 102, respectively, and the clocks of the timing clocks T1 and T2 are input. The number of rising edges (the number of clocks) N1 and N2 is counted, and the (self) initialization signal is output to the identification unit 303 as the control signals C1 and C2 at a predetermined cycle n, and either one of the control signals (initialization) Signals) are initialized by the outputs of C1 and C2.

  The identification unit 303 receives the control signals C1 and C2 output from the first and second clock counting units 301 and 302, respectively, and identifies a speed determination result and outputs a control signal (identification) to the first selection unit 106. When the control signal C1 is input to the first selection unit 106 first or simultaneously as the signal C3, “1” (an example of the first logical value) is output, and the control signal C2 is input first. In this case, “0” (an example of the inverted value of the first logic value) is output.

As shown in FIG. 3, the count values N1 and N2 of the first and second clock counters 301 and 302 and their control signals (initialization signals) C1 and C2 are output.
The operation of the receiving apparatus configured as described above will be described. FIG. 4 is a timing chart of each unit in the receiving apparatus 100 of FIG.

  The first demodulator 101 performs demodulation processing in conformity with the broadcasting system, outputs a timing clock T1 and demodulated data D1 (A [1], A [2], A [3],...) Synchronized therewith, The second demodulator 102 performs a demodulation process in conformity with the broadcasting system and outputs a timing clock T2 and demodulated data D2 (B [1], B [2], B [3],...) Synchronized with the timing clock T2. .

  The clock counting units 301 and 302 of the speed determination unit 105 count the rising edges of the timing clocks T1 and T2, and the count value outputs N1 and N2 increase as shown in FIG. Further, since the predetermined cycle is n, when N1 and N2 are equal to the cycle n (time 1 and time 2 in the figure), control signals (initialization signals) C1, C1 for initializing the clock counting units 301 and 302 are initialized. A logical value “1” is output as C2. Further, when either one of the clock counting units 301 and 302 reaches the cycle n, both the clock counting units 301 and 302 are initialized.

  The identification unit 305 of the speed determination unit 105 determines which clock counting unit 301, 302 has reached the predetermined period n first, that is, which of the control signals C1, C2 has the logical value “1” first. Thus, a high-speed output clock is identified from among the timing clocks T1 and T2, and a control signal C3 indicating the result is output. In the first embodiment, as the control signal C3, when the timing clock T1 is high speed, that is, when the control signal C1 is input first or simultaneously, “1” is output, and the timing clock T2 is high speed, that is, the control signal C2 is first. When “0” is input, “0” is output.

  As shown in FIG. 4, when the logical value of the control signal C3 is “1”, the first selection unit 106 outputs the timing locks T1 and T2 as a high-speed timing clock TH and a low-speed timing clock TL, respectively. Demodulated data D1 and D2 are output as high-speed demodulated data DH and low-speed demodulated data DL, respectively. When the logical value of the control signal C3 is “0”, the opposite is true.

The clock generation unit 103 outputs the input high-speed timing clock TH as it is to the AV decoder 107 as a high-speed timing clock.
The delay unit 201 of the clock generation unit 103 delays the low-speed timing clock TL and outputs the timing clock TLD. The edge detection unit 202 compares the timing clocks TH and TL, and outputs a logical value “1” when the rising edge is the same time as the selection signal SL, and outputs a logical value “0” when they are different. The second selection unit 203 selects the delayed timing clock TLD when the selection signal SL is a logical value “1”, selects the timing clock TL when the selection signal SL is a logical value “0”, and selects an AV decoder as a low-speed timing clock. It outputs to 107.

  The control signal generation unit 204 of the clock generation unit 103 outputs a logical value “1” as the control signal output to the multiplexing unit 104 when the high-speed timing clock rises, and outputs a logical value “0” when the low-speed timing clock rises. If there is no rising edge, the value is held.

  Multiplexer 104 selects high-speed demodulated data DH when the control signal output from control signal generator 204 has a logical value “1”, and selects low-speed demodulated data DL when the logical value is “0”. As shown in FIG. 4, multiplexed data is generated from the demodulated data DH and DL and output to the AV decoder 107.

  As described above, according to the first embodiment, a small circuit is added without using a storage unit (large-scale memory) that stores the two demodulated data D1 and D2 output from the two demodulation units 101 and 102. Thus, the two demodulated data D1 and D2 can be multiplexed, and the circuit scale and cost can be reduced by downsizing the receiving apparatus 100. At the same time, by reducing the number of output pins through multiple outputs, the cost can be reduced by downsizing the receiving apparatus. Further, since demodulated data is sequentially output without being stored in a memory or the like, it is possible to avoid deterioration of jitter performance and to avoid an increase in response time.

  Further, according to the first embodiment, even when the speed of the demodulated data D1 and D2 is changed or unknown (when the synchronized timing clocks T1 and T2 are changed or unknown), the speed determination unit 105 performs high-speed timing. Based on this, the first selection unit 106 selects one of the timing clocks T1 and T2 output from the demodulation units 101 and 102 as a high-speed timing clock TH and outputs the selected one. One of the demodulated data D1 and D2 output from the first and second demodulation units 101 and 102 is selected and output as the high-speed demodulated data DH, and the other is output as the low-speed timing clock TL. By being output as demodulated data DL, one system multiplexer 104 and clock generator 103 It becomes possible to sense, it is possible to reduce the circuit scale.

  Further, according to the first embodiment, by using the clock counting units 301 and 302 as the speed determining unit 105, the timing clocks T1 and T2 can be easily compared with a small circuit.

  According to the first embodiment, when the two timing clocks T1 and T2 rise simultaneously, the timing clock TLD delayed by the delay unit 201 is selected as the low-speed timing clock, and the rising timing of the low-speed timing clock is delayed, The two demodulated data D1 and D2 can be multiplexed without being lost, and the reliability can be improved.

  Note that the jitter performance can be improved by changing the predetermined period n according to the frequency of the clock timings T1 and T2, and the clock counters 301 and 302 can be improved by setting the period n to a multiplier of 2. The generation unit of the initialization signals (control signals C1 and C2) can be simplified, and the circuit can be further downsized.

  In addition, when the speeds of the timing clocks T1 and T2 are known in advance, the circuit can be further downsized by removing the speed determination unit 105 and the first selection unit 106. Needless to say, if the speed of the timing clocks T1 and T2 can be identified from the outside, the circuit can be downsized by removing only the speed determination unit 105.

Further, the polarity and logical value of the control signal shown in the first embodiment are not limited to this.
[Example 2]
Hereinafter, the receiving apparatus and the receiving method according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the first embodiment shown in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof is omitted.

In the second embodiment, a clock generation unit 501 is provided instead of the clock generation unit 103 of the first embodiment, and a multiplexing unit 503 is provided instead of the multiplexing unit 104.
The clock generation unit 501 according to the second embodiment receives the count values N1, N2, the control signals (initialization signals) C1, C2, and the control signal (identification signal) C3 from the speed determination unit 105, and receives the control signal (identification signal) C3 from the first selection unit 106. A high-speed timing clock TH is input, a high-speed timing clock TH is output as a high-speed timing clock, and a clock that is synchronized with the other low-speed timing clock TL and an average frequency equal to the high-speed timing clock TH is generated as a low-speed timing clock. And output.

  In addition, the multiplexing unit 503 according to the second embodiment inputs the high-speed demodulated data DH, the low-speed demodulated data DL, and the low-speed timing clock TL from the first selection unit 106, and inputs the low-speed timing clock from the clock generation unit 501. Based on the low-speed timing clock, the high-speed demodulated data DH and the low-speed demodulated data DL are selected to generate multiplexed data in units of bytes.

A specific circuit configuration of the clock generator 501 is shown in FIG.
As shown in FIG. 6, the clock generation unit 501 includes a third selection unit 601, a storage unit 602, a mask signal generation unit 603, a mask unit 604, and a logic inversion circuit 605.

  The third selection unit 601 receives the count values N1 and N2 and the control signal C3 from the speed determination unit 105. When the control signal C3 is a logical value “1”, that is, when the timing clock T1 is high speed, When the count value N1 of the clock counting unit 301 is selected and the control signal C3 is a logical value “0”, that is, when the timing clock T2 is high speed, the count value N2 of the second clock counting unit 302 is selected as the count value NH. And output to the mask signal generator 603.

  The storage unit 602 receives the count values N1 and N2, the control signals (initialization signals) C1 and C2 and the control signal C3 from the speed determination unit 105, and when the control signals (initialization signals) C1 and C2 are input. In addition, when the control signal C3 is the logical value “1” (when the timing clock T1 is high speed), the count value N2 output from the second clock counter 302 connected to the low speed timing clock T2 is used as the control value M. When the control signal C3 is a logical value “0” (when the timing clock T2 is high speed), the count value N1 output from the first clock counter 301 connected to the low speed timing clock T1 is controlled. The value M is stored and output to the mask signal generation unit 603.

  The mask signal generation unit 603 receives the count value NH output from the third selection unit 601 and the control value M output from the storage unit 602, and the count value NH of the third selection unit 601 is used as the mask signal. When the value is equal to or less than the control value M, “1” (an example of the fourth logical value) is output to the mask unit 604, and when the count value NH of the third selection unit 604 is greater than the control value M, “0” (the first value) 4) is output to the mask unit 604.

  The mask unit 604 receives the high-speed timing clock TH output from the first selection unit 106 and the mask signal output from the mask signal generation unit 603, and outputs the low-speed timing clock to the AV decoder 107 and the multiplexing unit 503. When the mask signal is “1”, a high-speed timing clock TH is output. When the mask signal is “0”, a logical value “L” is output.

The logic inversion circuit 605 logically inverts the high-speed timing clock TH output from the first selection unit 106 and outputs the result to the AV decoder 107 as a high-speed timing clock.
A specific circuit configuration of the multiplexing unit 503 is shown in FIG.

As illustrated in FIG. 7, the multiplexing unit 503 includes a FIFO unit 701 and a fourth selection unit 702.
The FIFO unit 701 sequentially writes the low-speed demodulated data DL input from the first selection unit 106 at the timing of the low-speed timing clock TL input from the first selection unit 106, and the low-speed timing clock output from the clock generation unit 501 And output to the fourth selection unit 702.

  The fourth selection unit 702 selects the low-speed demodulated data DL output from the FIFO unit 701 when the low-speed timing clock output from the clock generation unit 501 is a logical value “1”, and selects the low-speed demodulated data DL when the logical value is “0”. Selects the high-speed demodulated data DH to generate multiplexed data and outputs it to the AV decoder 107.

The operation of the receiving apparatus configured as described above will be described with reference to FIG.
The storage unit 602 stores the count output N2 of the second clock counter 302 connected to the low-speed timing clock T2 when the count output N1 of the counter 301 at time 1 or time 2 reaches the predetermined period n. Is stored as a control value M. In the case of FIG. 8, m is stored. The storage unit 602 is updated in accordance with the control signal C1 (initialization timing) of the first clock counting unit 301.

In the third selection unit 601, the count value N1 of the first clock counting unit 301 connected to the high-speed timing clock T1 is selected by the control signal C3 and output as the count value NH.
In the mask signal generation unit 603, the count value NH that changes in synchronization with the high-speed timing clock T1 output from the selection unit 601 is compared with the control value M stored in the storage unit 602, and the count value NH is the control value M. In the following cases, a logical value “1” is output as a mask signal, and when it is greater than the control value M, a logical value “0” is output. In the case of FIG. 8, the logical value is “1” until the count value NH reaches m. The mask unit 604 outputs a high-speed timing clock TH as a low-speed timing clock when the mask signal is a logical value “1”, and a logical value “L” when the mask signal is a logical value “0”. The logic inversion circuit 605 logically inverts the high-speed timing clock TH and outputs it as a high-speed timing clock.

  The low-speed demodulated data DL is written in the FIFO unit 701 at the timing of the low-speed timing clock TL, delayed by a predetermined time, and then read out at the timing of the low-speed timing clock, so that the output of the FIFO unit 701 is as shown in FIG. A number equal to the control value M is output in bursts in synchronization with the low-speed timing clock. The fourth selection unit 702 outputs the multiplexed data by selecting the output of the FIFO unit 701 when the low-speed timing clock is a logical value “1”, and selecting the high-speed demodulated data DH when the logical value is “0”. To do.

  As described above, according to the second embodiment, the two demodulated data DH and DL output from the two demodulating units 101 and 102 are synchronized with a single timing clock synchronized with a high-speed timing clock, and the multiplexed output timing is synchronized. Are equal intervals, signal processing for processing multiple outputs becomes easy, and the configuration of the entire receiving apparatus can be simplified. In addition, since the timing restrictions of the AV decoder 107 at the subsequent stage can be relaxed, an inexpensive one can be used, and the entire receiving system can be provided at a low cost.

  Further, according to the second embodiment, a low-speed timing clock having the same average frequency as that of the low-speed timing clock can be generated by a small circuit with reference to the high-speed timing clock.

  Further, according to the second embodiment, even if the speeds of the two demodulated data DH and DL output from the two demodulating units 101 and 102 and the two timing clocks TH and TL synchronized therewith are unknown, the speed determination is performed. Can be selected.

In the second embodiment, the clock generation unit 501 uses the count values N1, N2, the control signals (initialization signals) C1, C2, and the control signal C3 obtained by the speed determination unit 105, and the storage unit 602 Although the control value M is obtained, a high-speed timing clock TH and a low-speed timing clock TL are input from the first selection unit 106, and an initialization signal is output at a cycle n that counts the number of high-speed timing clocks TH. A third clock counter that is initialized together with a fourth clock counter that counts the number of clocks of the low-speed timing clock TL and that is initialized by an initialization signal of the third clock counter. The output of the fourth clock counter may be stored as the control value M by the initialization signal of the third clock counter. At this time, the mask signal generation unit 603 receives the control value M of the storage unit 602 and the count value of the third clock counter, and the count value of the third clock counter is equal to or less than the control value M. Outputs “1” (fourth logic value) as a mask signal, and when the count value of the third clock counter is larger than the control value M, “0” (inversion of the fourth logic value) Value) as a mask signal. Further, the clock generation unit 501 receives the high-speed timing clock TH and the low-speed timing clock TL from the selection unit 106, and the low-speed timing clock whose average frequency is equal to the other low-speed timing clock TL from the input high-speed timing clock TH. And outputs a high-speed timing clock and a low-speed timing clock.
[Example 3]
Hereinafter, the receiving apparatus according to the third embodiment of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the structure same as the structure of Example 1 of FIG. 1, and description is abbreviate | omitted.

FIG. 9 is a configuration diagram of a receiving device according to the third embodiment of the present invention.
The receiving apparatus 100 includes demodulation units 101 and 102, first and second data decompression units 901 and 902, a control signal generation unit 903, a multiplexing unit 904, a clock generation unit 905, and a clock generation unit 906. It is configured.

  The first and second data decompression units 901 and 902 receive demodulated data D1 and D2 and timing clocks T1 and T2 synchronized therewith from the demodulating units 101 and 102, respectively, and the timing clocks T1 and T2 each have one cycle. By alternately outputting in units, it is divided into timing clocks T1a, T1b, T2a, T2b and output, and further, demodulated data D1 synchronized with the rise of each of the timing clocks T1a, T1b is latched and used as timing clocks T1a, T1b. The demodulated data D1a and D1b synchronized with each other are generated, the demodulated data D2 synchronized with the rise of each of the timing clocks T2a and T2b are latched, and the demodulated data D2a and D2b synchronized with the timing clocks T2a and T2b are generated and output. I.e. each odd number Eyes of the timing clock and the odd-numbered demodulated data synchronized thereto, and outputs the even-numbered timing clock and two systems of even-numbered demodulated data synchronized therewith.

  The control signal generator 903 includes a control timing clock Tp having a short period T that is shorter than or equal to the shortest period of the timing clocks T1 and T2, and four demodulation timing clocks output from the first and second data decompressors 901 and 902. (Timing clocks T1a, T1b, T2a, T2b) are input, the rising edges of the four demodulation timing clocks are detected by using the control timing clock Tp, and the rising edges are detected within the control timing clock period T [N]. A data control signal (T1a or T1b or T2a or T2b; identification control signal) for sequentially identifying a timing clock whose rising edge has been detected in the next control timing clock cycle T [N + 1] is sequentially output. Is output.

  The multiplexing unit 904 synchronizes with the data control signal based on the data control signal (T1a or T1b or T2a or T2b) output from the control signal generation unit 903, and the demodulated data output from the data decompression units 901 and 902 D1a, D1b, D2a, and D2b are selected to generate multiplexed data and output to the AV decoder 107.

  The clock generation unit 905 receives the control timing clock Tp and the timing clocks T1a and T1b output from the first data decompression unit 901. By using the control timing clock Tp, the clock generation unit 905 uses the control timing clock cycle T to generate the timing clock T1a. , T1b is detected, and when one of the rising edges is detected within the control timing clock period T [N], the first one having a rising edge during the output period of the data control signal within the next period T [N + 1]. Multiple timing clock Ta is generated and output to AV decoder 107.

  The clock generation unit 906 receives the control timing clock Tp and the timing clocks T2a and T2b output from the second data decompression unit 902, and uses the control timing clock Tp to generate the timing clock T2a at the control timing clock cycle T. , T2b is detected, and when one of the rising edges is detected within the control timing clock period T [N], a second one having a rising edge during the output period of the data control signal within the next period T [N + 1]. Multiple timing clock Tb is generated and output to AV decoder 107.

The operation of the receiving apparatus 100 configured as described above will be described with reference to FIG.
The first data decompression unit 901 outputs the timing clock T1 divided into timing clocks T1a and T1b by alternately outputting the timing clock T1 in units of one cycle. Further, the demodulated data D1 synchronized with the rising edges of the timing clocks T1a and T1b is latched to generate demodulated data D1a and D1b synchronized with the timing clocks T1a and T1b, respectively. Similarly, the second data decompression unit 902 outputs timing clocks T2a and T2b, and generates demodulated data D2a and D2b synchronized with the timing clocks T2a and T2b, respectively.

  The control signal generation unit 903 detects rising edges of the four demodulation timing clocks (timing clocks T1a, T1b, T2a, T2b) by using the control timing clock Tp that is equal to or shorter than the shortest cycle of the timing clocks T1, T2. If a rising edge is detected within a certain control timing clock period T [N], a data control signal for identifying a timing clock whose rising edge has been detected in the next period T [N + 1] is sequentially output. If no rising edge is detected, data control is performed. Hold the signal and output.

  In the case of FIG. 10, since the timing clocks T1a and T2a rise in the cycle T [1], the data control signal sequentially outputs T1a and T2a in the cycle T [2]. Since the timing clocks T1a and T2b rise in the period T [3], the data control signal sequentially outputs T1a and T2b in the period T [4]. Since none of the timing clocks rises in the period T [4], the data control signal holds the immediately preceding T2b.

  Multiplexer 904 generates and outputs multiplexed data by selecting demodulated data D1a, D1b, D2a, and D2b according to the data control signal. In FIG. 10, since the data control signal of the cycle T [2] indicates T1a and T2a, the contents A0 and B0 of D1a and D2a corresponding to each are output as multiplexed data.

  The first clock generation unit 905 detects the rising edge of the timing clocks T1a and T1b in the control timing clock period T, and when one of the rising edges is detected in the control timing clock period T [N], the first period T [N + 1] The first multiple timing clock Ta having a rising edge during the output period of the data control signal is generated and output. In FIG. 10, since the timing clock T1a rises in the cycle T [1], the first multiple timing clock Ta is generated so that the data control signal in the cycle T [2] has a rise during the period T1a.

  Similarly to the first clock generation unit 905, the second clock generation unit 906 also detects the rising edge of the timing clocks T2a and T2b at the control timing clock cycle T [N], thereby generating the next cycle T [N + 1]. A second multiple timing clock Tb is generated and output.

  As described above, according to the third embodiment, the data is expanded using the control timing clock Tp faster than the timing clocks T1 and T2 without detecting the speeds of the first and second demodulated data D1 and D2. As a result, the two demodulated data D1 and D2 that operate asynchronously can be easily made into multiplexed data synchronized with a single clock, and the circuit scale and design man-hours can be reduced.

  The control timing clock period T is set to 1 / m of the timing clock T1 or T2 (m is a natural number of 2 or more), so that synchronous design is possible, and design efficiency can be further improved. .

Further, the data decompression units 901 and 902 may hold demodulated data when the timing clocks T1 and T2 rise or fall.
[Example 4]
Hereinafter, a receiving apparatus according to Embodiment 4 of the present invention will be described with reference to FIG. In FIG. 11, the same components as those in FIG. 1 are denoted by the same reference numerals and a and b identifying the two systems, and the description thereof is omitted.

  The receiving apparatus according to the fourth embodiment of the present invention receives 4n types of received signals (n is a positive integer greater than or equal to 1; in FIG. 11, four received signals A, B, C, and D having different broadcasting systems). 2n receivers 100 shown in the first embodiment are arranged in parallel (two in FIG. 11), and 4n types of timing clocks and 2n types of multiplexed data are generated and output to the AV decoder 107. ing. A demodulator is provided in accordance with the broadcast system of each received signal.

  As described above, according to the fourth embodiment, when 4n types of received signals are received, 2n types of reception devices illustrated in the first embodiment are provided in parallel, and can be output as 2n types of multiplexed data. In addition, it is possible to multiplex two demodulated data without using a large-scale memory, which is easy to design and avoids an increase in the board area on which the receiver is mounted. Can be provided at low cost.

In addition, although the configuration of the receiving device described in the first embodiment is provided as the receiving device in the fourth embodiment, the configuration of the receiving device described in the second or third embodiment may be used.
Further, although two pairs of demodulating units are provided as the demodulating units, a demodulating unit of each broadcasting system may be provided in combination.

In addition, 4n types of received signals are received signals A, B, C, and D having four different broadcasting systems. However, the 4n types of received signals are all of the same broadcasting system or a mixture of different broadcasting systems. It doesn't matter.
[Example 5]
Hereinafter, the reception method according to the fifth embodiment of the present invention will be described with reference to FIGS.

FIG. 12 is a configuration diagram of a processor that executes the receiving method according to the fifth embodiment.
In FIG. 12, reference numerals 1201 and 1202 denote input I / Fs for receiving reception signals A and B of each broadcasting system. Reference numeral 1203 denotes a general-purpose internal memory. Reference numeral 1204 denotes a CPU that performs control and calculation, and 1205 denotes a ROM that stores a control program and the like. Reference numeral 1207 denotes an output I / F that outputs to the AV decoder 107 a timing clock synchronized with each of the multiplexed data obtained by multiplexing the demodulated data obtained by demodulating each received signal and the multiplexed demodulated data. The input I / Fs 1201 and 1202, the built-in memory 1203, the CPU 1204, the ROM 1205, and the output I / F 1207 are connected by a bus 1208.

A reception method by the CPU 1204 will be described with reference to the flowchart of FIG.
Step-S1 (demodulation step)
First, the received signals A and B are demodulated on the basis of the respective systems, the demodulated data D1 and D2 are generated in units of bytes, and the timing clocks T1 and T2 synchronized therewith are generated.
Step-S2 (speed judgment step)
Next, the speed determination processing of the two timing clocks T1 and T2 generated in step -S1 is performed, and the two timing clocks T1 and T2 are output as the high-speed timing clock TH and the low-speed timing clock TL. Further, the two demodulated data D1 and D2 generated in step -S1 are output as the high-speed demodulated data DH and the low-speed demodulated data DL synchronized with the high-speed timing clock TH and the low-speed timing clock TL.
Step-S3 (clock generation step)
Next, a low-speed timing clock having the same average frequency as the low-speed timing clock TL is generated in synchronization with the high-speed timing clock TH.

More specifically, the clock generation step S3 includes the following steps -S4 to S6.
Step-S4 (memory step)
The count value of the low-speed timing clock TL counted every predetermined cycle n of the high-speed timing clock TH is stored as the control value M.
Step-S5 (mask signal generation processing step)
Next, if the count value of the high-speed timing clock TH is equal to or less than the control value M, a logical value “1” is output as a mask signal.
Step-S6 (mask processing step)
Next, when the mask signal output from step S5 is the logical value “1”, the high-speed timing clock TH is output as the low-speed timing clock, and when the logical value is “0”, the logical value “L” is output as the low-speed timing clock.
Step-S7 (multiple processing step)
Following the clock generation step S3 (S4 to S6), the low-speed demodulated data DL is selected and output when the low-speed timing clock has a logical value “1”, and the high-speed demodulated data DH is output when the logical value is “0”. Select and output.

  As described above, according to the fifth embodiment, it is possible to multiplex two demodulated data D1 and D2 in byte units with a general-purpose processor configuration, and it is possible to greatly reduce the capacity of the general-purpose memory 1203. The cost of the receiving apparatus can be reduced, and at the same time, the timing constraint of the connected AV decoder 107 is relaxed by synchronizing the timing clock output to the AV decoder 107 with the high-speed timing clock. Can be used to reduce the cost of the entire system. Further, even if the speeds of the two demodulated data D1 and D2 output by the two demodulating processes and the two timing clocks T1 and T2 synchronized therewith are unknown, the two demodulated data D1 and D2 can be multiplexed. Become.

  The receiving apparatus according to the present invention can multiplex two demodulated data by adding a small circuit without using a large-scale memory, thereby realizing cost reduction and low power consumption by reducing the circuit scale. In addition, it is possible to synchronize the timing clock synchronized with the multiplexed demodulated data with a single timing clock such as a high-speed timing clock or a higher-speed internal timing clock. Because it has the effect of being able to relax and building a cheaper system, it can be applied to applications such as systems that receive multiple broadcasts at a single location and distribute received data widely in remote locations. it can.

It is a block diagram of the receiver in Example 1 of this invention. It is a block diagram of the clock generation part of the receiver. It is a block diagram of the speed determination part of the receiver. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 2 of this invention. It is a block diagram of the clock generation part of the receiver. It is a block diagram of the multiplexing part of the receiver. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 3 of this invention. FIG. 4 is a timing chart for explaining the operation of the receiving apparatus. It is a block diagram of the receiver in Example 4 of this invention. It is a block diagram of the receiver in Example 5 of this invention. It is a flowchart of the receiving method of the receiving apparatus.

Explanation of symbols

100 receiver 101 first demodulator 102 second demodulator 103 clock generator 104 multiplexer 105 speed determiner 106 first selector
107 AV decoder (video signal processing device)
201 delay unit 202 edge detection unit 203 second selection unit 204 control signal generation unit 301 first clock counting unit 302 second clock counting unit 303 identification unit 305 identification unit 501 clock generation unit 503 multiplexing unit 601 third selection unit 602 Storage unit 603 Mask signal generation unit 604 Mask unit 605 Logic inversion circuit 701 FIFO unit 702 Fourth selection unit 901 First data decompression unit
902 Second data decompression unit 903 Control signal generation unit 904 Multiplexing unit 905 Clock generation unit 906 Clock generation unit 1201 Input I / F
1202 Input I / F
1203 Built-in memory 1204 CPU
1205 ROM
1207 Output I / F

Claims (12)

A receiving device for receiving two received signals of different broadcasting systems or digital broadcasting of the same broadcasting system,
A first demodulator and a second demodulator for inputting the two received signals and outputting demodulated data and timing clocks respectively synchronized with the demodulated data;
To generate and output timing clocks for each of the two demodulated data to be multiplexed based on the two timing clocks output from the first and second demodulator units, and to multiplex the two demodulated data A clock generator for outputting the control signal of
A receiving apparatus comprising: a multiplexing unit that multiplexes demodulated data output from the first and second demodulation units in units of bytes based on a control signal output from the clock generation unit. The receiving device according to claim 1,
From the two demodulated data output from the first and second demodulator and the two timing clocks, a high-speed timing clock and a high-speed demodulated data synchronized with the high-speed demodulated data are selected. The 1st selection part to output is provided. The receiving device according to claim 2,
The speeds of the timing clocks output from the first and second demodulation units are compared to determine which clock is higher, and the determination result is output to the first selection unit as a control signal. Equipped with a speed judgment unit,
The first selection unit selects a high-speed timing clock and high-speed demodulated data synchronized with the high-speed timing clock and a low-speed timing clock and low-speed demodulated data synchronized with the high-speed timing clock based on the control signal output from the speed determination unit. The receiving device according to claim 3,
As the speed determination unit,
The number of clocks of the two timing clocks output from the first and second demodulator units is counted, an initialization signal is output at a predetermined period, and both are initialized by output of one of the initialization signals. First and second clock counters to be
The first and second initialization signals respectively output from the first and second clock counting units are input, and the first initialization signal output is the first control signal output to the first selection unit. And a discriminator that outputs a first logical value when the first logical value is input, or outputs an inverted value of the first logical value when the second initialization signal is input first. The receiving device according to any one of claims 2 to 4,
The clock generation unit outputs the high-speed timing clock output from the first selection unit as it is as a high-speed timing clock,
The simultaneous rising of the two high-speed timing clocks output from the first selection unit and the low-speed timing clock is detected, and when the risings are at the same time, a second logical value is output. An edge detector that outputs an inverted value of the logical value;
A delay unit that delays and outputs the low-speed timing clock output from the first selection unit;
If the low-speed timing clock output from the first selection unit and the low-speed timing clock delayed by the delay unit are input and the second logical value is output from the edge detection unit, the delay unit The low-speed timing clock delayed by the second selection is selected, and if it is the inverted value of the second logical value, the low-speed timing clock output from the first selection unit is selected and output as the low-speed timing clock. A selection section;
When the high-speed timing clock rises as a control signal for inputting the high-speed timing clock and the low-speed timing clock output from the second selection unit and multiplexing two demodulated data output to the multiplexing unit, A control signal generation unit is provided that outputs a logical value, outputs an inverted value of the third logical value when the low-speed timing clock rises, and holds a value when there is no rising. A receiving device for receiving two received signals of different broadcasting systems or digital broadcasting of the same broadcasting system,
A first demodulator and a second demodulator for inputting the two received signals and outputting demodulated data and timing clocks respectively synchronized with the demodulated data;
Among the timing clocks output from the first and second demodulation units, a high-speed timing clock is output as a high-speed timing clock, and the other low-speed timing clock has the same average frequency and is synchronized with the high-speed timing clock. A clock generation unit that generates and outputs a low-speed timing clock;
A receiving apparatus comprising: a multiplexing unit that multiplexes demodulated data output from the first and second demodulation units in units of bytes based on a low-speed timing clock output from the clock generation unit. The receiving device according to claim 6,
The number of clocks of the two timing clocks output from the first and second demodulator units is counted, the count value is output, an initialization signal is output at a predetermined period, and one of the initial clocks is output. A first clock counter and a second clock counter that are initialized together by the output of the control signal;
The first and second initialization signals output from the first and second clock counting units are input, and the first initialization signal output is the first control signal output to the first selection unit. The first logic value is output when the second initialization signal is input first, or an inversion value of the first logic value is output when the second initialization signal is input first;
The first timing clock and first demodulated data output from the first demodulator, the second timing clock and second demodulated data output from the second demodulator, and the discriminator. If the control signal is the first logical value, the first timing clock is output as a high-speed timing clock, and the first demodulated data is output as high-speed demodulated data. A first selection unit that outputs the second demodulated data as high-speed demodulated data if the logical value of
Is provided. The receiving device according to claim 7,
The clock generator is
When the count value and initialization signal of each of the first and second clock counting units and the control signal of the identification unit are input, and the control signal is the first logic value, the first clock counting unit A third selection unit that outputs the count value of the second clock counting unit if the control signal is an inverted value of the first logic value;
The count value and the initialization signal of each of the first and second clock counting units and the control signal of the identification unit are input, and when the initialization signal is input, the control signal is the first logic value. If so, the count value of the second clock counter is stored as a control value, and if the control signal is an inverted value of the first logic value, the count value of the first clock counter is A storage unit for storing and outputting as a control value;
When the control value output from the storage unit and the count value output from the third selection unit are input, and the count value of the third selection unit is less than or equal to the control value, the fourth logical value is used as a mask signal A mask signal generation unit that outputs an inverted value of the fourth logic value as a mask signal when the count value of the third selection unit is greater than the control value,
The mask signal output from the mask signal generation unit and the high-speed timing clock output from the first selection unit are input. If the mask signal is the fourth logical value, the high-speed timing clock is output. When the mask signal is an inverted value of the fourth logic value, a mask unit that outputs a logic value “L” as a low-speed timing clock; and
A logic inversion circuit that logically inverts the high-speed timing clock output from the first selection unit and outputs the result as a high-speed timing clock; A receiving device for receiving two received signals of different broadcasting systems or digital broadcasting of the same broadcasting system,
A first demodulator and a second demodulator for inputting the two received signals and outputting demodulated data and timing clocks respectively synchronized with the demodulated data;
The demodulated data and a timing clock synchronized with the demodulated data are input from the first demodulator, and the odd-numbered timing clock and the odd-numbered demodulated data synchronized with the odd-numbered timing clock and the even-numbered demodulated data synchronized with the odd-numbered demodulated data. A first data decompression unit for outputting the system;
The demodulated data and the timing clock synchronized with the demodulated data are input from the second demodulator, and the odd-numbered timing clock and the odd-numbered demodulated data synchronized with the odd-numbered timing clock and the even-numbered demodulated data synchronized with the even-numbered demodulated data. A second data decompression unit for outputting the system;
A control timing clock having a cycle shorter than the shorter one of the two timing clocks output from the first and second demodulation units, and four demodulation timings output from the first and second data decompression units A control signal generator for inputting a clock, detecting the demodulation timing clock having a rising edge in the control timing clock cycle, and outputting an identification control signal in the next cycle;
Based on the identification control signal output from the control signal generation unit, a multiplexing unit that selects the demodulated data output from the first and second data decompression units synchronized with the identification control signal;
The control timing clock and the timing clock output from the first data decompression unit are input, the rising edge within the control timing clock period is detected, and there is a rising edge within the identification control signal period of the next period. A first clock generator for generating such a first multiple timing clock;
The control timing clock and the timing clock output from the second data decompression unit are input, the rising edge within the control timing clock period is detected, and the rising edge is within the identification control signal period of the next period. A receiving apparatus comprising a second clock generator for generating the second multiple timing clock. The receiver according to any one of claims 1 to 9 is arranged in parallel with 2n (n is a positive integer of 1 or more) units,
4. A receiving apparatus, wherein 4n types of received signals are input, 4n types of timing clocks and 2n types of multiplexed data are generated and output. The receiving device according to any one of claims 1 to 9,
The multiplexed data of the two demodulated data output from the receiver and the timing clock of each of the multiplexed demodulated data are input, and one or both of the two demodulated data of the multiplexed data are used as the received data. A receiving system comprising a signal processing device. A receiving method for receiving two received signals of different broadcasting systems or digital broadcasting of the same broadcasting system,
The two received signals are demodulated based on each method, each demodulated data is generated in units of bytes, and a timing clock synchronized with that is generated,
Next, speed determination processing of the two generated timing clocks is performed, the two timing clocks are output as a high-speed timing clock and a low-speed timing clock, and the generated two demodulated data are converted into the high-speed timing clock and the low-speed timing clock. Output as high-speed demodulated data and low-speed demodulated data synchronized with the timing clock,
Next, the count value of the low-speed timing clock counted every predetermined period of the high-speed timing clock is stored as a control value,
Next, if the count value of the high-speed timing clock is less than or equal to the stored control value, a logical value “1” is output as a mask signal, and if the count value is greater than the control value, a logical value “0” is output as a mask signal. And
Next, when the mask signal is a logical value “1”, the high-speed timing clock is output as a low-speed timing clock, and when the mask signal is a logical value “0”, the logical value “L” is output as a low-speed timing clock.
Next, when the low-speed timing clock is a logical value “1”, low-speed demodulated data is selected and output, and when the low-speed timing clock is a logical value “0”, high-speed demodulated data is selected and output. .

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