JP2014107610A - Receiving circuit for start-stop synchronous serial transmission and receiving method of start-stop synchronous serial transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a transmission rate of a start-stop synchronization system substantially equal to an operation frequency of a transmission circuit, in a simple circuit configuration.SOLUTION: A receiving circuit for start-stop synchronous serial transmission comprises: N pieces of sampling circuits each for sampling a received signal while using N pieces of polyphase clock signals each formed from a plurality of clock signals of an equal frequency, one of the polyphase clock signals being defined as a reference clock signal; N pieces of edge detection circuits each for detecting an edge of the signal sampled by the sampling circuit in a cycle of the reference clock signal in the polyphase clock signals; a selector circuit for decoding a detection result of the edge detection circuit for each cycle of the reference clock signal and, on the basis of a result of decoding, selecting one signal suitable as a signal corresponding to the received signal from among N pieces of signals sampled by the sampling circuits; and a conversion circuit for performing serial-to-parallel conversion on the sampled signal selected by the selector circuit.

Description

  Embodiments described herein relate generally to a serial transmission receiving circuit and an asynchronous serial transmission receiving method using an asynchronous method.

  2. Description of the Related Art Conventionally, a general asynchronous transmission circuit can be configured in an all-digital manner, and secondly, the cost of the circuit depends on a clock synchronization method in which a clock signal is superimposed on transmission line data. It is small compared to the transmission circuit, and thirdly, it can be easily mounted on an inexpensive field-programmable gate array (FPGA) device, and fourthly, the number of transmission lines is at least one (one-way or two-way). (In the case of heavy bidirectional)) On the other hand, in an asynchronous transmission system, the upper limit of the transmission rate (bit rate) is about 1/16 of the operating frequency of the transmission circuit. There is a drawback that when the transmission rate is from 100 MHz to over 100 MHz, the transmission speed is limited to several Mbps at the maximum.

  In high-speed serial transmission exceeding about 100 Mbps, serial transmission based on the clock synchronization method described above is the mainstream. This synchronization method has a disadvantage that firstly, a part of it is constituted by an analog circuit, and secondly, its circuit cost is higher than that of a transmission circuit using the start-stop synchronization method. The reason why the clock synchronization method is adopted instead of the start-stop synchronization method in spite of such drawbacks is that, as described above, the start-stop synchronization method has an upper limit on the transmission speed when the operating frequency is determined. This is because the transmission speed is lower than that of the clock synchronous system under the same operating frequency conditions. For example, in order to achieve a transmission rate of 100 Mbps by serial transmission using a general asynchronous process, the operating frequency of the transmission circuit must be at least about 1.6 GHz. Even if this is feasible in terms of circuit technology, it is not practical because the cost for devices and mounting will increase significantly. For this reason, several circuit techniques and methods have been devised for raising the upper limit of the transmission speed of the asynchronous system from about 1/16 of the operating frequency of the transmission circuit to about 1/1.

  For example, as a first method, there is a method in which a received signal is sampled with a multiphase clock, and finally a clock that is most synchronized with the bit data of the received signal is selected from the multiphase clock. By operating the receiving circuit with this selected clock, the transmission speed is reduced to about 1/1 of the operating frequency of the transmission circuit. In addition, as a second method and a third method, a received signal is sampled with a multiphase clock or the like, and a sampling signal that is most synchronized with the reference clock is selected based on a change point of the sampling result. There is.

Japanese Patent No. 3378830 Japanese Patent No. 3378831 JP 2007-123988 A

  However, the first and second methods described above are bit-wise synchronization methods for clock-synchronous serial transmission in which a clock signal is superimposed on bit data of a transmission line, and are frame-by-frame like the asynchronous method. In other words, synchronization in units of a set of bits from the start bit to the stop bit is not assumed. That is, the above-described first and second methods are over-specification for the asynchronous method, and the circuit structure is inevitably complicated. Specific examples are shown below.

  First, since the operation clock of the receiving circuit is dynamically switched in the first method described above, the timing of the operation clock that dynamically changes must be taken into account when the receiving circuit is mounted. In particular, FPGA devices that have become widely used in recent years are not suitable for mounting such circuits, and it is necessary to cover all the complexity of verification, that is, combinations of operation clock switching timings. Together, implementation is very difficult.

  In the second method described above, a deviation calculation circuit and a counter are provided, and the threshold value of the counter is made variable, thereby achieving both responsiveness and stability of synchronization in bit units. This is a necessary function for clock synchronization systems that need to synchronize quickly during reception of the preamble and to maintain the synchronization state stably during data reception. Not applicable. The second method requires a mechanism for controlling a synchronous FIFO (First In First Out buffer) and writing of the synchronous FIFO.

  The third method described above is different from the first and second methods in that the target is limited to asynchronous transmission of serial transmission. In other words, as in the first and second methods, there is a feature specialized in synchronization in units of frames, not in units of bits. However, this method has a problem that the circuit cost increases because the shift register circuit is required by the number of multiphase clocks. In addition, since a multi-phase clock is supplied to a large number of circuit blocks, it is expected that the implementation to the FPGA device will be difficult due to clock domain management and timing constraints, although not as much as the eleventh method. The

  The problem to be solved by the present invention is to provide a start-stop serial transmission receiving circuit and start-stop synchronous serial transmission capable of increasing the transmission speed of the start-stop synchronization method to almost the same as the operation frequency of the transfer circuit with a simple circuit configuration. It is to provide a receiving method.

  According to the embodiment, the asynchronous serial transmission receiver circuit samples a received signal using N multiphase clock signals, each of which includes a plurality of clock signals having the same frequency, and one of which is a reference clock signal. A plurality of sampling circuits, and N edge detection circuits for detecting a falling edge or a rising edge of a signal sampled by the sampling circuit in a cycle of the reference clock signal among the multiphase clock signals. The reception circuit decodes the detection result of the edge detection circuit every cycle of the reference clock signal, and based on the decoding result, the reception signal is selected from the N sampled signals of the sampling circuit. A selection circuit that selects an appropriate signal as a signal corresponding to the signal, and a conversion circuit that performs serial-parallel conversion on the sampled signal selected by the selection circuit.

  According to the present invention, it is possible to increase the transmission speed of the start-stop synchronization method to almost the same as the operating frequency of the transmission circuit with a simple circuit configuration.

The block diagram which shows an example of the receiving circuit of the asynchronous serial transmission in 1st Embodiment. The figure which shows an example of the specific structure of the 4-phase sampling circuit in 1st Embodiment. FIG. 3 is a diagram illustrating an example of a specific configuration of a falling edge detection circuit according to the first embodiment. The figure which shows an example of the specific structure of the sampling signal selection circuit in 1st Embodiment. 4 is a timing chart illustrating an example of operation waveforms of the sampling circuit according to the first embodiment. 4 is a timing chart illustrating an example of operation waveforms of the sampling circuit according to the first embodiment. 4 is a timing chart illustrating an example of operation waveforms of the sampling circuit according to the first embodiment. 4 is a timing chart illustrating an example of operation waveforms of the sampling circuit according to the first embodiment. 5 is a timing chart illustrating an example of operation waveforms of a falling edge detection circuit according to the first embodiment. 5 is a timing chart illustrating an example of operation waveforms of a falling edge detection circuit according to the first embodiment. 5 is a timing chart illustrating an example of operation waveforms of a falling edge detection circuit according to the first embodiment. 5 is a timing chart illustrating an example of operation waveforms of a falling edge detection circuit according to the first embodiment. 6 is a timing chart illustrating an example of operation waveforms of the sampling signal selection circuit according to the first embodiment. 6 is a timing chart illustrating an example of operation waveforms of the sampling signal selection circuit according to the first embodiment. 6 is a timing chart illustrating an example of operation waveforms of the sampling signal selection circuit according to the first embodiment. 6 is a timing chart illustrating an example of operation waveforms of the sampling signal selection circuit according to the first embodiment. The block diagram which shows an example of the receiving circuit of the asynchronous serial transmission in 2nd Embodiment. The figure which shows an example of the specific structure of the sampling circuit in 2nd Embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
(First embodiment)
First, the first embodiment will be described.
FIG. 1 is a block diagram illustrating an example of a receiver circuit for asynchronous serial transmission according to the first embodiment. In this embodiment, the reception circuit for asynchronous serial transmission is described on the assumption that a 4-phase clock signal is used. However, a configuration using a clock signal of 4 phases or more such as 8 phases and 12 phases is used. You can also.

  As shown in FIG. 1, the receiver circuit for asynchronous serial transmission in the first embodiment includes a four-phase clock generation circuit 10, a noise removal circuit 11, a four-phase sampling circuit 12, a falling edge detection circuit 13, and a sampling signal selection. A circuit 14, a four-input multiplexer 15, and a serial-parallel conversion circuit 16 are provided.

  The four-phase clock generation circuit 10 shown in FIG. 1 outputs four clock signals (φ0, φ1, φ2, φ3) from the clock signal input from the outside of the semiconductor device 1 via the input terminal and the input buffer. Circuit. The frequency of the clock signal input by the four-phase clock generation circuit 10 does not matter, but the four-phase clock generation circuit 10 has almost the same transmission speed as the received signal input from the outside of the semiconductor device 1 for each output clock signal. Has a function to adjust to the same frequency.

  The reason described as “substantially equal” is that there are fluctuations and errors in the frequency and transmission speed of the actual clock signal, and it is impossible to make them “equal” strictly and continuously. The receiver circuit for asynchronous serial transmission in FIG. 1 is configured so that it does not malfunction due to some errors due to manufacturing variations, as well as the influence of the aforementioned fluctuation.

  In the present embodiment, among the clock signals φ0, φ1, φ2, and φ3 output from the four-phase clock generation circuit 10, the clock signal φ0 is used as a reference clock signal, and the other clock signals φ1, φ2, and φ3 are respectively set to φ0. A clock signal whose phase is delayed by 90 degrees, 180 degrees, and 270 degrees is assumed. That is, each clock signal is a signal whose phase is shifted at equal intervals at the same speed as the transmission speed of the received signal. The configuration of the four-phase clock generation circuit 10 can be configured by only a simple frequency division counter, or can be configured by a DLL (Delayed Lock Loop) circuit that is mounted as a standard in recent FPGA devices.

  The noise removal circuit 11 illustrated in FIG. 1 is a circuit that removes noise included in a reception signal input from the outside of the semiconductor device 1 via an input terminal and an input buffer. In a conventional general asynchronous receiver circuit, a circuit corresponding to a noise removal circuit is often provided after sampling with a reference clock signal. On the other hand, in the receiving circuit shown in FIG. 1, since the frequency value of the reference clock signal φ0 is substantially equal to the transmission speed value of the received signal, a non-sampling noise removing circuit, for example, a multistage delay cell and a logic It is desirable to provide a circuit composed of sum cells or the like at the most input stage.

  The four-phase sampling circuit 12 shown in FIG. 1 is a circuit that samples the reception signal SI after the noise removal by the noise removal circuit 11 with the four-phase clock signals φ0, φ1, φ2, and φ3. The specific configuration and timing chart of each clock signal are as shown in FIGS. 2 (a) and 2 (b), respectively, and two stages of flip-flops are arranged for each clock signal as a measure for metastable. It has a configuration.

  In the example shown in FIG. 2A, the four-phase sampling circuit 12 includes latch circuits 12a, 12b, 12c, 12d, 12e, 12f, 12g, and 12h that are D flip-flops. The latch circuits 12a, 12b, 12c, and 12d are first-stage latch circuits viewed from the reception side of the received signal, and the latch circuits 12e, 12f, 12g, and 12h are second-stage latches viewed from the reception side of the received signal. Circuit.

The reception signal SI is input to the latch circuits 12a, 12b, 12c, and 12d.
The clock signal φ0 is input to the latch circuits 12a and 12e. The clock signal φ1 is input to the latch circuits 12b and 12f. The clock signal φ2 is input to the latch circuits 12c and 12g. The clock signal φ3 is input to the latch circuits 12d and 12h.

  The output signal SX_0 of the latch circuit 12a is input to the latch circuit 12e. The output signal SX_1 of the latch circuit 12b is input to the latch circuit 12f. The output signal SX_2 of the latch circuit 12c is input to the latch circuit 12g. The output signal SX_3 of the latch circuit 12d is input to the latch circuit 12h.

  The output signal of the latch circuit 12e is output to the falling edge detection circuit 13 as the sampling signal SX0. The output signal of the latch circuit 12f is output to the falling edge detection circuit 13 as the sampling signal SX1. The output signal of the latch circuit 12g is output to the falling edge detection circuit 13 as the sampling signal SX2. The output signal of the latch circuit 12h is output to the falling edge detection circuit 13 as the sampling signal SX3.

  The falling edge detection circuit 13 in FIG. 1 is a circuit that detects the falling edges of the sampling signals SX0, SX1, SX2, and SX3 obtained by sampling by the four-phase sampling circuit 12, respectively. The specific configuration is as shown in FIG. 3, and two stages of flip-flops are arranged for each sampling signal.

  The difference between the falling edge detection circuit 13 and the sampling circuit 12 shown in FIG. 2 is that the clock signal to be used is only the reference clock signal φ0 and the number corresponding to the number of sampling signals for edge detection. The AND circuit is added. The falling edge detection circuit 13 outputs the edge detection result signals as DET0, DET1, DET2, and DET3. In the example illustrated in FIG. 3, the falling edge of the sampling signal is detected, but the rising edge may be detected depending on the logic level of the received signal.

  In the example shown in FIG. 3, the falling edge detection circuit 13 includes latch circuits 13a, 13b, 13c, 13d, 13e, 13f, 13g, and 13h, which are D flip-flops, and AND circuits 13i, 13j, 13k, 13l.

  The latch circuits 13a, 13b, 13c, and 13d are first-stage latch circuits viewed from the sampling signal reception side, and the latch circuits 13e, 13f, 13g, and 13h are second-stage latches viewed from the sampling signal reception side. Circuit.

  Latch circuits 13a, 13b, 13c, and 13d have a first output terminal and a second output terminal. The first output terminal is a terminal that outputs without inverting the level of the input signal, and the second output terminal is a terminal that inverts and outputs the level of the input signal.

The sampling signal SX0 from the sampling circuit 12 is input to the latch circuit 13a. The sampling signal SX1 from the sampling circuit 12 is input to the latch circuit 13b. The sampling signal SX2 from the sampling circuit 12 is input to the latch circuit 13c. The sampling signal SX3 from the sampling circuit 12 is input to the latch circuit 13d.
The clock signal φ0 is input to the latch circuits 13a, 13b, 13c, 13d, 13e, 13f, 13g, and 13h. Further, unlike the sampling circuit 12, the clock signals φ 1, φ 2 and φ 3 are not input to the falling edge detection circuit 13.

The output signal SS_0 from the first output terminal of the latch circuit 13a is input to the latch circuit 13e. An output signal from the second output terminal of the latch circuit 13a is input to the AND circuit 13i.
The output signal of the latch circuit 13e is output to the 4-input multiplexer 15 as the sampling signal SS0 and also input to the AND circuit 13i.

The output signal SS_1 from the first output terminal of the latch circuit 13b is input to the latch circuit 13f. An output signal from the second output terminal of the latch circuit 13b is input to the AND circuit 13j.
The output signal of the latch circuit 13f is output to the 4-input multiplexer 15 as the sampling signal SS1, and also input to the AND circuit 13j.

The output signal SS_2 from the first output terminal of the latch circuit 13c is input to the latch circuit 13g. An output signal from the second output terminal of the latch circuit 13c is input to the AND circuit 13k.
The output signal of the latch circuit 13g is output to the 4-input multiplexer 15 as the sampling signal SS2 and also input to the AND circuit 13k.

The output signal SS_3 from the first output terminal of the latch circuit 13d is input to the latch circuit 13h. An output signal from the second output terminal of the latch circuit 13d is input to the AND circuit 13l.
The output signal of the latch circuit 13h is output to the 4-input multiplexer 15 as the sampling signal SS3 and also input to the AND circuit 13l.

  The output signal of the AND circuit 13i is output to the sampling signal selection circuit 14 as the falling edge detection signal DET0. The output signal of the AND circuit 13j is output to the sampling signal selection circuit 14 as the falling edge detection signal DET1. The output signal of the AND circuit 13k is output to the sampling signal selection circuit 14 as the falling edge detection signal DET2. The output signal of the AND circuit 13l is output to the sampling signal selection circuit 14 as the falling edge detection signal DET3.

  The sampling signal selection circuit 14 shown in FIG. 1 decodes the falling edge detection signals DET0, DET1, DET2, and DET3, and based on the results, the sampling signals SS0 and SS1 from the falling edge detection circuit 13 are decoded. , SS2, SS3 is a circuit for selecting a signal most suitable for the subsequent reception processing. Actual signal selection is performed by the 4-input multiplexer 15.

  The specific configuration of the sampling signal selection circuit 14 is as shown in FIG. In the present embodiment, the sampling signal selection circuit 14 is configured to receive the idle signal IDLE from the serial-parallel conversion circuit 16. The idle signal IDLE indicates that the state state of the serial-parallel conversion circuit 16 is an idle state.

  Specifically, the idle signal IDLE has a logic level “0” when the serial-parallel conversion circuit 16 recognizes the start bit of the reception signal, and becomes logical when the serial-parallel conversion circuit 16 recognizes the stop bit of the reception signal. It is a signal whose level becomes “1”.

  With this idle signal IDLE, the selection signal SEL is fixed between the time when the serial-parallel conversion circuit 16 recognizes the start bit of the received signal and the time when the stop bit is recognized, that is, while the frame is being received. Be controlled. That is, the sampling signal selection circuit 14 continues to select the signal most suitable for reception processing until the start bit of the reception signal is recognized, and continues to hold the selection state until the end of the transmission frame during frame reception. It is controlled as follows.

  The sampling signal selection circuit 14 performs the signal selection operation at the timing when the falling edge detection circuit 13 detects the falling edge or rising edge of the start bit indicated by the sampling result of the received signal. Other than the timing, the previous selection state is maintained.

  The sampling signal selection circuit 14 shown in FIG. 4 includes AND circuits 14a, 14b, 14c, and 14d, OR circuits 14e, 14f, and 14g, an AND circuit 14h, and latch circuits 14i and 14j that are D flip-flops with enable. In the sampling signal selection circuit 14, AND circuits 14a, 14b, 14c, and 14d constitute a decoding circuit. This decoding circuit is a circuit for decoding the falling edge detection signals DET0, DET1, DET2, and DET3 every cycle of the reference clock signal.

The falling edge detection signal DET0 is input to the AND circuits 14a, 14b, 14c, and 14d. However, the falling edge detection signal DET0 is inverted and input in the AND circuits 14a, 14b, and 14d.
The falling edge detection signal DET1 is input to the AND circuits 14a, 14b, 14c, and 14d. However, the falling edge detection signal DET1 is inverted and input in the AND circuits 14a and 14b.
The falling edge detection signal DET2 is input to the AND circuits 14a, 14b, 14c, and 14d. However, the falling edge detection signal DET2 is inverted and input in the AND circuit 14b.
The falling edge detection signal DET3 is input to the AND circuits 14a, 14b, 14c, and 14d.

  The output signal DET_0 from the AND circuit 14a is input to the OR circuit 14e. The output signal DET_1 from the AND circuit 14b is input to the OR circuits 14e and 14f. The output signal DET_2 from the AND circuit 14c is input to the OR circuits 14e and 14g. The output signal DET_3 from the AND circuit 14d is input to the OR circuits 14e, 14f, and 14g.

  The idle signal IDLE and the output signal of the OR circuit 14e are input to the AND circuit 14h. The output signal of the AND circuit 14h is input to the enable terminals of the latch circuits 14i and 14j.

The output signal of the OR circuit 14f is input to the latch circuit 14i. The output signal of the OR circuit 14g is input to the latch circuit 14j.
The clock signal φ0 is input to the latch circuits 14i and 14j. The clock signals φ1, φ2, and φ3 are not input to the sampling signal selection circuit 14.

The output signal of the latch circuit 14i is input to the 4-input multiplexer 15 as the selection signal SEL [0].
The output signal of the latch circuit 14j is input to the 4-input multiplexer 15 as the selection signal SEL [1].

  The 4-input multiplexer 15 selects the sampling signal SS0 from the falling edge detection circuit 13 when the selection signal SEL [1] and the selection signal SEL [0] from the sampling signal selection circuit 14 are both “0”. The received signal S is output to the serial-parallel conversion circuit 16.

  Further, the 4-input multiplexer 15 has a falling edge detection circuit 13 when the selection signal SEL [1] from the sampling signal selection circuit 14 is “0” and the selection signal SEL [0] is “1”. The sampling signal SS1 is selected and output as the received signal S to the serial-parallel conversion circuit 16.

  Further, the 4-input multiplexer 15 has a falling edge detection circuit 13 when the selection signal SEL [1] from the sampling signal selection circuit 14 is “1” and the selection signal SEL [0] is “0”. Sampling signal SS2 is selected and output as a received signal S to the serial-parallel conversion circuit 16.

The 4-input multiplexer 15 receives the sampling signal SS3 from the falling edge detection circuit 13 when both the selection signal SEL [1] and the selection signal SEL [0] from the sampling signal selection circuit 14 are “1”. The received signal S is selected and output to the serial-parallel conversion circuit 16.
The signal selected in this way is a signal sampled by a clock signal that rises at a timing close to the center of the bit length of the start bit of the reception signal SI.

  Further, the sampling signals SX0 to SX3 from the second stage latch circuits 12e, 12f, 12g and 12h with respect to the signals SX_0 to SX_3 from the first stage latch circuits 12a, 12b, 12c and 12d of the four-phase sampling circuit 12. Is output with a delay of one cycle.

  Further, the signals SS_0 to SS_3 from the latch circuits 13a, 13b, 13c, and 13d in the falling edge detection circuit 13 are output with a delay of a maximum of one period with respect to the sampling signals SX0 to SX3 from the four-phase sampling circuit 12. .

  In the falling edge detection circuit 13, since the clock signals inputted to the latch circuits 13a to 13h are equal to only φ0, the output timings of the signals SS_0 to SS_3 from the latch circuits 13a to 13d are the same. The output timing of the sampling signals SS0 to SS3 from the latch circuits 13e to 13h is delayed by one cycle from the output timing of the signals SS_0 to SS_3 from the latch circuits 13a to 13d.

  The output timing of the falling edge detection signals DET0 to DET3 in the falling edge detection circuit 13 is synchronized with the falling of the signals SS_0 to SS_3 described above.

Here, a specific example from the input of the received signal to the output of the sampling signal will be given.
5, 6, 7 and 8 are timing charts showing examples of operation waveforms of the sampling circuit 12 in the first embodiment.
The output signals SX0, SX1, SX2, to SX3 of the sampling circuit 12 have the following four types of waveforms depending on the phase difference between the received signal SI and the reference clock signal φ0.

The first waveform shown in FIG. 5 is received signal SI at a timing close to the center of the pulse of the start bit of received signal SI, that is, just near the middle of the pulse falling timing and the subsequent rising timing. This is a waveform when the clock signal sampling the start bit is φ0.
The second waveform is the waveform shown in FIG. 6 when the clock signal sampling the start bit of the reception signal SI at a timing close to the center of the pulse of the reception signal SI is φ1.

  The third waveform is the waveform shown in FIG. 7 when the clock signal sampling the start bit of the reception signal SI at a timing close to the center of the pulse of the reception signal SI is φ2.

  The fourth waveform is the waveform shown in FIG. 8 when the clock signal sampling the start bit of the reception signal SI at a timing close to the center of the pulse of the reception signal SI is φ3.

Next, details of the first waveform described above will be described.
In the first waveform, after the start bit of the reception signal SI falls, the various clock signals rise in the order of clock signals φ2, φ3, φ0, and φ1.

When the clock signal φ2 rises in a state where the start bit of the reception signal SI falls and becomes “0”, the output signal SX_2 of the latch circuit 12c falls according to the start bit and becomes “0”.
Then, at the timing when the clock signal φ2 rises after the output signal SX_2 falls and becomes “0”, the output signal SX2 of the second stage latch circuit 12g falls and becomes “0”.

When the clock signal φ3 rises while the start bit of the reception signal SI falls to “0”, the output signal SX_3 of the latch circuit 12d falls according to the start bit and becomes “0”.
Then, at the timing when the clock signal φ3 rises after the output signal SX_3 falls and becomes “0”, the output signal SX3 of the second-stage latch circuit 12h falls and becomes “0”.

When the clock signal φ0 rises in a state where the start bit of the received signal SI falls and becomes “0”, the output signal SX_0 of the latch circuit 12a falls according to the start bit and becomes “0”.
Then, at the timing when the clock signal φ0 rises after the output signal SX_0 falls to “0”, the output signal SX0 of the second-stage latch circuit 12e falls according to the start bit and becomes “0”. Become.

When the clock signal φ1 rises in a state where the start bit of the reception signal SI falls and becomes “0”, the output signal SX_1 of the latch circuit 12b falls and becomes “0”.
Then, at the timing when the clock signal φ1 rises after the output signal SX_1 falls and becomes “0”, the output signal SX1 of the second-stage latch circuit 12f falls and becomes “0”.

  Therefore, the output order of the output signals SX_0 to SX_3 of the first-stage latch circuits 12a to 12d after the falling edge of the start bit of the received signal SI, that is, the order in which the output signals become “0” is SX_2, SX_3, SX_0, The order is SX_1. The output order of the output signals SX0 to SX3 of the second-stage latch circuits 12e to 12h after the falling of the reception signal SI, that is, the order in which the output signals become “0” is the order of SX2, SX3, SX0, SX1. It becomes.

Next, details of the second waveform described above will be described.
In the second waveform, after the start bit of the reception signal SI falls, the various clock signals rise in the order of the clock signals φ3, φ0, φ1, and φ2.

  Therefore, the output order of the output signals SX_0 to SX_3 of the first-stage latch circuits 12a to 12d after the falling edge of the start bit of the received signal SI, that is, the order in which the output signals become “0” is SX_3, SX_0, SX_1, The order is SX_2. The output order of the output signals SX0 to SX3 of the second-stage latch circuits 12e to 12h after the falling of the reception signal SI, that is, the order in which the output signals become “0” is the order of SX3, SX0, SX1, and SX2. It becomes.

Next, details of the third waveform described above will be described.
In the third waveform, after the start bit of the reception signal SI falls, the various clock signals rise in the order of the clock signals φ0, φ1, φ2, and φ3.

  Therefore, the output order of the output signals SX_0 to SX_3 of the first-stage latch circuits 12a to 12d after the falling edge of the start bit of the received signal SI, that is, the order in which the output signals become “0” is SX_0, SX_1, SX_2, The order is SX_3. The output order of the output signals SX0 to SX3 of the second-stage latch circuits 12e to 12h after the falling of the reception signal SI, that is, the order in which the output signals become “0” is the order of SX0, SX1, SX2, and SX3. It becomes.

Next, details of the fourth waveform described above will be described.
In the fourth waveform, after the start bit of the reception signal SI falls, the various clock signals rise in the order of the clock signals φ1, φ2, φ3, and φ0.

  Therefore, the output order of the output signals SX_0 to SX_3 of the first-stage latch circuits 12a to 12d after the falling edge of the start bit of the received signal SI, that is, the order in which the output signals become “0” is SX_1, SX_2, SX_3. The order is SX_0. The output order of the output signals SX0 to SX3 of the second-stage latch circuits 12e to 12h after the falling of the reception signal SI, that is, the order in which the output signals become “0” is the order of SX1, SX2, SX3, SX0. It becomes.

9, FIG. 10, FIG. 11, and FIG. 12 are timing charts showing examples of operation waveforms of the falling edge detection circuit in the first embodiment.
The output waveform of the falling edge detection circuit 13 is the first waveform shown in FIG. 9, the second waveform shown in FIG. 10, and the output waveform shown in FIG. 11, depending on the phase difference between the received signal SI and the reference clock signal φ0. One of four types of waveforms, which is the third waveform and the fourth waveform shown in FIG.

As shown in FIG. 5, the first waveform shown in FIG. 9 is that the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ0, and the first waveform from the sampling circuit 12 This is a waveform when the signal input order is signals SX2, SX3, SX0, SX1.
The second waveform shown in FIG. 10 is a waveform when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ1, as shown in FIG. This is a waveform when the input order of signals from the sampling circuit 12 is the signals SX3, SX0, SX1, and SX2.
As shown in FIG. 7, the third waveform shown in FIG. 11 is that the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ2, This is a waveform when the signal input order is the signals SX0, SX1, SX2, SX3.
As shown in FIG. 8, the fourth waveform shown in FIG. 12 is that the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ3. This is a waveform when the signal input order is signals SX1, SX2, SX3, SX0.

Next, details of the first waveform shown in FIG. 9 will be described.
In the first waveform, the signals SX2 and SX3 have already fallen to “0” at the timing when the reference clock signal φ0 rises first after the input of the signal SX2 whose order of input from the sampling circuit 12 is first. The signal SX1 is “1”. At this timing, the signal SX0 falls from “1” to “0” as the reference clock signal φ0 rises.

  At this timing, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “1”, “1”, “0”, and “0”, and the reference clock signal φ0 Output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h at the next rise timing are similarly “1”, “1”, “0”, and “0”. Become.

  At the timing when the reference clock signal φ0 first rises, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “1”, “1”, “0” and “0” are output, and as described above, signals whose levels are inverted are output from the second output terminals of the latch circuits 13a, 13b, 13c, and 13d to the AND circuits 13i, 13j, 13k, and 13l. Is done.

  At this timing, the output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h are all “1” before falling, so that the AND circuits 13i and 13j , 13k, and 13l output signals DET0, DET1, DET2, and DET3 are “0”, “0”, “1”, and “1”. That is, in the first waveform shown in FIG. 9, DET2 and DET3 of the output signals DET0 to DET3 are preceded by “1”.

Next, details of the second waveform shown in FIG. 10 will be described.
In the second waveform, the signal SX3 has already fallen at the timing when the reference clock signal φ0 rises first after the signal SX3 input in the first order from the sampling circuit 12 is input by the falling edge detection circuit 13. The signals SX1 and SX2 are “1”.

  At this timing, the output signals SS_0, SS_1, SS_2, and SS_3 from the first stage latch circuits 13a, 13b, 13c, and 13d are “1”, “1”, “1”, “0”, and the reference clock signal φ0. Output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h at the next rise timing are similarly “1”, “1”, “1”, and “0”. Become.

  At the timing when the reference clock signal φ0 first rises, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “1”, “1”, “1” and “0”, and as described above, signals whose levels are inverted are output from the second output terminals of the latch circuits 13a, 13b, 13c, and 13d to the AND circuits 13i, 13j, 13k, and 13l. Is done.

  At this timing, the output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h are all “1” before falling, so that the AND circuits 13i and 13j , 13k, and 13l output signals DET0, DET1, DET2, and DET3 are “0”, “0”, “0”, and “1”. That is, in the second waveform shown in FIG. 10, DET3 precedes “1” among the output signals DET0 to DET3.

Next, the details of the third waveform shown in FIG. 11 will be described.
In the third waveform, the signals SX1, SX2, SX3 are input at the timing when the reference clock signal φ0 first rises after the signal SX0 input first from the sampling circuit 12 is input by the falling edge detection circuit 13. Has already fallen to "0".

  At this timing, the output signals SS_0, SS_1, SS_2, and SS_3 from the first stage latch circuits 13a, 13b, 13c, and 13d are “0”, and the second stage at the timing when the reference clock signal φ0 rises next time. The output signals SS0, SS1, SS2, and SS3 from the latch circuits 13e, 13f, 13g, and 13h are also “0”.

  At the timing when the reference clock signal φ0 first rises, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “0” as described above. In addition, these inverted signals are output from the second output terminals of the latch circuits 13a, 13b, 13c, 13d to the AND circuits 13i, 13j, 13k, 13l.

  At this timing, the output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h are all “1” before falling, so that the AND circuits 13i and 13j , 13k, and 13l, the output signals DET0, DET1, DET2, and DET3 are all “1”.

Next, details of the fourth waveform shown in FIG. 12 will be described.
In the first waveform, the signals SX1, SX2, and SX3 are input at the timing when the reference clock signal φ0 first rises after the signal SX1 that is input first from the sampling circuit 12 is input by the falling edge detection circuit 13. Has already fallen to "0".

  At this timing, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “1”, “0”, “0”, “0”, and the reference clock signal φ0 Output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h at the next rise timing are similarly “1”, “0”, “0”, and “0”. Become.

  At the timing when the reference clock signal φ0 first rises, the output signals SS_0, SS_1, SS_2, and SS_3 from the first-stage latch circuits 13a, 13b, 13c, and 13d are “1”, “0”, “0” and “0” are output, and as described above, signals whose levels are inverted are output from the second output terminals of the latch circuits 13a, 13b, 13c, and 13d to the AND circuits 13i, 13j, 13k, and 13l. Is done.

  At this timing, the output signals SS0, SS1, SS2, and SS3 from the second-stage latch circuits 13e, 13f, 13g, and 13h are all “1” before falling, so that the AND circuits 13i and 13j , 13k, and 13l output signals DET0, DET1, DET2, and DET3 are “0”, “1”, “1”, and “1”. That is, in the fourth waveform shown in FIG. 12, among the output signals DET0 to DET3, DET1, DET2, and DET3 are preceded by “1”.

FIG. 13, FIG. 14, FIG. 15, and FIG. 16 are timing charts showing examples of operation waveforms of the sampling signal selection circuit in the first embodiment.
The output waveform of the sampling signal selection circuit 14 is based on the waveforms of the signals DET0 to DET3 from the falling edge detection circuit 13, and the first waveform shown in FIG. 13, the second waveform shown in FIG. 14, and the waveform shown in FIG. The third waveform is one of four types of waveforms consisting of the fourth waveform shown in FIG.

The first waveform shown in FIG. 13 is a waveform when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ0, as shown in FIG.
The second waveform shown in FIG. 14 is a waveform when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ1, as shown in FIG.

The third waveform shown in FIG. 15 is a waveform when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ2, as shown in FIG.
The fourth waveform shown in FIG. 16 is a waveform when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ3, as shown in FIG.

Next, details of the first waveform shown in FIG. 13 will be described.
As shown in FIG. 4, the signal DET0 from the falling edge detection circuit 13 is inverted on the input side of the AND circuits 14a, 14b, and 14d, the signal DET1 is inverted on the input side of the AND circuits 14a and 14b, and the signal DET2 is It is inverted at the input side of the AND circuit 14b.

  As shown in FIG. 13, the signals DET0, DET1, DET2, and DET3 input to the AND circuits 14a, 14b, 14c, and 14d of the sampling signal selection circuit 14 are “0”, “0”, “1”, “1”. , The signals DET_0, DET_1, DET_2, and DET_3 input from the AND circuits 14a, 14b, 14c, and 14d are “1”, “0”, “0”, and “0”.

  Then, the output of the OR circuit 14e becomes “1”, and the outputs of the OR circuits 14f and 14g become “0”. Under the condition that the IDOL signal is “1”, the output from the AND circuit 14h is “1”, and this signal is output from the latch circuits 14i and 14j when the signal is input to the enable terminals of the latch circuits 14i and 14j. The selection signals SEL [0] and SEL [1] are both “0”.

  As described above, when the selection signal SEL [1] and the selection signal SEL [0] from the sampling signal selection circuit 14 are both “0”, the 4-input multiplexer 15 performs sampling from the falling edge detection circuit 13. The signal SS0 is selected and output to the serial-parallel conversion circuit 16 as a reception signal S.

  Thus, as shown in FIG. 5, when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ0, the signal sampled by the clock signal φ0 SS0 will be selected.

Next, the details of the second waveform shown in FIG. 14 will be described.
As shown in FIG. 14, the signals DET0, DET1, DET2, and DET3 input to the AND circuits 14a, 14b, 14c, and 14d of the sampling signal selection circuit 14 are “0”, “0”, “0”, “1”. , The signals DET_0, DET_1, DET_2, and DET_3 input from the AND circuits 14a, 14b, 14c, and 14d are “0”, “1”, “0”, and “0”.

  Then, the output of the OR circuit 14e becomes “1”, the output of the OR circuit 14f becomes “1”, and the output of the OR circuit 14g becomes “0”. Under the condition that the IDOL signal is “1”, the output from the AND circuit 14h is “1”, and this signal is output from the latch circuits 14i and 14j when the signal is input to the enable terminals of the latch circuits 14i and 14j. The selection signal SEL [0] is “1”, and the selection signal SEL [1] is “0”.

  As described above, the 4-input multiplexer 15 has a falling edge when the selection signal SEL [1] from the sampling signal selection circuit 14 is “0” and the selection signal SEL [0] is “1”. The sampling signal SS1 from the detection circuit 13 is selected and output to the serial-parallel conversion circuit 16 as a reception signal S.

  Thus, as shown in FIG. 6, when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ1, the signal sampled by this clock signal φ1 SS1 is selected.

Next, the details of the third waveform shown in FIG. 15 will be described.
As shown in FIG. 15, when the signals DET0, DET1, DET2, and DET3 input to the AND circuits 14a, 14b, 14c, and 14d of the sampling signal selection circuit 14 all become “1”, the AND circuits 14a, Signals DET_0, DET_1, DET_2, and DET_3 input from 14b, 14c, and 14d are “0”, “0”, “1”, and “0”.

  Then, the output of the OR circuit 14e becomes “1”, the output of the OR circuit 14f becomes “0”, and the output of the OR circuit 14g becomes “1”. Under the condition that the IDOL signal is “1”, the output from the AND circuit 14h is “1”, and this signal is output from the latch circuits 14i and 14j when the signal is input to the enable terminals of the latch circuits 14i and 14j. The selection signal SEL [0] is “0”, and the selection signal SEL [1] is “1”.

  As described above, the 4-input multiplexer 15 has a falling edge when the selection signal SEL [1] from the sampling signal selection circuit 14 is “1” and the selection signal SEL [0] is “0”. The sampling signal SS2 from the detection circuit 13 is selected and output to the serial-parallel conversion circuit 16 as a reception signal S.

  Thus, as shown in FIG. 7, when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ2, the signal sampled by this clock signal φ2 SS2 will be selected.

Next, the details of the fourth waveform shown in FIG. 16 will be described.
As shown in FIG. 16, the signals DET0, DET1, DET2, and DET3 input to the AND circuits 14a, 14b, 14c, and 14d of the sampling signal selection circuit 14 are “0”, “1”, “1”, “1”. , The signals DET_0, DET_1, DET_2, and DET_3 input from the AND circuits 14a, 14b, 14c, and 14d are “0”, “0”, “0”, and “1”.

  Then, the output of the OR circuit 14e is “1”, and the outputs of the OR circuits 14f and 14g are both “1”. Under the condition that the IDOL signal is “1”, the output from the AND circuit 14h is “1”, and this signal is output from the latch circuits 14i and 14j when the signal is input to the enable terminals of the latch circuits 14i and 14j. Both the selection signal SEL [0] and the selection signal SEL [1] are “1”.

  As described above, the 4-input multiplexer 15 performs sampling from the falling edge detection circuit 13 when the selection signal SEL [1] and the selection signal SEL [0] from the sampling signal selection circuit 14 are both “1”. The signal SS3 is selected and output to the serial-parallel conversion circuit 16 as a reception signal S.

  Thus, as shown in FIG. 8, when the clock signal sampling the start bit of the received signal SI at a timing close to the center of the pulse is φ3, the signal sampled by this clock signal φ3 SS3 is selected. Therefore, an appropriate signal is selected as a signal according to the received signal from signals sampled using various clock signals.

  The serial-parallel conversion circuit 16 shown in FIG. 1 is a circuit that converts the serial reception signal S selected by the sampling signal selection circuit 14 into parallel data. The serial-parallel conversion circuit 16 basically operates in the same manner as a general asynchronous circuit that starts conversion by using start bit recognition as a trigger, but the only difference is the serial-parallel conversion circuit 16. Then, since the sampling process has already been performed in the preceding stage, the circuit of that part can be omitted. That is, the serial-parallel conversion circuit 16 requires a smaller circuit cost than a circuit used for a general asynchronous process.

  Here, the features of the present embodiment will be described. In the asynchronous serial transmission receiving circuit shown in FIG. 1, only the four-phase sampling circuit 12 uses φ1, φ2, and φ3 other than the reference clock signal φ0. In the design of a logic circuit that uses a plurality of clock signals as well as multiphase clock signals, the more complex the clock domain (the configuration of the flip-flop to which each clock is connected), the more difficult it is to mount on the semiconductor device 1. .

  In particular, FPGA devices that have become widely used in recent years may not be mountable due to the lower allowable limit of the clock domain compared to custom devices such as ASIC (Application Specific Integrated Circuits). . Also, this tolerance limit tends to be lower as the FPGA device is cheaper, so the complexity of the clock domain leads to a jump in the cost of the FPGA device.

  On the other hand, the receiving circuit shown in FIG. 1 minimizes the number of flip-flops covered by φ1, φ2, and φ3 other than the reference clock signal φ0 (specifically, two each in the four-phase sampling circuit 12). This simplifies the clock domain to the limit and facilitates mounting on an inexpensive FPGA device.

  As described so far, the configuration of the receiver circuit for asynchronous serial transmission shown in FIG. 1 is very simple and does not require any special circuit technology. In the embodiment of FIG. 1, a receiver circuit using a four-phase clock is shown. However, in this embodiment, even when a transmission speed of, for example, 100 Mbps is realized by increasing the number of clock phases, reception of asynchronous serial transmission is performed. The operation frequency of the circuit can be suppressed to 100 MHz, and even an inexpensive FPGA device can be easily realized.

  As a result, the operation frequency of the transmission circuit had to be at least about 1.6 GHz in order to realize a transmission rate of 100 Mbps with the conventional general asynchronous method, but the method in this embodiment is significantly low. It becomes possible to suppress to 100MHz. Therefore, the transmission speed is not limited when the operating frequency is determined, which can contribute to data redundancy (increase in data amount) and shortening of the transmission cycle. In addition, it is not necessary to increase the operating frequency when the transmission speed is fixed, which can contribute to cost reduction and power saving of the device. Conventionally, in order to realize serial transmission of the 100 Mbps class, it is usual to use a clock synchronization method in which a clock signal is superimposed on the data of the transmission line, and in this case, it is necessary to partially configure an analog circuit. There were some restrictions. However, in the method according to the present embodiment, the circuit configuration is not limited as described above, so that it can be easily mounted on an inexpensive FPGA device.

  Therefore, the asynchronous transmission serial transmission receiving circuit according to the present embodiment has the advantage that the circuit configuration can be simplified, which is inherent in the asynchronous transmission serial transmission circuit, and the serial transmission of the clock synchronous system. The receiver circuit has the advantage that the transmission speed is not limited when the operating frequency is determined, and that the operating frequency does not need to be significantly increased when the transmission speed is determined. Can do.

(Second Embodiment)
Next, a second embodiment will be described. Note that, in the configuration of the receiver circuit for asynchronous serial transmission in this embodiment, the description of the same part as the configuration described in the first embodiment is omitted.
FIG. 17 is a block diagram illustrating an example of a receiver circuit for asynchronous serial transmission according to the second embodiment.
As shown in FIG. 17, the asynchronous serial transmission receiving circuit according to the second embodiment includes a clock generation circuit 10a, a noise removal circuit 11, a sampling circuit 21, a falling edge detection circuit 13, a sampling signal selection circuit 14, 4 and the like. An input multiplexer 15 and a serial-parallel conversion circuit 16 are provided.

  That is, in the second embodiment, the asynchronous serial transmission receiving circuit includes the clock generation circuit 10a instead of the four-phase clock generation circuit 10 provided in the first embodiment. A sampling circuit 21 is provided instead of the four-phase sampling circuit 12 provided.

  The clock generation circuit 10a shown in FIG. 18 outputs two clock signals (φ0, φ1) from the clock signal input from the outside of the semiconductor device 1 via the input terminal and the input buffer.

  In this embodiment, of the clock signals φ0 and φ1 output from the clock generation circuit 10a, the clock signal φ0 is a reference clock signal, and the clock signal φ1 is a clock signal whose phase is delayed by 90 degrees with respect to φ0. That is, in the first embodiment, the four-phase clock generation circuit 10 receives four clock signals (φ0, φ1, φ2, φ3 from the clock signal input from the outside of the semiconductor device 1 via the input terminal and the input buffer. However, in the second embodiment, the clock generation circuit 10a outputs only two clock signals (φ0, φ1).

  The sampling circuit 21 shown in FIG. 17 is a circuit that samples the reception signal SI after the noise removal by the noise removal circuit 11 with the two-phase clock signals φ0 and φ1. The specific configuration and timing chart of each clock signal are as shown in FIGS. 18A and 18B, respectively, and two stages of flip-flops are arranged for each clock signal as a countermeasure against metastable. ing.

In the example shown in FIG. 18A, the sampling circuit 21 includes latch circuits 21a, 21b, 21c, 21d, 21e, 21f, 21g, and 21h, which are D flip-flops. The reception signal SI is input to the latch circuits 21a, 21b, 21c, and 21d.
The clock signal φ0 is input to the latch circuits 21a and 21e. The clock signal φ1 is input to the latch circuits 21b and 21f. A signal obtained by inverting the clock signal φ0 is input to the latch circuits 21c and 21g. A signal obtained by inverting the clock signal φ1 is input to the latch circuits 21d and 21h. That is, in the second embodiment, the signal obtained by inverting the clock signal φ0 has the same function as the clock signal φ2 described in the first embodiment, and the signal obtained by inverting the clock signal φ1 is described in the first embodiment. Performs the same function as the clock signal φ3.

  The output signal SX_0 of the latch circuit 21a is input to the latch circuit 21e. The output signal SX_1 of the latch circuit 21b is input to the latch circuit 21f. The output signal SX_2 of the latch circuit 21c is input to the latch circuit 21g. The output signal SX_3 of the latch circuit 21d is input to the latch circuit 21h.

The output signal of the latch circuit 21e is output to the falling edge detection circuit 13 as the sampling signal SX0. The output signal of the latch circuit 21f is output to the falling edge detection circuit 13 as the sampling signal SX1. The output signal of the latch circuit 21g is output to the falling edge detection circuit 13 as the sampling signal SX2. The output signal of the latch circuit 21h is output to the falling edge detection circuit 13 as the sampling signal SX3.
The operations of the falling edge detection circuit 13, the sampling signal selection circuit 14, the 4-input multiplexer 15, and the serial-parallel conversion circuit 16 are the same as those in the first embodiment.

  That is, in the second embodiment, since the signal obtained by inverting the clock signal for two phases is used as the clock signal for two phases, in the configuration provided with a circuit for generating two clock signals, The same effect as in the first embodiment can be obtained.

  Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... 4 phase clock generation circuit, 10a ... Clock generation circuit, 11 ... Noise removal circuit, 12 ... 4 phase sampling circuit, 13 ... Falling edge detection circuit, 14 ... Sampling signal selection circuit, 15 ... 4 Input multiplexer, 16... Serial-parallel conversion circuit, 21... Sampling circuit, .phi.0 .reference clock signal, .phi.1 .phi.0 phase delayed clock signal, .phi.2 .phi.0 phase delayed 180.degree. Signal, clock signal delayed in phase by 270 degrees with respect to φ3, φ0, SI, received signal after noise removal, SX0, sampling signal obtained by sampling SI with φ0, SX1, ... sampling signal obtained by sampling SI with φ1, SX2,. Sampling signal with SI sampled at φ2, SX3 ... sampled at SI φ3 Sampling signal, SS0... SX0 sampled at φ0, SS1... SX1 sampled at φ0, SS2... SX2 sampled at φ0, SS3... SX3 sampled at φ0, DET0 ... SX0 falling edge detection signal, DET1 ... SX1 falling edge detection signal, DET2 ... SX2 falling edge detection signal, DET3 ... SX3 falling edge detection signal, IDLE ... Serial-parallel conversion circuit 16 is idle , SEL [1], SEL [0], a selection signal of the sampling signal selection circuit 14, and S, a reception signal selected by the sampling signal selection circuit 14.

Claims (4)

N sampling circuits for sampling a received signal using N multiphase clock signals, each of which includes a plurality of clock signals having the same frequency, and one is a reference clock signal;
N edge detection circuits for detecting a falling edge or a rising edge of a signal sampled by the sampling circuit in a cycle of the reference clock signal among the multiphase clock signals;
The detection result by the edge detection circuit is decoded every cycle of the reference clock signal, and based on the decoding result, a signal corresponding to the received signal is selected from the N sampled signals by the sampling circuit. A selection circuit for selecting an appropriate signal;
A start circuit for asynchronous serial transmission, comprising: a conversion circuit for serial-parallel conversion of the sampled signal selected by the selection circuit. The selection circuit includes:
A new selection operation of the appropriate one signal is performed at the timing when the falling edge or the rising edge of the start bit of the received signal is detected, and the previous selection state is held at other timing than the detected timing. The receiver circuit for asynchronous serial transmission according to claim 1. The selection circuit includes:
Until the conversion circuit recognizes the start bit of the received signal until it recognizes the stop bit of the received signal, the previous selection state is maintained without performing a new selection operation of the appropriate signal. The receiver circuit for asynchronous serial transmission according to claim 2, wherein the receiver circuit continues. N sampling circuits for sampling a received signal using N multiphase clock signals, each of which includes a plurality of clock signals having the same frequency, and one of which is a reference clock signal, and the reference among the multiphase clock signals A method used for a start circuit for asynchronous serial transmission having N edge detection circuits for detecting a falling edge or a rising edge of a signal sampled by the sampling circuit in a cycle of a clock signal,
The detection result by the edge detection circuit is decoded every cycle of the reference clock signal, and based on the decoding result, a signal corresponding to the received signal is selected from the N sampled signals by the sampling circuit. Choose the right signal,
A reception method for asynchronous serial transmission, wherein the selected sampled signal is serial-parallel converted.

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