JP3717173B2 - Digital data receiving apparatus and digital data receiving method - Google Patents

Description

  The present invention relates to an STL (Studio Transmitter Link) receiving apparatus and a receiving method for receiving a digital broadcast signal transmitted from a broadcasting station (performer) or the like to a transmitting station, and in particular, the digital broadcast signal is provided for a preliminary purpose. The present invention relates to a digital data switching technique that is received by a receiver of more than one system and selects one system from the receiver output signals of each system.

  In an STL (Studio Transmitter Link) receiving device that receives a digital broadcast signal sent from a broadcasting station (performer) or the like to a transmitting station, the digital broadcast signal is received by two or more receivers provided for preliminary purposes. 2. Description of the Related Art There is known a digital data receiving apparatus provided with a system switching device that selects one system among receiver output signals of each system.

  As an example of such a prior art, Japanese Patent Laid-Open No. 11-17669 discloses a phase synchronization circuit that synchronizes the phases of a clock and a plurality of data in a communication system having a system switching device. In this prior art, a phase synchronization circuit (6) is provided after the system switching device (3).

  As another example of the prior art, in Japanese Patent Laid-Open No. 8-251151, a FIFO memory (2) is provided in front of the system switching circuit (7), and 2 is input to the switching circuit (7) by the FIFO memory. The signals of the two systems are synchronized.

  In Japanese Patent Laid-Open No. 11-17669, the system switching device (3) is based on the relationship between the phase difference between the clock signals of the two input digital signals and the selection switching timing when the system is selected at any time. May cause missing clocks or missing data due to variations in the amount of jitter generated in each signal. Therefore, when a signal is output from the system switching device (3) in which the clock loss or data loss has occurred, the loss cannot be reproduced by the subsequent phase synchronization circuit (6) or optical transmission circuit (10). A signal with a data error will be transmitted.

  On the other hand, in Japanese Patent Application Laid-Open No. 8-251151, the operation of the 1 / N frequency divider (12) of the read control unit (1) for controlling the read operation of the FIFO memory (2) is set in units of frames. The frame pulse is extracted and controlled by the frame synchronization circuit (3, 4) so as to synchronize with the signal DATAR or DATAI. However, since DATAAR and DATAI must be in units of frames and they need to be frame-synchronized, it is not easy to use the technique of this publication for signals that are not frame-synchronized.

  Also, a conventional digital data receiving apparatus provided with a system switching device for receiving a digital broadcast signal by two or more receivers provided for a preliminary purpose and selecting one of the receiver output signals of each system. This technique will be described with reference to FIG.

  A digital broadcast signal transmitted from a broadcasting station (performance station) to a transmitting station is received by the antenna 10 of the STL receiver 1 and distributed to the receivers 20 of the first and second machines. The digital broadcast signal is converted into an IF signal by the down converter 21 in the receiver 20 and demodulated by the demodulator 22. The digital data demodulated by the demodulator 22 is separated into TS (Transport Stream) data and TS clock included in the digital data by the separation device 23.

  The TS data 30-2 and 30-4 and the clocks 30-1 and 30-3 obtained by the separation device 23 of each system are input to the switching device 30. The TS data 30-2 and 30-4 and the clocks 30-1 and 30-3 input to the switching device 30 are set in each selector 31 according to the switching control signal 30-7 output from the switching control device 40. Unit 2 TS data and clock are selected. The TS data and the clock selected by the selector 31 are distributed by the distributor 32 and output to the broadcasting machine 50 (the first machine and the second machine (preliminary machine)).

  FIG. 6 shows signal waveforms in the switching device 30 of FIG. A signal received by the antenna 10 of the STL receiver 1 is distributed to the first and second receivers 20. Although the data input to the receivers 20 of the first and second units is the same, there is an individual difference between the receivers 20 of the first and second units, so TS data output from the receivers 20 of the first and second units And the clock (No. 1 TS clock 30-1, No. 1 TS data 30-2 and No. 2 TS clock 30-3, No. 2 TS data 30-4) have a phase difference as shown by the phase difference 30-c in FIG. And each signal has jitter.

  Specifically, when the first signal is selected when the switching signal 30-7 in FIG. 6 is “Hi” and the second signal is selected when the switching signal 30-7 is “Low”, the signals having the above phase difference and different jitters are connected. When the switching signal 30-7 changes from “Hi” to “Low”, the switching clock 30-5 in FIG. 5 and the switching data 30-6 in FIG. Noise occurs in the clock and data.

  As a result, the output TS clock 30-8, the output TS clock 30-10, the output TS data 30-9, and the output TS data 30-11 output from the switching device 30 in FIG. As shown in the noise 30-e, a discontinuous section occurs.

During operation at Unit 1, Unit 1 may be switched to Unit 2 for maintenance and inspection of Unit 1, and Unit 1 may be stopped. On the other hand, there is a case where the second unit is switched to the first unit. When this switching is performed, a discontinuous section is generated in the TS clock and TS data, and this causes a problem that a freeze or the like occurs in an image, sound, or the like.
Japanese Patent Laid-Open No. 11-17669 JP-A-8-251151

  An object of the present invention is to provide a digital data receiving method and apparatus capable of solving the above-mentioned problems of the prior art.

  Another object of the present invention is to provide a digital data receiving method and apparatus in which a discontinuous period does not occur in received data when switching from one system of two or more receiver output signals to another system. Is to provide.

  The present invention provides a digital data receiving apparatus that distributes the same received signal to two systems, demodulates the two systems of received signals, respectively, obtains and outputs a plurality of data streams of two systems, and And a switching unit that selects and outputs a plurality of data streams of one of the plurality of data streams. In the digital data receiving method, the same received signal is divided into two systems. Distributing and demodulating each of the two received signals to obtain and output a plurality of data streams of two systems, and selecting a plurality of data streams of one of the plurality of data streams of the two systems Output.

  The receiving unit stores, for each of the plurality of data streams of the two systems, a storage unit that temporarily stores the clock in the data stream of the system, and the two systems of data streams temporarily stored in the storage unit Are respectively read simultaneously, and a clock control unit that generates a clock that is output in pairs with a data stream that is selected by the selection unit and output from the digital data receiving device.

  Furthermore, according to an example of the present invention, the clock control unit of the reception unit generates a clock having a frequency 1 / N (N is a positive number) of the clock frequency of each system for each of the two data streams. A frequency divider that synchronizes the frequency divider, a selector that selects one of the clocks having a frequency 1 / N of the two clock frequencies from the frequency divider, And a multiplier for multiplying a clock having a frequency of 1 / N of the clock frequency selected by the selector by N, and an output clock of the frequency divider synchronizer is used as an output clock of the clock controller.

  According to an example of the present invention, in the clock control unit of the receiving unit, the constant N of the frequency divider and the multiplier is any integer between 4 and 8.

  According to the present invention, the TS clock and TS data are not interrupted even when switching between the receiver No. 1 20A and No. 2 No. 20B during the reception of digital data. A digital data receiving apparatus capable of seamless switching can be realized.

  Hereinafter, embodiments of a digital data receiving apparatus and a receiving method provided with a system switching apparatus according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a digital data receiving apparatus having a system switching device according to this embodiment, FIG. 2 is a block diagram showing the configuration of the system switching device of FIG. 1, and FIG. FIG. 3 is a timing chart showing signal waveforms in respective parts of FIG. 1 and FIG. 2.

  A STL (Studio Transmitter Link) receiver 100 in FIG. 1 generates TS (Transport Stream) data and a clock based on a digital broadcast signal received by an antenna 10 and transmits them to broadcasters 50A and 50B (No. 1 and No. 2). Output. The receiving device 100 includes first and second receivers 20A and 20B, a switching control device 40, and a switching device 300. The receiving apparatus 100 inputs the digital broadcast signal received by the antenna 10 to the first and second receivers 20A and 20B, respectively. The input digital broadcast signals are converted into IF (Intermediate Frequency) signals by down converters 21A and 21B in receivers 20A and 20B, respectively, and demodulated by demodulators 22A and 22B. The digital data demodulated by the demodulators 22A and 22B are separated into TS (Transport Stream) data (DATA) and TS clock (CLK) included in the digital data by the separating devices 23A and 23B, respectively. The No. 1 TS clock 30-1 (FIG. 3A) and the No. 1 TS data 30-2 (FIG. 3B) output from the No. 1 receiver 20A are input to the No. 1 synchronization controller 33A. There, the synchronization code in the No. 1 TS data 30-2 is detected. From this synchronization code, the control (write reset) signal CTL of the first unit memory 34A is generated by the synchronization controller 33A.

  That is, in response to the No. 1 TS clock 30-1 and the control signal CTL generated by the No. 1 synchronous controller 33A, the No. 1 TS data 30-2 is written in the No. 1 memory 34A. Similarly, in response to the No. 2 TS clock 30-3 (FIG. 3C) and the control signal CTL generated by the No. 2 synchronous controller 33B, the No. 2 TS data 30-4 (FIG. 3D) )) Is written to the memory 34B for the second machine.

  On the other hand, in the clock control unit 35, the 1st TS clock 30-1 and the 2nd TS clock 30-3 are input to the clock control unit 35. Of these input No. 1 TS clock 30-1 and No. 2 TS clock 30-3, one TS clock selected by the clock selector 352 is supplied to the PLL (353-355) multiplied by 1 in the clock control unit 35. Then, a 1 × clock 30-5 (FIG. 3F) is generated by the 1 × PLL, and data is read from the memories 34A and 34B by the 1 × clock 30-5.

  The multiplied clock 30-5 is input to both the memories 34A and 34B for the first and second machines, and is used to read data from the respective memories. The multiplied clock 30-5 is also input to a data control unit 37 for generating control (read reset) signals for the memories 34A and 34B for both the first and second machines.

  As a result, the memories 34A and 34B for Unit 1 and Unit 2 are read-controlled with the same clock (switched clock 30-5) as the control signal CTL and the same control signal 371-2. Therefore, as shown in FIGS. 2G and 2H, the No. 1 TS read data 3-17 and the No. 2 TS read data 3-18 output from the memories 34A and 34B are synchronized.

  Therefore, in response to the timing 30-i by the switching signal 30-7 (FIG. 3E) from the switching control device 40, the data selectively output by the selector 31 is the TS of No. 1 and No. 2. When switching from one of the data 3-17 and 3-18 to the other (for example, from the TS data 3-17 to 3-18), the clock control unit 35 and the data control unit 37 actually perform switching successfully. The timing 30-j that can be obtained is obtained.

  That is, in the selector 31, the 1st TS read data 3-17 or the 2nd TS read data 3-17 is generated in accordance with the switching signal 372-1 generated based on the one-time clock 30-5 from the clock control unit 35. 18 is switched and selected at timing 30-j, and data 30-6 is output from the selector 31.

  As a result, both the output TS clock 30-8 and the output TS clock 30-10 are output as the same clock based on the clock 30-5 generated by the 1 × PLL in the clock control unit 35. In the selector 31, the output TS data 30-9 and the output TS data 30-11 are switched by a signal synchronized with the TS clock 30-5 as shown in FIGS. 3 (G) to 3 (J). Data continuity is not impaired before and after data switching. That is, there is no data discontinuity section before and after data switching.

  Specific configuration examples and operations of the clock control unit 35 and the data control unit 37 of the switching device 300 illustrated in FIG. 1 will be described in more detail with reference to FIGS.

  In the clock control unit 35, the input No. 1 TS clock 30-1 is frequency divided by 1 / N by the frequency divider 351A. Similarly, the input No. 2 TS clock 30-3 is frequency-divided by 1 / N by the frequency divider 351B. The No. 1 TS clock 30-1 frequency divider 351A and the No. 2 TS clock 30-3 frequency divider 351B each have a frequency-dividing synchronizer that resets the frequency dividing operation of the other party at its output. It is configured as.

  A clock 351-1 obtained by dividing the frequency of the No. 1 TS clock 30-1 by 1 / N and a clock 351-3 obtained by dividing the frequency of the No. 2 TS clock 30-3 by 1 / N are: Are output from the frequency dividers 351A and 351B, respectively. These clocks 351-1 and 351-3 are input to the clock selector 352, and one of them is selected and output by the clock selector 352 according to the switching control signal 30-7 output from the switching control device 40. The frequency-divided clock selected and output by the clock selector 352 is directly input to the phase comparator 354 via the 1/1 frequency divider 353-1 of the frequency divider 353. The output of the phase comparator 354 is given to a VCO (voltage control oscillator) 355, and the VCO 355 outputs a clock signal having a clock frequency corresponding to the input signal. The output clock signal of the VCO 355 is frequency-divided to 1 / N by the 1 / N frequency divider 353-2 of the frequency divider 353. The phase of the clock divided by the frequency divider 353-2 and the phase of the divided clock selected by the clock selector 352 (the output clock of the frequency divider 353-1) are compared by the phase comparator 354. A signal corresponding to the phase difference is output from the phase comparator 354.

  In the data control unit 37, the memory read controller 371 outputs a timing signal 371-1 for read control of the FIFO memories 34A and 34B to the data selection controller 372. The data selection controller 372 sends the data to the selector 31 based on the timing signal 371-1 indicating the data switching timing from the memory read controller 371 and the signal (clock selection information) 35-1 from the clock selector 352. Data selection information 372-1 is output.

  Here, as the frequency division ratio N of the above-described frequency dividers 351A, 351B, and 353-2, it is preferable to set an integer in the range of 4 to 8, for example. That is, by setting the frequency division ratio N in this way, the operations of the phase comparator 354 and the VCO 355 are stabilized as much as possible, and the memories 34A and 34B, the memory read controller 371, the distributor The frequency accuracy of the synchronous clock 30-5 supplied to 32 can be improved. That is, the period of the synchronous clock 30-5 can be optimized, and the delay of the data selection information 372-1 output from the data selection controller 372 can be minimized.

  2 will be described with reference to signal waveforms in FIGS. 4A to 4M. The No. 1 TS clock signal 30-1 separated by the separation device 23 is obtained as a rectangular wave clock signal as shown in FIG. In this figure, the clock signal 30-1 is a rectangular wave with a duty ratio of 50%, but the duty ratio need not be 50%. This No. 1 TS clock signal 30-1 is input to a frequency divider 351A, where the frequency is divided by 1 / N. In the example of this figure, the clock signal 30-1 is divided by 8, resulting in a No. 1 TS frequency-divided clock signal 351-1 having a duty ratio of 12.5% (FIG. 4B). The frequency-divided clock signal 351-1 and the later-described No. 2 TS clock signal 30-3 have a signal LOW level period and a HIGH level period that differ greatly, that is, the duty ratio is, for example, 12 .5% is set. In this way, it is desirable that the duty ratio is closer to 100% or closer to 0% than 50%.

  Similarly, the No. 2 TS clock signal 30-3 is separated as a rectangular wave clock signal having a duty ratio of 50% in the example of this figure, and its frequency is reduced by a No. 2 TS clock divider 351B. By dividing the frequency by 8, a No. 2 TS frequency-divided clock signal 351-3 (FIG. 4F) is obtained.

  Further, the No. 1 TS clock frequency divider 351A and the No. 2 TS clock frequency divider 351B output reset signals respectively synchronized with the divided clock. That is, the No. 2 TS clock divider reset signal 351-2 (FIG. 4C) output from the No. 1 TS clock divider 351 A is input to the reset signal input terminal of the No. 2 TS clock divider 351 B. The No. 1 TS clock divider reset signal 351-4 (FIG. 4F) output from the No. 2 TS clock divider 351B is input to the reset signal input terminal of the No. 1 TS clock divider 351A. Is done. The reset signals 351-2 and 351-4 are signals having the same waveform that are output earlier than the corresponding divided clocks 351-1 and 351-3 by a half phase of the TS clock signal. Therefore, the difference between the frequency division start timings of the two frequency dividers 351A and 351B is set within a predetermined period corresponding to the half phase. For this reason, the period in which the levels of the longer period of the No. 1 TS clock and the No. 2 TS clock overlap each other can be made equal to or longer than a predetermined period, and the overlapping period can be switched to a switchable period (section) T (see FIG. 4 (A)).

  By configuring as described above, even if the period of the TS clock is short, the switchable period can be made longer according to the size of the frequency division ratio N, and therefore the influence of jitter of the TS clock. Thus, data can be switched without causing a discontinuous section of TS data.

  Hereinafter, the state of the data switching will be described. In the embodiment of the present invention, the switching signal 30-7 is input to the clock selector 352 at a timing corresponding only to the operation of the switching control device 40 without being synchronized with the TS clock or TS data. Therefore, in the clock selector 352, a switching signal (FIG. 4 (H)) in which the switching timing of the input switching signal 30-7 (FIG. 4 (G)) is delayed around the middle point of the switchable period after that timing. ) Is generated. Then, at the timing of the delayed switching signal, switching selection output from one to the other of the No. 1 TS divided clock signal 351-1 and the No. 2 TS divided clock signal 351-3 input to the clock selector 352. Perform the action. By doing so, it is possible to eliminate the possibility that the TS clock disappears before and after the switching selection operation, causing a problem such that discontinuity occurs in the TS data.

  Note that if the TS divided clock is switched at a timing near the intermediate point of the switchable period (T), the ratio of the phase difference between the divided clocks with respect to the TS divided clock period is determined between the divided clocks with respect to the TS clock period. Of the output signal 352-1 of the clock selector 352 and the signal 353-2 obtained by dividing the VCO 355 by 1 / N (divided by 8 in this figure). Since the phase error at the time of switching is similarly reduced, the phase fluctuation of the output of the VCO 355 can be made slower.

  As described above, according to the present invention, in the switching device 300, the TS clocks 30-1 and 30-3 output from the receiver No. 1 20A and No. 2 20B are not switched and output as they are. Within 300, continuous clocks 351-1 and 351-3 having the same frequency synchronized with the input TS clock are generated and output as TS clocks. Further, the TS data 30-2 and 30-4 output from the first receiver 20A and the second receiver 20B are not switched and output as they are, but the input TS data is stored in the memory 34A, in the switching device 300. The data read into the memory 34B and read from the memories 34A and 34B are switched and output as TS data.

  As a result, even when switching between the first receiver 20A and the second receiver 20B during operation, the TS clock and TS data are not interrupted. A data receiving apparatus can be realized.

  In the above embodiment, the same received signal is distributed to two systems, and the received signals of the two systems are demodulated to obtain a plurality of data streams of two systems, of the plurality of data streams of the two systems. A plurality of data streams of one system are selected and output. However, in the present invention, the same received signal is distributed to three or more systems, the received signals of three or more systems are demodulated to obtain a plurality of data streams of three or more systems, and the plurality of three or more systems of a plurality of data streams are obtained. A plurality of data streams of one system among the data streams may be selected and output.

The block diagram which shows the whole structure of the Example of the digital data receiver of this invention. FIG. 2 is a block diagram showing a configuration example of a system switching device of the digital data receiving device in FIG. The timing chart which shows a signal waveform for demonstrating operation | movement of the digital data receiver of this invention. The timing chart which shows a signal waveform for demonstrating operation | movement of the system switching apparatus of FIG. The block diagram which shows an example of the conventional digital data receiver. The timing chart which shows the operation | movement inside the conventional digital data receiver.

Explanation of symbols

1,100 STL receiver 10 antenna 20, 20A, 20B receiver 21, 21A, 21B down converter 22, 22A, 22B demodulator 23, 23A, 23B separator 31 selector (selector)
32 Distributor 40 Switching control device 50, 50A, 50B Broadcaster 30-1 No. 1 TS clock 30-2 No. 1 TS data 30-3 No. 2 TS clock 30-4 No. 2 TS data 30-5 Clock after switching 30- 6 Data after switching 30-7 Switching control signal 30-8 TS clock 30-9 Output TS data,
30-10 output TS clock 30-11 output TS data 33A, 33B synchronous controller 34A, 34B memory 35 clock control unit 300 switching device 351A, 351B frequency divider 352 clock selector 353-1, 353-2 frequency divider 354 phase Comparator 355 VCO
371 Memory read controller 372 Data selection controller

Claims (2)

Digital data that distributes the same received signal to two or more systems, receives a plurality of data streams (data, clock) obtained by demodulating each system, and selects and outputs one of the data streams In a digital reception device including a switching unit, a storage unit that temporarily stores two or more data streams input to the digital data reception unit of the digital reception device with a clock of the system, and data temporarily stored in the storage unit A data read control unit that simultaneously reads a stream from each system, a selection unit that selects and outputs one of the read data streams, and a data stream that is selected by the selection unit and output from the digital data receiver A clock control unit for generating an output clock, and the clock of the digital data receiving unit. The clock controller includes a frequency divider that generates a 1 / N (N is a positive number) clock of the clock frequency fs of each system and a frequency divider that generates a 1 / N clock of the clock frequency fs of each system. A frequency-dividing synchronizer for synchronizing, a selector for selecting 1 / N clock of the clock frequency fs of each system, and a multiplier for multiplying 1 / N clock of the clock frequency fs selected by the selector by N. A digital data receiving apparatus . Digital data that distributes the same received signal to two or more systems, receives a plurality of data streams (data, clock) obtained by demodulating each system, and selects and outputs one of the data streams In the receiving method, the two or more input data streams are temporarily stored with the clocks of the systems, the temporarily stored data streams are read simultaneously for each system, and one of the read data streams is selected. And generating a clock that is output in pairs with the data stream to be selected and output. The generation of the clock generates 1 / N (N is a positive number) clock of the clock frequency fs of each system. The 1 / N clock of the generated clock frequency fs of each system is synchronized, and the 1 / N clock of the clock frequency fs of each system is synchronized. -Option, and digital data receiving method characterized by N multiplying the 1 / N clock of the selected clock frequency fs.

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