JPH11298466A - Data transmitter and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synthesize the moving picture experts group MPEG-transport stream TS packets sent from each broadcast station with a unique clock without a failure and without distributing clock/frame synchronization/super frame synchronization at a synthesizer side in a transmission station to a multiplexer side in the broadcast station. SOLUTION: An MPEG-TS (TS1) sent from a broadcast station is written in a buffer 24 by a clock of a multiplexer. A read clock is supplied from a clock generator 29 separately from the clock used by the broadcast station. A buffer control section 30 monitors a residual amount of data in the buffer at a read point of time. If it finds that the residual is close to an underflow, since it means that required data are not sent from the broadcast station, changeover switch 35 is thrown to the position of a null packet output terminal from a null packet generator 33 to insert a null packet. Thus, even when a clock of the multiplexer is slower than the clock from the clock generator in the synthesis device, no failure takes place as for a frame generated by the synthesis device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus and a data processing apparatus to which digital transmission technology is applied, and more particularly to a plurality of MPEG (Moving Picture).
e ExpertsGroup) When a transport stream (MPEG-TS) is identified by an allocation position in a frame and a modulation scheme is independently allocated and transmitted, each MPE is used by using a null packet.
The present invention relates to a data transmission device and a data processing device capable of synchronizing and synthesizing even when a G-TS is operated with an independent clock.

[0002]

2. Description of the Related Art First, a multiplexing / transmission system of digital satellite broadcasting will be described as an example using digital transmission related to the present invention. In digital satellite broadcasting, multiple MPEG
-TS can be multiplexed and transmitted on one carrier by applying a unique modulation method. At this time, the MPEG-TSs do not interfere with each other. Also one MPEG-TS
Can apply a plurality of modulation schemes to each packet. FIG. 1 shows a transmission system.

FIG. 1 is a signal generation system diagram of digital satellite broadcasting. A program composed of video, audio, and the like produced in each of the broadcasting stations 1 and 2 is encoded by an MPEG encoder 3 that encodes each video, audio, and data, and is controlled by an MPEG multiplexing device 4 under the control of a transmission control unit 5. One M
It becomes a PEG-TS and is transmitted to the sending station 7 via the terminal station 6 and is input to the MPEG-TS combining device 9 via the terminal station 8 in the sending station 7. The MPEG-TS synthesizer 9 is 1
A plurality of MPEG-TSs sharing one carrier are assigned to a frame in packet units, and a plurality of MPEG-TSs are output as a combined signal. This signal is encoded by the transmission path encoding unit 10 in a different modulation scheme according to the assigned position, modulated by the modulation / transmitter 11, and emitted from the antenna 12 to the satellite as radio waves.

FIG. 2 shows the assignment to frames obtained by the MPEG-TS synthesizer 9, and FIG.
3 shows a configuration of a superframe obtained by the S combining device 9. Forty-eight packets per frame are grouped into a frame, and the modulation scheme and the TS identifier are determined based on the frame allocation position. Also, a superframe is composed of eight frames, and frame configuration information (TMCC) is transmitted in this unit. A different frame configuration can be used in this superframe unit. Each MPE
The G-TS determines an allocation position in a frame according to a method of modulating the G-TS.

As described above, a plurality of MPEs are
In the transmission method for distributing and allocating G-TS, all M
The PEG-TS must operate synchronously based on a single clock source. Further, the number of packets allocated to the frame and the superframe, and the phase of each generated MPEG-TS and the stream after combining must also match. For this reason, the conventional MPEG-TS
The clock used in the synthesizer is used as a main clock, and this clock is distributed to each MPEG multiplexer in each broadcasting station together with the frame / superframe synchronization timing generated here. In each broadcasting station, MPE
G-TS packets have been generated. If such a method is not adopted, a failure due to a slip occurs periodically according to the clock accuracy.

[0006]

In the conventional system in which a clock is distributed from a transmitting station to a broadcasting station to perform synthesizing in a completely synchronized state, an MPEG-TS synthesizing apparatus and an MPEG multiplexing apparatus are located at separate places. In this case, the clock / frame synchronization / superframe synchronization is performed using each dedicated line for each M.
It had to be distributed to a PEG multiplexing device. For this reason, the line cost increases and each signal generation is always performed by MPE.
Since the processing must be performed under the control of the G-TS synthesizing apparatus, there arise problems such as a need to increase the reliability of a clock generated by the MPEG-TS synthesizing apparatus.

[0007] Further, when operating with a unique clock,
On the broadcast station side, a large number of null packets are inserted in advance between the respective MPEG-TSs, and on the sending station side, the MPE taking the timing by this deletion or further insertion.
A G-TS synchronization device has also been proposed, but it has been difficult to apply frame / superframe timing with this device. For this reason, when changing the frame configuration, a signal failure occurs.

[0008] Therefore, the present invention provides a method for controlling the MP in each multiplexer.
An operation of generating an EG-TS, generating a frame / superframe timing, and the like can be performed using a unique clock, and a data transmission device that does not fail even if the frame configuration is switched. It is an object to provide a data processing device.

[0009]

To achieve the above object, according to the present invention, there are provided a plurality of output devices for outputting data having a frame structure, and a device for inputting data transmitted from the plurality of output devices. A data transmission device having a synthesis device for synthesizing the data packet, wherein the output device comprises: a first clock generation means for generating a first operation clock; and a plurality of data packets based on a clock from the first clock generation means. And a frame generating means for generating a frame from the input data. The synthesizing device comprises: a second clock generating means for generating a second operation clock; synchronization information extracted from the input data; Synchronizing means for synchronizing a frame with the second operation clock during the synthesizing based on the second operation clock. To.

According to a second aspect of the present invention, in the first aspect, the output device outputs a plurality of frames generated by the frame generating means based on a first operation clock from the first clock generating means. A synchronizing unit configured to generate a super frame based on synchronization information extracted from the input data and a second operation clock from the second clock generating unit; A super frame is synchronized with the second operation clock.

According to a third aspect of the present invention, in the first or second aspect, the synchronizing means includes: a buffer for storing data transmitted from the output device; Means for inserting or deleting a null packet from the data until the synchronization is achieved.

Further, the invention according to claim 4 is characterized in that, in any one of claims 1 to 3, the data is an MPEG transport stream.

Further, the invention according to claim 5 is a data processing device having a synthesizing device for inputting and synthesizing a plurality of transmitted data, wherein the synthesizing device includes a clock generating means for generating an operation clock; Based on the synchronization information and the operation clock extracted from the input data,
Synchronizing means for synchronizing a frame with the operation clock at the time of the synthesizing.

According to a sixth aspect of the present invention, in the fifth aspect, the synchronizing means includes a plurality of frames for the synthesizing based on synchronization information extracted from the input data and an operation clock from the clock generating means. Is synchronized with the operation clock.

According to a seventh aspect of the present invention, in the fifth or sixth aspect, the synchronizing means includes a buffer for storing the transmitted data and the synchronization before extracting the data from the buffer and synthesizing the data. Means for inserting or deleting a null packet with respect to the data until the data conversion is achieved.

The invention of claim 8 is characterized in that, in any one of claims 5 to 7, the data is an MPEG transport stream.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital satellite broadcast signal generation system to which the present invention is applied is the same as that shown in FIG. 1, and the present invention relates to an MPEG multiplexing apparatus in a broadcasting station and an MPEG-TS synthesizing apparatus in a transmitting station. It has features. FIG. 7 shows a configuration of an MPEG multiplexer in a broadcasting station.

As shown in FIG. 7, the MPEG multiplexing apparatus 4A controlled by the transmission control section 5A includes a TS converting section 13A.
In, one MPEG-TS is generated based on signals from each signal (video, audio, data) from an encoder,
Output. The TS conversion unit 13 is a standard MPEG-TS multiplexer, and simply converts video and audio into TS packets. Numeral 14 denotes a null packet generator, which outputs a null packet. A switch 15 receives an output from the TS conversion unit 13 and an output from the null packet generation unit 14, and switches (selects) one of them. That is,
With this switch 15, a null packet can be inserted according to the clock precision. The output from the switch 15 is input to the PCR replacement unit 16 and the PCR (Pro
A change of the "gramClock Reference" is performed and the result is output. Thereby, the disturbance of the PCR due to the insertion of the null packet is corrected. 17 is TMCC
(Transmission and Multipl
exing Configuration Controller
ol) an information generation unit, which is information T of each packet.
Generate and output MCC information. Reference numeral 18 denotes a switch, which receives an output from the PCR replacement unit 16 and an output from the TMCC information generation unit 17 and switches (selects) one of them. Thereby, TMCC information is inserted between TS packets. Null packet and TM
The CC information is inserted at a predetermined timing under the control of the switches 15 and 18 by the transmission control unit 5A.

The MPEG multiplexing apparatus 4 having the above configuration
The control operation of the A transmission control unit 5A will be described with reference to FIG. Note that the transmission control unit 5 has a CPU and a memory in which a control procedure executed by the CPU as shown in FIG. 8 is stored. The memory also has a work area for the CPU.

When the control of the multiplexer is started, it is determined in step 1 (S1) whether or not the normal operation is performed. The normal operation means a period during which normal clock synchronization is performed, and the case where the operation is not the normal operation means an operation mode for switching the frame configuration. It can be input to the control unit 5A. In S1, if the operation is the normal operation, the process proceeds to S2, where a null packet is inserted into the X packet once for each modulation scheme according to the clock accuracy and the transmission rate (TS conversion unit 13, null packet generation unit 14, Switch 15
by). If the operation is not the regular operation, the process proceeds to S3, where it is determined whether or not the time exceeds Y seconds before the frame switching. If not, return to S1. If it exceeds, S
Then, W null packets are inserted every Z seconds (by the TS conversion unit 13, the null packet generation unit 14, and the switch 15). Next, in S5, it is determined whether or not the frame switching time has come. If the switching time has not been reached,
It returns to S4. If the switching time has come, the process proceeds to S6, where the frame is switched (the switching information can be added to the TMCC, for example), that is, the process returns to S1 to process the next frame.

FIG. 9 shows a configuration of an MPEG-TS synthesizing device in the transmitting station.

As shown in FIG. 9, according to the BS digital broadcasting standard, a maximum of four types of modulation schemes and eight types of MPEG-TS can be combined and transmitted per carrier wave.
The PEG-TS synthesizing apparatus has a processing unit (in FIG. 9, indicated by 20, 21, 22) for each MPEG-TS,
Each processing unit has a buffer for each modulation method. MPEG sent from each multiplexing device of each broadcasting station
-TS is input to each corresponding processing unit. Each processing unit
Since each MPEG-TS has the same configuration and performs the same processing, here, the processing unit 20 that processes the first MPEG-TS transmitted from the broadcasting station 1 will be mainly described. In addition, since the same processing is performed for each buffer in the processing unit 20, the M of the first modulation scheme is used here.
The buffer 24 for inputting and processing the PEG-TS and the peripheral processing means will be mainly described. The operation of the other buffers is the same, and a detailed description is omitted.

The first MPEG-T transmitted from the broadcasting station
S (TS1) is written into the corresponding buffer (any of 24-27) for each modulation scheme with the clock of the multiplexer. The clock of the multiplexer is the first MPE
Extracted from the G-TS by the clock extractor 28,
It is supplied to each of the buffers 24-27. Further, the TMCC information extraction unit 23 extracts TMCC information from the first MPEG-TS, and inputs the TMCC information to the buffer control unit 30. The buffer control unit 30 includes a CPU and a CPU
And a memory storing a control procedure such as 0. The memory also has a work area for the CPU.

Each buffer has a storage capacity of one superframe or more. Next, the necessary amount is read from each of the buffers 24-27 according to the frame configuration intended by the synthesizing device. The read clock is different from the clock used in each of the broadcasting stations, Clock generator 29. At this time, the buffer controller 30 includes the TMC from the TMCC information extractor 23.
C information, the superframe synchronization detected from the first MPEG-TS by the superframe synchronization detector 31, and the timing generated by the superframe / frame timing generator 32 based on the clock from the clock generator 29. , And the remaining amount of data in the buffer 24, and the buffer control unit 30 controls the changeover switch 35 based on these inputs as follows.
The changeover switch 35 includes a read data output terminal 35b from the buffer, a null packet output terminal 35a from the null packet generator 33, and a null deletion output terminal 35c that skips an output packet for the null packet deletion process from the buffer 24. Is selected according to the control signal from the buffer control unit 30 and output.

The output of the changeover switch from each processing unit is input to the multiplexer 34, and the respective outputs are combined.
PCR replacement is performed, and a TMCC newly added to indicate information of all TSs is generated and multiplexed and output.

FIG. 10 shows a null control flow mainly by the buffer control unit 30 of the synthesizing apparatus. The operation will be described with reference to FIGS. 4, 5 and 6.

When the control of the synthesizing apparatus is started, it is determined in S11 whether or not the apparatus is in a regular operation. The judgment is, for example, TM
This is performed based on the TMCC information from the CC information extraction unit 23. In S11, if the operation is the normal operation, the process proceeds to S12, where the buffer state is determined. That is, the buffer control unit monitors the remaining amount of data in the buffer at the time of buffer reading, and if it is close to an underflow, it means that necessary data has not arrived from the broadcasting station. Proceed to S13 for insertion, and then switch the changeover switch to the null packet output terminal 35a from the null packet generator, and return to S12.
This is the case where the clock of the multiplexer is slower than the clock of the clock generator in the synthesizer as shown in FIG. 4A, and the frame generated in the synthesizer by inserting null packets. Can be prevented from failing. In S12, if the remaining amount of data in the buffer is a predetermined amount, since necessary data has arrived from the broadcasting station, the process proceeds to S14, where the changeover switch 35 is switched to a data output terminal 35b for reading data from the buffer.
A predetermined packet in the buffer is read and taken out from the changeover switch. If the remaining amount of data in the buffer is close to overflow in S12, it means that more data than necessary has arrived from the broadcasting station, and the process proceeds to S15, where it is determined whether the next data to be read is a null packet. If the packet is determined to be a null packet, the clock of the multiplexer is faster than the clock of the clock generator in the synthesizer, as shown in FIG.
The changeover switch is switched to the null deletion output terminal 35c for processing corresponding to the null packet deletion from the buffer 24, and the null packet is deleted so that the frame generated in the synthesizing device does not break down. be able to. If the data to be read next is not a null packet in S15, the process returns to S11.

With the above operation, each MPEG-TS and the clock phase in the synthesizing apparatus can be matched.

If it is determined in step S11 that the operation is not the regular operation, step S17 is executed.
Then, it is determined whether or not the superframe synchronization phase has shifted from the regulation. This determination is made by the buffer control unit 3
0, based on the superframe synchronization detected by the superframe synchronization detector 31 and the timing generated by the superframe / frame timing generator 32.

If the superframe synchronization phase deviates from the regulation, control is performed to match the frame / superframe phase. The multiplexing device in the broadcasting station uses its MPE
G-TS independently sets frame / superframe timing according to the number allocated in the frame,
On the other hand, the synthesizing device in the transmitting station previously synchronizes the clock based on the clock from the clock generator in the synthesizing device, and from the buffer at the timing of the frame / superframe based on this. Is read. If such an operation is performed for each modulation scheme, it is only necessary that the operation be permanently continued unless the frame configuration is changed. However, due to the operation of the null packet, the frame synchronization phase / superframe synchronization phase assumed by the multiplexer becomes a completely different position from the phase assumed by the synthesizer.

Therefore, when the frame configuration is changed at the end of a certain superframe, if the unit of the superframe assumed by the multiplexing apparatus and the unit of the superframe assumed by the combining apparatus do not match, the adjacent superframe may be changed. Data is spilled between frames. As a result, the spilled packet may be transmitted in an unexpected modulation scheme, causing data corruption.

FIGS. 5A and 5B show the manner in which the synchronizing phase of the superframe is shifted in the synthesizing apparatus.
Indicates a state in which superframe synchronization is established, and a different system is transmitted across the superframe switching point. (B) shows a case where the synchronization in the synthesizer is recognized earlier than the synchronization in the multiplexer. In this case, the clock in the synthesizer is slower than the clock in the multiplexer. As a result of the insertion of the null packet, the recognition position of the superframe is earlier. If superframe switching is performed in this state, for example, QP
A packet to be transmitted by SK is transmitted by 8PSK. (C) shows a case where the synchronization in the synthesizer is recognized at a later position than the synchronization in the multiplexer,
In this case, since the clock of the synthesizing device is faster than the clock of the multiplexing device, the recognition position of the superframe is delayed as a result of the null packet deletion. This shows a case where the superframe phase is shifted due to null packet deletion.

In order to prevent such a data frame failure from occurring due to such a shift in the superframe synchronization phase, for example, a null packet corresponding to a superframe phase error is inserted at the switching of the superframe on the multiplexer side. By doing so, data leakage does not occur in adjacent superframes having different frame configurations. Usually, the multiplexing device cannot recognize the phase difference between the superframe phase generated by the multiplexing device and the superframe phase generated by the synthesizing device. Insertion may be performed, and the combining apparatus may delete null packets that have been additionally inserted for this switching until the superframe phase matches. But with this method,
Null packets for one superframe are MPEG-TS
Since the buffer enters the decoder, the buffer of the MPEG-TS decoder underflows and breaks down. For this reason, the multiplexer limits the number of consecutive null packets to an allowable range according to the buffer size of the MPEG-TS decoder, and switches the superframe before switching the superframe.
Transmission of a null packet is started sufficiently long ago. Thus, the synthesizer can gradually adjust the superframe timing recognized by the multiplexer and the superframe timing recognized by the synthesizer (for example, from (a) to (b) in FIG. 6). ), From (b) to (c)). That is, if the superframe synchronization phase is shifted from the regulation in S17, the process proceeds to S18, and the changeover switch is switched to the null deletion output terminal 35c for the null packet deletion processing from the buffer 24, and the null packet is deleted. Further, after updating the value of the deletion number register N by one, the process returns to S17, and the above operation is repeated until the superframe timing recognized by the multiplexer and the superframe recognized by the synthesizer match. . If the timing matches in S17, the process proceeds to S19.

In S19, the process waits until the timing of switching the superframe is reached, and when the timing is reached, the control of switching the superframe is performed in S20, and the process proceeds to S20. In S20, the changeover switch is switched to the null packet output terminal 35a from the null packet generator, and a number of null packets corresponding to the value of the deletion number register N are inserted again after the superframe is switched.
Return to 1. That is, in S18, a change in speed occurs if the null packet is left deleted, so that the null packet that has just been deleted is inserted again after the superframe is switched. Even if both the synthesizing devices use asynchronous clocks, all can be handled in synchronization, and switching of the frame configuration does not fail. Actually, null packet addition is started a specified time before switching according to the clock accuracy and the bit rate, and the adjustment is completed to the point where the superframe phase matches the specified switching time. If the superframe phase is not always managed, the broadcasting station needs to notify the transmitting station of the occurrence of the switching event before switching.

[0035]

As described above, according to the present invention,
Each data packet can be synthesized with a unique clock without distributing the clock / frame synchronization / superframe synchronization of the synthesis device to the output device.

[Brief description of the drawings]

FIG. 1 is a signal generation system diagram of digital satellite broadcasting related to the present invention.

FIG. 2 is a diagram illustrating a frame configuration of a digital satellite broadcast signal.

FIG. 3 is a diagram showing a superframe configuration of the same signal.

FIG. 4 is a diagram illustrating a clock synchronization method.

FIG. 5 is a diagram illustrating a state of failure when frame timing is shifted.

FIG. 6 is a diagram showing a state of timing adjustment at a switching timing.

FIG. 7 is a configuration diagram of a multiplexing device according to the present invention.

FIG. 8 is a flowchart showing the operation of the multiplexer.

FIG. 9 is a configuration diagram of a synthesis device according to the present invention.

FIG. 10 is a flowchart showing the operation of the synthesizing device.

[Explanation of symbols]

 20, 21, 22 processing unit 23 TMCC information extraction unit 24, 25, 26, 27 buffer 28 clock extractor 30 buffer control unit 31 superframe synchronization detection unit 32 superframe / frame timing generation unit 33 null packet generator 34 multiplexer 35 Selector switch

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor: Akira Hashimoto 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute

Claims (8)

[Claims] 1. A data transmission device comprising: a plurality of output devices for outputting data having a frame structure; and a combining device for inputting and combining data transmitted from the plurality of output devices, wherein the output device is A first clock generating means for generating a first operation clock; and a frame generating means for generating a frame from a plurality of data packets based on a clock from the first clock generating means. A second clock generating means for generating a second operating clock; and synchronizing information extracted from the input data and a second operating clock from the second clock generating means, for synthesizing a frame during the second synthesis. A data transmission device comprising: synchronization means for synchronizing with an operation clock. 2. The device according to claim 1, wherein the output device is configured to output a first clock from the first clock generation unit.
Further comprising a superframe generating means for generating a superframe from the plurality of frames generated by the frame generating means, based on the operation clock of the above, wherein the synchronizing means comprises: synchronization information extracted from the input data; A data transmission device, wherein a super frame is synchronized with the second operation clock at the time of the synthesizing based on a second operation clock from two clock generation means. 3. The synchronizing means according to claim 1, wherein the synchronizing means achieves the synchronization before taking out data from the buffer and storing the data transmitted from the output device and synthesizing the data. Means for inserting or deleting a null packet from the data until the data transmission. 4. The data transmission apparatus according to claim 1, wherein the data is an MPEG transport stream. 5. A data processing device having a synthesizing device for inputting and synthesizing a plurality of transmitted data, wherein said synthesizing device includes a clock generating means for generating an operation clock, and a clock extracted from the input data. A data processing apparatus comprising: a synchronizing unit that synchronizes a frame with the operation clock at the time of the synthesis based on synchronization information and the operation clock. 6. The synchronizing unit according to claim 5, wherein the synchronizing unit generates a superframe including a plurality of frames upon the synthesizing, based on synchronization information extracted from the input data and an operation clock from the clock generating unit. A data processing device synchronized with an operation clock. 7. The synchronizing means according to claim 5, wherein the synchronizing means comprises: a buffer for storing the transmitted data; and, until the synchronization is achieved before the data is taken out from the buffer and combined. Means for inserting or deleting a null packet with respect to the data. 8. The data processing apparatus according to claim 5, wherein the data is an MPEG transport stream.