JPWO2003065455A1 - Semiconductor integrated circuit - Google Patents

Abstract

A function selection circuit with a controller that can change the rising / falling characteristics of the signal waveform output from the output buffer and the logical threshold value in the input buffer according to the logic level of the common node signal given by the option. Reduce the scale of. In addition, by configuring the coupling circuit including the depletion type first transistor, the voltage level of the signal input to the second circuit is lowered, and the transistor included in the second circuit does not flow to the transistor exhibiting the GIDL characteristic. Reduce the desired current. Further, the output buffer and the output driver are coupled to each other through the signal wiring formed using the upper layer of the portion where the memory cell array is formed, thereby achieving optimization of the layout of the output circuit.

Description

Technical field
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including an input buffer and an output buffer.
Background art
In the semiconductor integrated circuit, a function selection method as described below is adopted.
That is, a first method for determining a function by changing a signal level supplied to a predetermined terminal of the semiconductor integrated circuit on a substrate on which the semiconductor integrated circuit is mounted according to setting information such as a mode register, a test process after assembly The second method for determining the function using an electrical fuse, the third method for determining the function by a bonding option at the time of assembly, the fourth method for determining the function using a fuse or the like in the wafer state, and the wiring mask for the wafer This is the fifth method for determining the function by changing the function. Here, the functions determined by the selection of the optional function include the input threshold value in the input buffer, the rising / falling (tr / tf) characteristics of the output waveform in the output buffer, the operating power supply voltage, the package, the capacity, and the bit width. , And functions (truth table, state transition diagram). In addition, in this specification, when “option” is used alone, in addition to the bonding option, various functions such as function selection by laser fuse, function selection by electric fuse, function selection by antifuse, function selection by nonvolatile memory element, etc. Means selection.
The first technique is an easy and simple technique when a system product is sold using a semiconductor device (board product or the like). However, in the case of a business with a single semiconductor integrated circuit that requires standardization, it is often not accepted by customers because it requires special management in use. The second method needs to employ a wafer process that can make a nonvolatile memory such as an electric fuse in a semiconductor component. In addition, this nonvolatile memory needs to be programmable in a short time and highly reliable. The third method is effective as a relatively easy and simple method. In the fourth method, inventory management at the wafer process factory is currently managed in the wafer state after the completion of the test, and therefore, it is necessary to have a wafer inventory for each function determined by the fuse state. It becomes difficult to follow changes in the market. The fifth method is widely adopted because it can be changed in specifications with a high degree of functionality and a high degree of freedom. However, the function determination by option is optional compared to the first method and the fourth method. This process is earlier in the production process, and the need to have a wafer inventory similar to the fourth method is generated.
According to the inventor's investigation, function selection by option is effective in order to respond quickly to specification changes in a semiconductor integrated circuit. However, as the number of options increases, the function selection circuit is required for each option. Therefore, for example, when a bonding option is adopted, it has been found that the number of pads for bonding increases as the number of options increases, thereby inhibiting the reduction of the chip size of the semiconductor integrated circuit. The same is true when options other than bonding, such as a fuse circuit, are employed.
Further, the inventors of the present invention have studied an interface circuit that allows signals to be exchanged with the outside in a semiconductor integrated circuit. When two types of voltages having different voltage levels are used as power supply voltages for circuit operation, Is a transistor having a GID (Gate Induced Drain Leakage) characteristic in which a drain current increases when a potential having a polarity opposite to a channel turning-on potential is applied between a gate and a source due to miniaturization of a semiconductor integrated circuit It has been found that an undesired current flowing in such a transistor hinders the reduction of the current consumption of the circuit.
Furthermore, when the inventor of the present application has studied an interface circuit in a semiconductor memory device which is an example of a semiconductor integrated circuit, it has been found that there is room for improvement in the layout of an output circuit included in the interface circuit. The output circuit has a function of outputting data read from the memory cell array in the semiconductor memory device to the outside, but a relatively large number of control signals are used to control the operation thereof. Such a control signal is generated in relation to other timing signals in a control circuit that generates various timing signals for the internal operation of the semiconductor memory device. In order to generate various timing signals for the internal operation of the semiconductor memory device, this control circuit is preferably arranged closer to the center of the semiconductor chip than to be arranged at the edge of the semiconductor chip. For this reason, the control circuit is usually formed at a position away from the signal output pad for externally outputting read data from the memory cell array. In this case, if the output circuit is arranged in the vicinity of the external output terminal, the signal line for controlling the operation must be wired up to the vicinity of the external terminal, so that the wiring becomes complicated. On the other hand, if the output circuit is arranged in the vicinity of the control circuit, the signal wiring for transmitting the output signal from the output circuit to the signal output pad is routed inside the semiconductor chip. Since a relatively large current flows in the signal wiring for transmitting the output signal from the output circuit to the signal output pad, routing such signal wiring to the inside of the semiconductor chip is another internal circuit. This is not preferable because it causes noise generation.
An object of the present invention is to provide a technique for reducing the scale of a function selection circuit.
Another object of the present invention is to provide a technique for reducing an undesired current flowing in a transistor exhibiting GIDL characteristics.
Another object of the present invention is to provide a technique for optimizing the layout of an output circuit for externally outputting data read from a memory cell array.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Disclosure of the invention
The outline of typical ones of the inventions disclosed in this specification will be described as follows.
Depending on the input buffer for capturing the signal, the output buffer for outputting the signal, the rising and falling characteristics of the signal waveform output from the output buffer, and the logic level of the common node signal given by the option And a controller capable of changing the logic threshold value in the input buffer to constitute a semiconductor integrated circuit. When the logic level of the common node signal given by the option is determined, the controller accordingly determines the rising / falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer. change. For this reason, it is not necessary to form a function selection circuit for each function to be selected. This reduces the scale of the function selection circuit.
Also, a step-down circuit for stepping down the input power supply voltage to a predetermined level, a first logic circuit that operates when the power supply voltage is supplied, and a stage subsequent to the first logic circuit, are provided from the step-down circuit. When the semiconductor integrated circuit is configured to include a second logic circuit that operates when the output voltage is supplied and a coupling circuit for coupling the first logic circuit and the second logic circuit, The coupling circuit includes the depletion type first transistor. The depletion-type first transistor lowers the voltage level of the signal input to the second circuit, and in the transistor included in the second circuit, a potential having a polarity opposite to the potential for turning on the channel is between the gate and the source. It acts to avoid being applied. This reduces the undesired current flowing through the transistor exhibiting GIDL characteristics.
Furthermore, when a semiconductor integrated circuit is configured including a memory cell array in which a plurality of memory cells are arranged in an array and an output circuit for outputting data read from the memory cell array to the outside, An output buffer for outputting, and an output driver arranged to face the output buffer via the memory cell array and for driving the output buffer based on data read from the memory cell array, An output circuit is configured. At this time, the output buffer and the output driver are coupled to each other through a signal wiring formed using an upper layer of the portion where the memory cell array is formed. This avoids complication of signal wiring and suppresses noise generation in other circuits, thereby achieving optimization of the output circuit layout.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a semiconductor memory device 10 which is an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor memory device 10 of the present embodiment is not particularly limited, but is formed as a semiconductor integrated circuit on a single semiconductor substrate 9 such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
The semiconductor memory device 10 shown in FIG. 1 has four memory cell arrays 28, 29, 30, and 31 although not particularly limited. Memory cell arrays 28, 29, 30, and 31 are arranged such that a plurality of word lines and a plurality of data line pairs intersect, and a plurality of static memory cells are provided in an array at the intersections. Become. The plurality of word lines are driven to a selection level based on an output signal of a row address decoder (not shown) for decoding a row address. When one word line is driven to a selected level, all the memory cells coupled to the word line are selected, and data is written to or read from the memory cell via the data line pair. Reading is possible. Data line selection circuits 32, 33, 34 and 35 for selectively coupling a plurality of data line pairs in the corresponding memory cell array to common line pairs are coupled to the memory cell arrays 28, 29, 30, and 31. . The data line selection operation in the data line selection circuits 32, 33, 34, and 35 is performed based on the output signal of the column address decoder that decodes the column address signal. In the vicinity of the data line selection circuits 32, 33, 34, 35, sense amplifiers 36, 37, 38, 39 for amplifying the signal level of the corresponding common line pair are arranged. The common line pair is coupled to the output driver 42 so that signals amplified by the sense amplifiers 36, 37, 38, 39 are transmitted to the output driver 42 through the common line. A pad 17 for outputting read data from the memory cell arrays 28, 29, 30, 31 to the outside is provided on the edge of the semiconductor chip 9. The pad 17 is coupled to an external terminal (not shown) by a bonding wire. An output signal from the output buffer 43 is transmitted to the pad 17. An electrostatic breakdown protection element 27 is disposed between the output buffer 43 and the pad 17 in order to prevent the constituent elements of the output buffer 43 from being destroyed by static electricity input via an external terminal. The output buffer 43 is driven by the output driver 42. That is, the output buffer 43 is driven by the output driver 42 based on the read data from the memory cell arrays 28, 29, 30, and 31. Thereby, external output of read data from the memory cell arrays 28, 29, 30, and 31 is enabled. The output driver 42 and the output buffer 43 driven by the output driver 42 are arranged to face each other via the memory cell array 31, and an output signal from the output driver 42 is a metal wiring 52 formed in an upper layer of the formation region of the memory cell array 31. To the output buffer 43. In order to prevent the constituent elements of the output driver 42 from being destroyed by static electricity, the electrostatic breakdown protection element 26 is disposed at the subsequent stage of the output driver 26. Note that a predetermined wiring resistance exists in the metal wiring 52 formed in the upper layer of the formation region of the memory cell array 31, and this wiring resistance also prevents the constituent elements of the output driver 42 from being destroyed by static electricity. It is useful for.
In addition, a pad 16 for capturing input data for writing is formed on the edge of the semiconductor chip 9. The pad 16 is bonded to an input terminal (not shown) for signal capture. An input buffer 40 is coupled to the pad 16 via a metal wiring 53 formed in an upper layer of the memory cell array 30, and externally input write data is input via the metal wiring 53 to the input buffer 40. To be communicated to. In order to prevent the constituent elements of the input buffer 40 from being destroyed by static electricity, the electrostatic breakdown protection element 23 is disposed in the vicinity of the pad 16, and the electrostatic breakdown protection element 24 is disposed in the vicinity of the input buffer 40. The An output signal from the input buffer 40 is transmitted to a write circuit (not shown) for writing data to the memory cell arrays 30 and 31.
Further, a pad 15 for capturing input data for writing is formed on the edge of the semiconductor chip 9. The pad 15 is bonded to an input terminal (not shown) for signal capture. The pad 15 is coupled to the input buffer 41 via a metal wiring 54 formed in an upper layer of the formation region of the memory cell array 29, and write data input from the outside is input to the input buffer 41 via the metal wiring 54. To be communicated to. In order to prevent the constituent elements of the input buffer 41 from being destroyed by static electricity, the electrostatic breakdown protection element 21 is disposed in the vicinity of the pad 15, and the electrostatic breakdown protection element 22 is disposed in the vicinity of the input buffer 41. The An output signal from the input buffer 41 is transmitted to a write circuit (not shown) for writing data to the memory cell arrays 28 and 29.
The input buffers 40 and 41 and the output driver 42 are selectively activated by a chip select signal CSB output from the chip controller 46. In this example, although not particularly limited, the input buffers 40 and 41 and the output driver 42 are activated during the period when the chip controller 46 asserts the chip select signal CSB to the low level. . The chip controller 46 is part of the function of a control circuit (not shown) for controlling the overall operation of the semiconductor memory device 10.
The input buffers 40 and 41 can change the logic threshold value with respect to the input signal by the control signal CTL, and the output driver 42 can rise and fall (tr / tf) of the waveform of the output signal by the control signal CTL. The characteristic can be changed. The control signal CTL is formed by the interface controller 45.
Here, the reason why the output driver 42 and the output buffer 43 are arranged to face each other via the memory cell array 31 will be described.
The output driver 42 and the output buffer 43 are collectively referred to as an output circuit and are usually arranged adjacent to each other. When this output circuit (output driver 42 and output buffer 43) is provided at the formation position of the output buffer 43 in FIG. 1, many signal lines coupled to the output driver 42 are connected to the output buffer in FIG. It is necessary to wire up to the formation position of 43, which is not preferable because wiring in the upper layer of the formation region of the memory cell array 31 becomes complicated. When the output circuit (the output driver 42 and the output buffer 43) is provided at the position where the output driver 42 is formed in FIG. 1, a signal line for transmitting the output signal of the output buffer 43 is electrostatically connected. It is routed to the position of the destruction protection element 27. Since the output buffer 43 has a high driving capability and a relatively large current flows through a signal line for transmitting the output signal, it is preferable to route such a signal line in the semiconductor chip 9 because noise is easily generated. Absent. Therefore, in this example, as shown in FIG. 1, the output driver 42 and the output buffer 43 are arranged to face each other via the memory cell array 31. In this way, the output driver 42 is arranged in the vicinity of the interface controller 45 and the chip controller 46, and the output buffer 43 is arranged in the vicinity of the pad 17. In addition, in that case, the wiring in the upper layer of the formation part of the memory cell array 31 need only be a signal line for transmitting the output signal of the output driver 42 to the output buffer 43. It is possible to avoid complications. Further, since the driving capability of the output driver 42 is smaller than that of the output buffer 43, noise is hardly generated.
An interface controller 45 is provided. The interface controller 45 changes the logic threshold value in the input buffers 40 and 41 and changes the waveform rising / falling (tr / tf) characteristics of the output signal in the output driver 42. Then, adjustment is made according to the logic level of the common node signal given to the control line 55 by the bonding option. That is, a bonding option pad 13 is formed at one end of the semiconductor chip 9, and a bonding option pad 18 is formed at the other end of the semiconductor chip 9. The pad 13 or the pad 18 is a bonding option. When the logic level of the control line 55 is determined by being coupled to the high-potential-side power supply VCC or the ground GND (low-potential-side power supply VSS), the logic in the input buffers 40 and 41 is determined according to the logic level. The threshold value and the waveform rising / falling (tr / tf) characteristics of the output signal in the output driver 42 are determined. The pad 14 formed in the vicinity of the bonding option pad 13 is used for taking in the high potential side power supply VCC from the outside, and the pad 19 formed in the vicinity of the bonding option pad 18 is externally connected. Used to take in the low potential side power supply (ground GND).
Next, the necessity of changing the logic threshold value in the input buffers 40 and 41 and the necessity of changing the waveform rising / falling (tr / tf) characteristic of the output signal from the output buffer 43 will be described.
Examples of the interface type in the semiconductor integrated circuit include an LV-CMOS interface and an LV-TTL interface. As shown in FIG. 39, in the LV-CMOS interface, when the horizontal axis is the high potential side power supply VCC and the vertical axis is the input voltage Vin, VCC / 2 is the center of the logic threshold value. A low level is guaranteed below VCC, and a high level is guaranteed above 0.75 × VCC. A difference 131 between the VCC / 2 line and the 0.25 × VCC line is a noise margin on the low level side, and a difference 132 between the VCC / 2 line and the 0.75 × VCC line is a noise on the high level side. It is a margin. As is apparent from FIG. 39, the noise margin 131 on the low level side and the noise margin 132 on the high level side are enlarged as the level of the high potential side power supply VCC increases. Normally, when the output buffer is driven at a high speed, a large current flows through the output terminal, and the noise component included in the output signal increases. However, when a signal is supplied to a circuit that employs the LV-CMOS interface, even if the signal contains a little noise, the circuit operation is hindered if the signal is within the noise margin. Therefore, the output buffer can be driven at high speed.
On the other hand, as shown in FIG. 40, the LV-TTL interface guarantees a low level when the input voltage Vin is 0.8 V or less, regardless of the fluctuation of the high potential side power supply VCC, and the input voltage Vin is 2 Since the high level is guaranteed at 0.0 V or higher, the noise margin 141 on the low level side becomes smaller as the level of the high potential side power supply VCC becomes lower, and the noise on the high level side becomes higher as the level of the high potential side power supply VCC becomes higher. The margin 142 is reduced. Therefore, when a signal is supplied to a circuit employing such an LV-TTL interface, it is necessary to suppress noise included in the output signal by driving the output buffer at a low speed.
In a semiconductor integrated circuit including an interface such as an input buffer or an output buffer, a logical threshold value in the input buffers 40 and 41 is determined by a bonding option so as to meet an interface specification adopted in a user system to which the interface is applied. It is desirable to be able to adjust the waveform rising / falling (tr / tf) characteristics of the output signal from the output buffer 43. The logical threshold values in the input buffers 40 and 41 and the waveform rising / falling (tr / tf) characteristics of the output signal from the output buffer 43 can be individually adjusted by separate bonding options. Since the function selection circuit is required for each option, many pads must be formed on the edge of the semiconductor chip for the bonding option, which hinders reduction in the chip size of the semiconductor integrated circuit. In this example, the rising and falling characteristics of the signal waveform output from the output buffer 43 and the logic threshold value in the input buffers 40 and 41 can be adjusted according to the logic level of the common node signal in the control line 55. Is done. In other words, the logic level of the control line 55 is determined by the bonding option, whereby the rising / falling characteristics of the signal waveform output from the output buffer 43 and the logic threshold values in the input buffers 40 and 41 are determined. In this way, the function selection circuit can be shared by the bonding option, thereby reducing the scale of the function selection circuit.
Next, the bonding option will be described in detail.
FIG. 2 shows a main part of the semiconductor memory device 10 shown in FIG.
A pad 16 for data input and a pad 19 to which the high potential side power supply VCC is supplied are formed at one end of the semiconductor chip 9, and a bonding option pad 18 is formed in the vicinity of the pad 19. . At the other end of the semiconductor chip 9, a data input pad 15 and a pad 14 to which a low potential side power supply (ground GND) is supplied are formed. A pad 13 for bonding options is formed in the vicinity of the pad 14. It is formed. The pad 16 and the external terminal 57 are coupled by a bonding wire 63, the pad 19 and the external terminal 11 are coupled by a bonding wire 62, and the pad 15 and the external terminal 58 are coupled by a bonding wire 65. And the external terminal 12 are coupled by a wire 64 by bonding. If the logic of the control line 55 is to be set to a high level by a bonding option, the external terminal 11 and the pad 18 are coupled with a wire 61 by bonding. Thereby, the logic of the control line 55 can be made high. Since the bonding option pad 18 is disposed in the vicinity of the supply pad 19 of the high potential side power supply VCC, the bonding between the external terminal 11 and the pad 18 can be easily performed. If the logic of the control line 55 is to be set to a low level by the bonding option, the external terminal 12 and the pad 13 are connected by a wire 66 by bonding as shown in FIG. Thereby, the logic of the control line 55 can be set to a low level. Since the bonding option pad 13 is disposed in the vicinity of the low-potential-side power supply (ground GND) supply pad 14, the bonding between the external terminal 12 and the pad 13 can be easily performed.
The electrostatic protection elements 21 and 23 are not particularly limited, but a first protection circuit (ESD1) as shown in FIG. 4 is employed. The first protection circuit (ESD1) includes a thyristor formed by coupling an npn bipolar transistor 67 and a pnp bipolar transistor 68, a resistor 69 disposed in the subsequent stage, and a capacitor formed by an n channel MOS transistor 70. And a time constant circuit. The electrostatic breakdown protection elements 20 and 25 are not particularly limited, but a second protection circuit (ESD2) as shown in FIG. 5 is adopted. The second protection circuit (ESD2) includes a resistor 71 and a time constant circuit including a capacitor formed by an n-channel MOS transistor 72.
Further, as the electrostatic breakdown protection elements 24 and 22 arranged in the vicinity of the input terminals of the input buffers 40 and 41, an electrostatic breakdown protection circuit (ESD3) as shown in FIG. 6 is used. This electrostatic breakdown protection circuit (ESD3) is for inputting a series circuit of a p-channel MOS transistor 74 coupled to the high potential side power supply VCC and an n-channel MOS transistor 75 coupled to the ground GND, and for signal input. The resistor 73 is coupled.
A detailed configuration of the input buffers 40 and 41 will be described.
First, a basic configuration of a circuit applied to the input buffers 40 and 41 will be described.
FIG. 13 shows the basic configuration of the input buffer.
The step-down circuit 81 generates an internal power supply VDDI of a lower level based on the input high potential side power supply VCC. Although not particularly limited, when the high potential side power supply VCC is 3.3V, the internal power supply VDD is 1.2V. A first logic circuit 101 that is operated by being supplied with the high-potential-side power supply VCC, and a second logic circuit 102 that is disposed in the subsequent stage and that is operated by being supplied with the internal power supply VDDI are provided. An n-channel MOS transistor 85 is provided as a coupling circuit for coupling the first logic circuit 101 and the second logic circuit 102. The n-channel MOS transistor 85 is a depletion type, and is turned on when the internal power supply VDDI is supplied to its gate electrode. The first circuit 101 is an inverter in which a p-channel MOS transistor 83 and an n-channel MOS transistor 84 are connected in series. The second logic circuit 102 includes a p-channel MOS transistor 86 and an n-channel MOS transistor. An inverter is formed by connecting a transistor 87 in series. The p-channel MOS transistors 83 and 86 are coupled to the high potential side power supply VCC, and the n-channel MOS transistors 84 and 87 are coupled to the ground GND. A signal transmission path from the n-channel MOS transistor 85 to the input terminal of the second logic circuit 102 is a node 6.
The input signal is logically inverted by the first logic circuit 101, further logically inverted by the second logic circuit 102 at the subsequent stage, and then output via the output terminal OUT.
The step-down circuit 81 is not particularly limited, but as shown in FIG. 32, a constant voltage generation circuit 301 for generating a reference voltage Vref of a predetermined level and an internal power supply VDDI based on the reference voltage Vref are generated. And a negative feedback amplifier circuit 302. The negative feedback amplifier circuit 302 is not particularly limited, but as shown in FIG. 33, a differential coupling circuit in which n-channel MOS transistors 311 and 312 are coupled to the ground GND via a constant current source 313. And p-channel MOS transistors 314 and 315 forming a current mirror type load of the differential coupling circuit, and a p-channel MOS for outputting the internal power supply VDDI based on an output signal from the differential coupling circuit Transistor 317 and a phase compensation capacitor 316 coupled to the gate electrode and drain electrode of p channel MOS transistor 317 are included. The capacitor 316 is formed of a depletion type MOS transistor, and the other MOS transistors are of an enhancement type. The phase compensation capacitor 316 may be coupled between the drain electrode of the p-channel MOS transistor 317 and the ground GND via a resistor 318, as shown in FIG.
Here, when the phase compensation capacitor 316 is formed by the gate capacitance of a depletion type MOS transistor, the n-channel type MOS transistor 85 in FIG. 13 is formed by the same process as the capacitor 316.
Next, the reason why a depletion type MOS transistor 85 is provided between the first logic circuit 101 and the second logic circuit 102 will be described.
As shown in FIG. 14, in the case where the first logic circuit 101 and the second logic circuit 102 are directly coupled, the p-channel MOS transistor 86 is not caused by the GIDL (Gate Induced Drain Leakage) characteristic. There is a possibility that a desired current flows. For example, as shown in FIG. 15, the p-channel MOS transistor has a characteristic that the subthreshold current from the drain to the source increases as the gate-source voltage VGS increases. Show. As the gate-source voltage VGS decreases, the drain current from the drain to the source generally decreases. However, as the semiconductor integrated circuit becomes finer, the channel is turned on. There is a transistor having GIDL characteristics in which a drain current increases when a potential having a polarity opposite to the potential to be applied is applied between the gate and the source. When the p-channel MOS transistor 86 is a transistor exhibiting the above-mentioned GIDL characteristics, in the configuration shown in FIG. 14, the p-channel MOS transistor 83 is coupled to the high potential side power supply VCC, and the p-channel MOS transistor Since the node 86 is coupled to the internal power supply VDDI, the high-level potential of the node 7 becomes equal to the high-potential-side power supply VCC. Therefore, the potential for turning on the channel is between the gate and the source of the p-channel MOS transistor 86. As a result, an undesired current caused by the GIDL characteristic flows.
Therefore, in the configuration shown in FIG. 13, a depletion type MOS transistor 85 is provided between the first logic circuit 101 and the second logic circuit 102 to lower the high-level potential of the node 6. That is, when the threshold value of the depletion type MOS transistor 85 is set to Vth, the high level potential of the node 6 is lowered to VDDI−Vth. As a result, it is possible to avoid applying a potential having a polarity opposite to the potential for turning on the channel between the gate and the source of the p-channel MOS transistor 86 and to suppress an undesired current due to the GIDL characteristic. Further, when the high level potential of the node 6 is lowered in this way, it is lower than the high level potential (VCC) of the node 7, and therefore, as shown in FIG. Since the time until the level 6 decreases to the low level is shortened, the signal transmission speed can be increased accordingly.
Eighteenth is a configuration example of the input buffers 40 and 41 shown in FIG. This configuration basically adds a function for changing the logic threshold value for the input signal by the control signal CTL and a function for activating the circuit by the chip select signal CSB to the circuit shown in FIG. Has been.
The first logic circuit 101 that operates when the high-potential-side power supply VCC is supplied includes an n-channel MOS transistor 100 connected to an inverter in which a p-channel MOS transistor 83 and an n-channel MOS transistor 84 are connected in series. Are connected in series, and a p-channel MOS transistor 98 whose operation is controlled by a control signal CTL transmitted from the interface controller 45 shown in FIG. 1 is provided, and the p-channel MOS transistor 98 is connected in series. A p-channel MOS transistor 99 is provided. When the control signal CTL is set to low level by the interface controller 45 and the p-channel MOS transistor 98 is turned on, the p-channel MOS transistor 99 is connected in parallel to the p-channel MOS transistor 83.
A chip select signal CSB is transmitted through an inverter 96 to the gate electrode of the n-channel MOS transistor 100. When the chip controller 46 shown in FIG. 1 asserts the chip select signal CSB to the low level, the output logic of the inverter 96 is set to the high level and the n-channel MOS transistor 100 is turned on. One logic circuit 100 is activated. On the other hand, when the chip select signal CSB is negated to the high level by the chip controller 46, the output logic of the inverter 96 is set to the low level, and the n-channel MOS transistor 100 is turned off. The logic circuit 100 is deactivated.
A second logic circuit 102 that operates when the high-potential-side power supply VCC is supplied is disposed at the subsequent stage of the first logic circuit 101. Although not particularly limited, the second logic circuit 102 is a two-input NAND circuit 97. The output signal of the first logic circuit 101 is transmitted to one input terminal of the NAND circuit 97 via a depletion type MOS transistor 85. The depletion type MOS transistor 85 is provided in order to suppress an undesired current caused by the GIDL characteristic from flowing to the MOS transistor constituting the second logic circuit 102, as in the case of the structure shown in FIG. It is done. The chip select signal CSB is transmitted to the other input terminal of the NAND circuit 97 via the inverter 96. When the chip select signal CSB is asserted to a low level, the NAND circuit 97 is activated and signal output from the output terminal OUT is enabled.
A high breakdown voltage MOS transistor is employed as a component of a circuit that is operated by being supplied with the high-potential-side power supply VCC or a component of its peripheral circuit. In the configuration example shown in FIG. 18, the MOS transistors 83, 84, 85, 98, 99, 100 and the configuration transistors of the NAND circuit 97 are of a high breakdown voltage type. Note that the constituent transistors of the inverter 96 may not be of a high breakdown voltage type.
When the chip controller 46 asserts the chip select signal CSB to the low level and the first logic circuit 101 is activated, when the control signal CTL is at the high level, the p-channel MOS transistor 99 is turned on. Since it is excluded from the circuit operation, the logic threshold value of the first logic circuit 101 is a value determined by the gate size ratio between the p-channel MOS transistor 83 and the n-channel MOS transistor 84.
On the other hand, when the control signal CTL is at a low level, the p-channel MOS transistor 98 is turned on, so that the p-channel MOS transistor 99 is connected in parallel to the p-channel MOS transistor 83, thereby The logic threshold value of the logic circuit 101 is increased. Thus, by controlling the operation of the p-channel MOS transistor 98 according to the logic level of the control signal CTL, the logic threshold value for the input signal can be easily switched.
FIG. 19 shows a more detailed configuration example of the input buffer 40. In FIG. 19, the gate size ratio of the MOS transistors is shown. For example, “30 / 0.6” is indicated in the vicinity of the p-channel MOS transistor 98 because the ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistor 98 is 30 /0.6. The driving capability increases as the gate size ratio increases.
A first logic circuit 101 that is operated by being supplied with the high-potential-side power supply VCC, and a second logic circuit 102 that is disposed in the subsequent stage and that is operated by being supplied with the internal power supply VDDI are provided. An n-channel MOS transistor 85 as a coupling circuit for coupling the first logic circuit 101 and the second logic circuit 102 is provided in the same manner as shown in FIG.
The second logic circuit 102 has a 2-input NAND circuit 97, an inverter 110 for inverting the output signal of the 2-input NAND circuit 97, and a non-inverted output OUTT by inverting the output signal of the inverter 110. Inverter 111, an inverter 112 for inverting the output signal of the inverter 110, and an inverter 113 for obtaining an inverted output OUTB by inverting the output signal of the inverter 112. Each of inverters 110 to 113 is formed by connecting a p-channel MOS transistor coupled to internal power supply VDDI and an n-channel MOS transistor coupled to ground GND in series.
Since the metal wiring 53 formed in the upper layer of the formation site of the memory cell array 30 is relatively long, the wiring resistance 115 is relatively large. Since the wiring resistance 115 is connected in series to the resistance 73 included in the electrostatic breakdown protection element 24, the wiring resistance 115 exhibits an electrostatic breakdown protection function in the same manner as the resistance 73. For this reason, as the electrostatic breakdown protection element 24, a smaller one can be adopted in consideration of the value of the wiring resistance 115.
The input buffer 41 can employ the same configuration as that shown in FIG.
Next, detailed configurations of the output driver 42 and the output buffer 43 will be described.
FIG. 24 shows a configuration example of the output driver 42 and the output buffer 43.
The output driver 42 is not particularly limited, but is a signal output from the output drivers 201, 202, 203, damper resistors 211, 212 coupled to the output terminals of the output driver circuits 201, 202, and the output buffer 43. And a switching control circuit 204 for switching the rising and falling characteristics of the waveform. The output drivers 201, 202, 203 and the switching control circuit 204 are activated by the driver activation signal DOC transmitted from the chip controller 46. Then, the output drivers 201, 202, and 203 drive the output buffer 43 based on the data DATA input in a state activated by the driver activation signal DOC.
The output buffer 43 is not particularly limited, but includes a first output driver in which a p-channel MOS transistor 231 and an n-channel MOS transistor 232 are connected in series, a p-channel MOS transistor 233, and an n-channel MOS transistor. And a second output driver in which a transistor 234 is connected in series. The source electrodes of the p-channel MOS transistors 231 and 233 are coupled to the high potential side power supply VCC, and the source electrodes of the n-channel MOS transistors 232 and 234 are coupled to the ground GND.
An electrostatic breakdown protection element 26 is disposed between the output driver 42 and the output buffer 43. The electrostatic breakdown protection element 26 includes, but is not limited to, resistors 221, 222, 223, and 224. The output driver 42 and the output buffer 43 are coupled by a metal wiring 52 on the memory cell array 31 as is apparent from FIG. , 223, 224. The electrostatic breakdown protection element 27 disposed in the vicinity of the signal output pad 17 includes a diode 271 coupled to the output signal line of the output buffer 43 and the high potential side power supply VCC, and an output of the output buffer 43. And a diode 272 coupled to the signal line and ground GND.
The output driver circuits 201, 202, and 203 are basically configured as shown in FIG.
That is, the output driver circuits 201, 202, 203 basically include gate circuits 241, 242, 243, 244, p-channel MOS transistors 245, 247, and n-channel MOS transistors 246, 248. It consists of The gate circuit 241 takes the logic of the input data DATA and the driver activation signal DOC, and the p-channel MOS transistor 245 is driven according to the logic output. The gate circuit 242 takes the logic of the input data DATA and the driver activation signal DOC, and the n-channel MOS transistor 246 is driven according to the logic output. The gate circuit 243 takes the logic of the input data DATA and the driver activation signal DOC, and the p-channel MOS transistor 247 is driven according to the logic output. The gate circuit 244 takes the logic of the input data DATA and the driver activation signal DOC, and the n-channel MOS transistor 248 is driven according to the logic output. The source electrodes of the p-channel MOS transistors 245 and 247 are coupled to the high potential side power supply VCC, and the source electrodes of the n-channel MOS transistors 246 and 248 are coupled to the ground GND. The output driver circuit has a first output terminal 291 and a second output terminal 292 for driving the output buffer 43 in the open drain form of a MOS transistor. That is, the p-channel MOS transistor 245 and the drain electrode of the n-channel MOS transistor 246 are coupled via a resistor 249, and this output is made from the connection node between the p-channel MOS transistor 245 drain electrode and the resistor 249. A first output terminal 291 of the driver circuit is drawn out. The drain electrode of the p-channel MOS transistor 247 and the drain electrode of the n-channel MOS transistor 248 are coupled via a resistor 250, and the connection between the drain electrode of the n-channel MOS transistor 248 and the resistor 250 is made. A second output terminal 292 of the output driver circuit is drawn from the node.
The p-channel MOS transistor 245 has a function of resetting the p-channel MOS transistor by driving the gate electrode of the p-channel MOS transistor 231 or 233 in the output buffer 43 to a high level. The p-channel MOS transistor 245 is referred to as a “pMOS reset side circuit 281”.
The n-channel MOS transistor 246 and the resistor 249 have a function of setting the n-channel MOS transistor by driving the gate electrode of the p-channel MOS transistor 231 or 233 in the output buffer 43 to a low level. In this sense, the n-channel MOS transistor 246 and the resistor 249 are referred to as “pMOS set side circuit 282”.
The n-channel MOS transistor 247 and the resistor 250 have a function of setting the n-channel MOS transistor by driving the gate electrode of the n-channel MOS transistor 232 or 234 in the output buffer 43 to a high level. In this sense, the n-channel MOS transistor 247 and the resistor 250 are referred to as “nMOS set side circuit 283”.
The p-channel MOS transistor 248 has a function of resetting the n-channel MOS transistor by driving the gate electrode of the n-channel MOS transistor 232 or 234 in the output buffer 43 to a low level. The n-channel MOS transistor 248 is referred to as an “nMOS reset side circuit 284”.
The resistors 249 and 250 have a function of delaying driving of the output driver 43. Therefore, the driving capability of the output driver 42 can be switched by properly using a circuit in which such a resistor is interposed and a circuit in which the resistor is not interposed based on the driver activation signal DOC. Further, the output buffer drive size can be changed by changing the number of MOS transistors involved in the output operation in the output buffer 43 based on the driver activation signal DOC. For example, in order to correspond to the LV-CMOS interface or the LV-TTL interface, as shown in FIG. 26, the pMOS reset side circuit 281 in the output driver circuits 201, 202, 203 is based on the driver activation signal DOC. The pMOS set side circuit 282, the nMOS set side circuit 283, and the nMOS reset side circuit 284 may be used properly. That is, in order to correspond to the LV-CMOS interface, the pMOS set side circuit 282 and the nMOS set side circuit 283 in the output driver circuit 201 and all the set side circuits and reset side circuits in the output driver circuits 202 and 203 are used. As a result, the output buffer 43 is driven at high speed. As apparent from FIG. 39, in the LV-CMOS interface, the low-level noise margin 131 and the high-level noise margin 132 are large, so that the output buffer 43 is driven at high speed. The tr / tf value, which is the waveform rising / falling characteristic of the output signal from 43, can be reduced to shorten the signal transmission time.
On the other hand, in order to correspond to the LV-TTL interface, the pMOS set side circuit 282 and the nMOS set side circuit 283 in the output driver circuit 201 and the pMOS reset side circuit 281 and the nMOS reset side circuit 284 in the output driver circuit 202 are provided. The other circuits used are not involved in driving the output buffer 43. By reducing the drive capability of the output buffer 43 in this way, the output current from the output buffer 43 is reduced, thereby reducing the noise included in the output waveform. In the LV-TTL interface, as shown in FIG. 40, the lower the high potential side power supply VCC level, the smaller the low level noise margin 141 and the higher the high potential side power supply VCC level. This is because the noise margin 142 on the high level side becomes small, and it is necessary to suppress noise included in the output signal by driving the output buffer 43 at a low speed.
27 to 29 show further detailed configuration examples of the output driver 42 and the output buffer 43. FIG.
The gate size ratio (W / L) of the corresponding MOS transistor is shown in the vicinity of the MOS transistor shown in FIGS.
As shown in FIG. 27, the switching control circuit 204 includes a first DOC driver 262, a second DOC driver 261, and a data driver 263. Output signals DOC_B_C, DOC_T_C, DOC_B, DOC_T, DATA_B, and DATA_T from the first DOC driver 262, the second DOC driver 261, and the data driver 263 are output driver circuits 201, 202-1, and 202-2 shown in FIG. 203-1 and 203-2. The output driver circuits 202-1 and 202-2 in FIG. 28 correspond to the output driver circuit 202 in FIG. 24, and the output driver circuits 203-1 and 203-2 in FIG. This corresponds to the output driver circuit 203 in FIG. The output signals of the output driver circuits 201, 202-1, 202-2, 203-1, 203-2 are transmitted to the output buffer 43 shown in FIG. Electrostatic breakdown protection elements 27-1 and 27-2 are arranged at the front and rear stages of the output buffer 43, respectively. These electrostatic breakdown protection elements 27-1 and 27-2 correspond to the electrostatic breakdown protection element 27 in FIG. Since the MOS transistor included in the output buffer 43 needs to drive an external load, the gate size ratio (W / L) is 100 / 0.6, 200 / 0.6, etc. A transistor having a larger gate size ratio than the MOS transistor is employed.
FIG. 30 shows a truth table of the main parts of the output driver 42 and the output buffer 43 in FIGS. In FIG. 30, “L” indicates a low level, “H” indicates a high level, “HZ” indicates a high impedance state, and X indicates logic indefinite.
FIG. 31 shows a layout example in which two systems of the output driver 42 and the output buffer 43 in FIGS. 27 to 29 are arranged.
The control circuit 299 includes an interface controller 45 and a chip controller 46 and outputs various control signals. The output drivers 42-1 and 42-2 correspond to the output driver 42 shown in FIG. Output pads 17-1 and 17-2 are formed at predetermined intervals on the edge of the semiconductor chip, and output buffers 43-1 and 43-2 are arranged between the output pads 17-1 and 17-2. The output buffers 43-1 and 43-2 correspond to the output buffer 43 shown in FIG. Electrostatic breakdown protection elements 27-1 and 27-2 are formed in the formation areas of the output buffers 43-1 and 43-2. Since the output drivers 42-1 and 42-2 and the output buffers 43-1 and 43-2 are arranged separately, the formation area of the output buffers 43-1 and 43-2 is relatively small, and the output pad 17 -1 and 17-2.
In addition, the resistors, capacitors, and diodes in this example can be configured as follows.
For example, as shown in FIG. 35, a resistor 403 can be obtained between terminals 401 and 402 by using a polysilicon layer formed on a semiconductor substrate such as silicon (Si).
As shown in FIG. 36, an N-type well (WELL) formed in a semiconductor substrate (P-type) and a semiconductor region (P ⁺ , N ⁺ ) Can be used to obtain the resistor 414 between the terminals 411 and 412 and further to obtain the diode 415 coupled thereto.
As shown in FIG. 37, a P-type well (WELL) formed in a semiconductor substrate (P-type) and a semiconductor region (N) stacked thereon ⁺ , N ⁻ ) And a conductor, a capacitor 423 can be obtained between the terminals 421 and 422.
As shown in FIG. 38, a P-type well (WELL) formed in a semiconductor substrate (N-type) and a semiconductor region (N ⁺ , N ⁺ ) And a conductor, a capacitor 433 can be obtained between the terminals 431 and 432, and a diode 435 coupled to the capacitor 433 can be obtained.
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.
For example, various modes can be considered for the bonding option as shown below.
FIGS. 7 to 12 show another configuration example of the bonding option.
As shown in FIG. 7, the first protection circuit ESD1 shown in FIG. 4 may be adopted for all of the electrostatic breakdown protection elements 20, 21, 23, 25.
As shown in FIG. 8, the logic threshold of the input buffers 40 and 41 and the rise of the waveform of the output signal of the output driver 42 are determined by the combination of the logics of the two control lines 55-1 and 55-2. The falling (tr / tf) characteristics can be adjusted in four stages. In this case, bonding option pads 18-1 and 18-2 are formed at one end of the semiconductor chip 9, and bonding option pads 13-1 and 13-2 are formed at the other end. . The electrostatic breakdown protection element 25-1 is disposed in the vicinity of the pad 18-1, the electrostatic breakdown protection element 20-1 is disposed in the vicinity of the pad 13-1, and the electrostatic breakdown protection element 25-2 is disposed in the pad 18-. 2 and the electrostatic breakdown protection element 20-2 is disposed near the pad 13-2. Bonding option pads 18-1 and 13-1 are coupled via control line 55-1, and bonding option pads 18-2 and 13-2 are coupled via control line 55-2. Is done. Depending on the bonding option, both of the control lines 55-1 and 55-2 can be set to high level or low level, and either one of the control lines 55-1 and 55-2 is set to high level or low level. Therefore, a total of four types of logic combinations can be obtained.
And in FIG. 8, you may make it cross the control lines 55-1 and 55-2 in the middle of them. The configuration in this case is shown in FIG.
Furthermore, the logic threshold value in the input buffers 40 and 41 and the waveform rising / falling (tr / tf) characteristic of the output signal in the output driver 42 can be adjusted in multiple stages. For example, the configuration shown in FIG. 10 allows adjustment in 16 steps. In this case, bonding option pads 18-1 to 18-4 are formed at one end of the semiconductor chip 9, and bonding option pads 13-1 to 13-4 are formed at the other end. . The electrostatic breakdown protection elements 25-1 to 25-4 are arranged in the vicinity of the corresponding pads 18-1 to 18-4, and the electrostatic breakdown protection elements 20-1 to 20-4 are respectively corresponding to the pads 13. It is arranged in the vicinity of −1 to 13-4. Bonding option pads 18-1 and 13-1 are coupled via control line 55-1, and bonding option pads 18-2 and 13-2 are coupled via control line 55-2. Is done. Also, the bonding option pads 18-3 and 13-3 are coupled via a control line 55-3, and the bonding option pads 18-4 and 13-4 are coupled via a control line 55-4. Are combined. There are 16 combinations of logic in the control lines 55-1 to 55-4 depending on which pad is coupled by the wires 61-1, 61-2, 13-1, and 13-2 by the bonding option.
As shown in FIG. 11, if two external terminals 12-1 and 12-2 for ground GND can be arranged adjacent to each other, in semiconductor chip 9, two external terminals for ground GND are provided. Corresponding to 12-1 and 12-2, pads 14-1 and 14-2 for ground GND are formed, and pads 13-1 and 13-2 for bonding options are formed in the vicinity thereof. Also good. In order to bring the control line 55-1 to the low level, the external terminal 12-1 and the pad 13-1 may be coupled by the bonding option. To bring the control line 55-2 to the low level, the external line is selected by the bonding option. What is necessary is just to couple | bond the terminal 12-2 and the pad 13-2.
As shown in FIG. 12, corresponding to the four edges of the semiconductor chip 9, external terminals 11-1 and 11-2 for supplying the high potential side power supply VCC, and the low potential side power supply (ground GND). If the external terminals 12-1 and 12-2 for supplying are provided, bonding options can be formed correspondingly. As in the case of the configuration shown in FIG. 10, the logic threshold value in the input buffers 40 and 41 and the waveform rising / falling (tr / tf) characteristic of the output signal in the output driver 42 are adjusted in 16 steps. can do.
In the above embodiment, an undesired current flowing in a transistor exhibiting GIDL characteristics is avoided by inserting a depletion type MOS transistor, but an enhancement type MOS transistor is used instead of this depletion type MOS transistor. You can also. For example, as shown in FIG. 16, an enhancement type MOS transistor 95 is provided between the first logic circuit 101 and the second logic circuit 102. In that case, a p-channel MOS transistor 94 for feedback is provided. The p-channel MOS transistor 94 is turned on when the output signal of the second logic circuit 102 becomes low level, and reduces the high-level potential of the node 8 to the internal power supply VDDI. Even if such a configuration is adopted, it is possible to avoid applying a potential having the opposite polarity to the potential for turning on the channel between the gate and the source of the p-channel MOS transistor 86, which is undesirable due to the GIDL characteristic. Current can be suppressed.
Various methods for switching the logical threshold value in the input buffers 40 and 41 are conceivable. For example, as shown in FIG. 20, the control signal CTL may be supplied to the gate electrode of the p-channel MOS transistor 98, or to the gate electrode of the p-channel MOS transistor 98 as shown in FIG. The control signal CTL may be supplied to the gate electrode of the p-channel MOS transistor 99 by supplying the input signal IN. In the above example, the switching of the logic threshold value in the input buffers 40 and 41 is performed by the p-channel MOS transistor, but this switching can also be performed by the n-channel MOS transistor. For example, as shown in FIG. 22, an inverter is formed by connecting a p-channel MOS transistor 98 and an n-channel MOS transistor 124 in series, and an n-channel connected in series to the n-channel MOS transistor 123. When the n-type MOS transistor 84 is turned on by a control signal CTLB (inverted signal of CTL), the n-channel type MOS transistor 123 is connected to the n-channel type MOS transistor 124 in parallel so as to participate in the circuit operation. To do. The logic threshold value can be changed depending on whether or not the n-channel MOS transistor 123 is connected in parallel to the n-channel MOS transistor 124. However, as shown in FIG. 23, the characteristic curve 126 in the case where the switching of the logic threshold value in the input buffers 40 and 41 is performed by an n-channel MOS transistor (see FIG. 22), and the p-channel MOS transistor As can be seen from the comparison of the characteristic curve 125 (see FIG. 20 and FIG. 21), the switching of the logic threshold value in the input buffers 40 and 41 is performed by an n-channel MOS transistor. While a large amount of through current I flows, when the logic threshold value switching in the input buffers 40 and 41 is performed by an n-channel MOS transistor, there is an advantage that the through current I can be reduced.
In the above example, the bonding option is adopted, but a fuse circuit that enables logic setting by blowing a specific fuse can also be adopted.
In addition to the input threshold value in the input buffer and the rising / falling (tr / tf) characteristics of the output waveform in the output buffer, the function selection target is the operating power supply voltage, package, capacity, bit width, and function. (Truth table, state transition diagram).
Industrial applicability
The present invention can be applied to a semiconductor integrated circuit including an input buffer and an output buffer, particularly a semiconductor integrated circuit as a semiconductor memory device having a memory cell array for storing information.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device which is an embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 2 is an explanatory diagram of a configuration example of a main part in the semiconductor memory device.
FIG. 3 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 4 is a circuit diagram of a configuration example of the electrostatic breakdown protection element included in the semiconductor memory device.
FIG. 5 is a circuit diagram showing another configuration example of the electrostatic breakdown protection element included in the semiconductor memory device.
FIG. 6 is a circuit diagram of another configuration example of the electrostatic breakdown protection element included in the semiconductor memory device.
FIG. 7 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 8 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 9 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 10 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 11 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 12 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
FIG. 13 is a circuit diagram of a basic configuration example of an input buffer included in the semiconductor memory device.
FIG. 14 is a circuit diagram of a configuration example of a circuit to be compared with the input buffer shown in FIG.
FIG. 15 is an explanatory diagram of the GIDL characteristic of the MOS transistor.
FIG. 16 is a circuit diagram showing another basic configuration example of the input buffer included in the semiconductor memory device.
FIG. 17 is a waveform diagram for explaining the operation of the input buffer.
FIG. 18 is a circuit diagram of a configuration example of an input buffer included in the semiconductor memory device.
FIG. 19 is a circuit diagram showing a detailed configuration example of an input buffer included in the semiconductor memory device.
FIG. 20 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
FIG. 21 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
FIG. 22 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
FIG. 23 is a characteristic diagram of an input buffer included in the semiconductor memory device.
FIG. 24 is a circuit diagram of a configuration example of an output driver and an output buffer included in the semiconductor memory device.
FIG. 25 is a circuit diagram showing a configuration example of a main part in the output driver.
FIG. 26 is an explanatory diagram of an operation example of the output driver.
FIG. 27 is a circuit diagram showing a detailed configuration example of a main part in the output driver.
FIG. 28 is a circuit diagram showing a detailed configuration example of a main part in the output driver.
FIG. 29 is a circuit diagram showing a detailed configuration example of the output buffer and its peripheral portion.
FIG. 30 is a diagram for explaining the operation of the main part of the output driver and output buffer in FIGS. 27 to 29.
FIG. 31 is an explanatory diagram of a layout example of the output driver and output buffer in FIGS. 27 to 29.
FIG. 32 is a block diagram showing a configuration example of a step-down circuit included in the input buffer.
FIG. 33 is a circuit diagram showing a configuration example of a main part in the step-down circuit.
FIG. 34 is a circuit diagram showing another configuration example of the main part of the step-down circuit.
FIG. 35 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
FIG. 36 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
FIG. 37 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
FIG. 38 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
FIG. 39 is a characteristic explanatory diagram of an LV-CMOS interface employed in the semiconductor memory device.
FIG. 40 is a characteristic explanatory diagram of an LV-TTL interface employed in the semiconductor memory device.

Claims (17)

An input buffer to capture the signal;
An output buffer for outputting a signal;
A controller capable of changing the rising / falling characteristics of the signal waveform output from the output buffer and the logical threshold value in the input buffer according to the logic level of the common node signal given by the option. A semiconductor integrated circuit. An input buffer to capture the signal;
An output buffer for outputting a signal;
A first pad provided at one end of the semiconductor chip; a second pad electrically connected to the first pad; and provided at the other end of the semiconductor chip;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A semiconductor integrated circuit comprising: a controller; An input buffer to capture the signal;
An output buffer for outputting a signal;
A first pad provided at one end of the semiconductor chip;
A second pad provided on the other end of the semiconductor chip and connected to the first pad;
A third pad for power supply on the high potential side;
A fourth pad for supplying low-potential-side power;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A controller, and
A semiconductor integrated circuit, wherein when one of the first pad and the second pad is arranged in the vicinity of the third pad, the other is arranged in the vicinity of the fourth pad. An input buffer to capture the signal;
An output buffer for outputting a signal;
A first pad provided at one end of the semiconductor chip;
A second pad provided on the other end of the semiconductor chip and connected to the first pad;
A third pad for power supply on the high potential side;
A fourth pad for supplying low-potential-side power;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A controller,
A first electrostatic breakdown protection element for protecting an internal circuit from static electricity input through the first pad;
A second electrostatic breakdown protection element for protecting an internal circuit from static electricity inputted through the second pad, and one of the first pad and the second pad is the third pad. A semiconductor integrated circuit in which the other is disposed in the vicinity of the fourth pad. A step-down circuit for stepping down the input power supply voltage to a predetermined level;
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit is a semiconductor integrated circuit including a depletion type first transistor. A step-down circuit for stepping down the input power supply voltage to a predetermined level;
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit includes a depletion-type first transistor,
The second logic circuit includes a second transistor for capturing a signal input through the first transistor,
The second transistor is a semiconductor integrated circuit having a characteristic that a drain current increases when a potential having a polarity opposite to a potential for turning on a channel is applied between a gate and a source. A step-down circuit for stepping down the input power supply voltage to a predetermined level;
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
A capacitor formed by a gate capacitance of a depletion type transistor,
The coupling circuit includes a depletion-type first transistor that is formed in the same process as the capacitor and is turned on when an output voltage from the step-down circuit is supplied.
The second logic circuit includes a second transistor for capturing a signal input through the first transistor,
The second transistor is a semiconductor integrated circuit having a characteristic that a drain current increases when a potential having a polarity opposite to a potential for turning on a channel is applied between a gate and a source. A step-down circuit for stepping down the input power supply voltage to a predetermined level;
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The step-down circuit includes a capacitor formed by a gate capacitance of a depletion type transistor,
The coupling circuit includes a depletion-type first transistor that is formed in the same process as the capacitor and is turned on when an output voltage from the step-down circuit is supplied.
The second logic circuit includes a second transistor for capturing a signal input through the first transistor,
The second transistor is a semiconductor integrated circuit having a characteristic that a drain current increases when a potential having a polarity opposite to a potential for turning on a channel is applied between a gate and a source. A step-down circuit for stepping down the input power supply voltage to a predetermined level;
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit feeds back an enhancement type first transistor that is turned on when an output voltage from the step-down circuit is supplied, and an output voltage of the second logic circuit to the input side of the second logic circuit. A feedback transistor, and
The second logic circuit includes a second transistor for capturing a signal input through the first transistor,
The second transistor is a semiconductor integrated circuit having a characteristic that a drain current increases when a potential having a polarity opposite to a potential for turning on a channel is applied between a gate and a source. An input buffer to capture the signal;
An output buffer for outputting a signal;
A controller capable of changing a rising / falling characteristic of a signal waveform output from the output buffer and a logical threshold value in the input buffer;
A step-down circuit for stepping down an input power supply voltage to a predetermined level, and a semiconductor integrated circuit,
The input buffer is
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit is a semiconductor integrated circuit including a depletion type first transistor. An input buffer to capture the signal;
An output buffer for outputting a signal;
A first pad provided at one end of the semiconductor chip; a second pad electrically connected to the first pad; and provided at the other end of the semiconductor chip;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A controller,
A step-down circuit for stepping down an input power supply voltage to a predetermined level, and a semiconductor integrated circuit,
The input buffer is
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit is a semiconductor integrated circuit including a depletion type first transistor. An input buffer to capture the signal;
An output buffer for outputting a signal;
A first pad provided at one end of the semiconductor chip;
A second pad provided on the other end of the semiconductor chip and connected to the first pad;
A third pad for power supply on the high potential side;
A fourth pad for supplying low-potential-side power;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A controller,
A step-down circuit for stepping down the input power supply voltage to a predetermined level, and when one of the first pad and the second pad is disposed in the vicinity of the third pad, the other is A semiconductor integrated circuit disposed in the vicinity of the fourth pad,
The input buffer is
A first logic circuit that operates by being supplied with the power supply voltage;
A second logic circuit which is arranged at a subsequent stage of the first logic circuit and operates by being supplied with an output voltage from the step-down circuit;
A coupling circuit for coupling the first logic circuit and the second logic circuit;
The coupling circuit is a semiconductor integrated circuit including a depletion type first transistor. A memory cell array in which a plurality of memory cells are arranged in an array;
An output circuit for externally outputting data read from the memory cell array,
The output circuit is
An output buffer for outputting a signal;
An output driver disposed opposite to the output buffer via the memory cell array, and driving the output buffer based on data read from the memory cell array,
A semiconductor integrated circuit in which the output buffer and the output driver are coupled through a signal wiring formed using an upper layer of a portion where the memory cell array is formed. A memory cell array in which a plurality of memory cells are arranged in an array;
An input circuit for capturing write data to the memory cell array;
An output circuit for externally outputting data read from the memory cell array,
The output circuit is
An output buffer for outputting a signal;
An output driver disposed opposite to the output buffer via the memory cell array and for driving the output buffer based on data read from the memory cell array;
A controller capable of changing a rising / falling characteristic of a signal waveform output from the output buffer and a logical threshold value in the input buffer;
A semiconductor integrated circuit in which the output buffer and the output driver are coupled through a signal wiring formed using an upper layer of a portion where the memory cell array is formed. A memory cell array in which a plurality of memory cells are arranged in an array;
An input circuit for capturing write data to the memory cell array;
An output circuit for externally outputting data read from the memory cell array,
The output circuit is
An output buffer for outputting a signal;
An output driver disposed opposite to the output buffer via the memory cell array and for driving the output buffer based on data read from the memory cell array;
A first pad provided at one end of the semiconductor chip; a second pad electrically connected to the first pad; and provided at the other end of the semiconductor chip;
The rising and falling characteristics of the signal waveform output from the output buffer and the logic threshold value in the input buffer can be changed according to the logic level fixed by bonding to the first pad or the second pad. A controller, and
A semiconductor integrated circuit in which the output buffer and the output driver are coupled through a signal wiring formed using an upper layer of a portion where the memory cell array is formed. An input buffer interfaced externally, an output buffer interfaced externally,
A single-node signal line commonly used for changing the logic threshold of the input buffer and the transition characteristics of the signal output from the output buffer;
A semiconductor integrated circuit comprising: a selecting unit that determines a state of the signal wiring according to a setting state; 17. The semiconductor integrated circuit according to claim 16, wherein said selection means is an electrode on a semiconductor chip whose connection to a high potential or a low potential is determined by a bonding option.

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