JPWO2003021668A1 - Wiring board, semiconductor device, and manufacturing method thereof - Google Patents

Wiring board, semiconductor device, and manufacturing method thereof Download PDF

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Publication number
JPWO2003021668A1
JPWO2003021668A1 JP2003525905A JP2003525905A JPWO2003021668A1 JP WO2003021668 A1 JPWO2003021668 A1 JP WO2003021668A1 JP 2003525905 A JP2003525905 A JP 2003525905A JP 2003525905 A JP2003525905 A JP 2003525905A JP WO2003021668 A1 JPWO2003021668 A1 JP WO2003021668A1
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Japan
Prior art keywords
wiring
conductor
wiring board
insulating base
manufacturing
Prior art date
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Pending
Application number
JP2003525905A
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Japanese (ja)
Inventor
福富　直樹
直樹 福富
鈴木　和久
和久 鈴木
嶋田　修
修 嶋田
竹内　一雅
一雅 竹内
善昭 若島
善昭 若島
進 沖川
進 沖川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Metals Ltd
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Metals Ltd
Showa Denko Materials Co Ltd
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Application filed by Hitachi Chemical Co Ltd, Hitachi Metals Ltd, Showa Denko Materials Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of JPWO2003021668A1 publication Critical patent/JPWO2003021668A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本発明では、絶縁基材と、該絶縁基材の表裏一方の面に設けられた配線と、該絶縁基材内に埋め込まれた導体部材とを備え、導体部材の一端が絶縁基材表面に露出して配線に接続しており、他端は絶縁基材内に埋め込まれている配線基板、該配線基板を用いた半導体装置、及びそれらの製造方法が提供される。In the present invention, an insulating base, wiring provided on one of the front and back surfaces of the insulating base, and a conductive member embedded in the insulating base are provided, and one end of the conductive member is provided on the surface of the insulating base. Provided are a wiring board that is exposed and connected to a wiring and the other end is embedded in an insulating base material, a semiconductor device using the wiring board, and a method of manufacturing the same.

Description

技術分野
本発明は、配線基板と、該配線基板を用いた半導体装置と、それらの製造方法に関する。
背景技術
半導体の集積度が向上するに従い、入出力端子数が増加している。したがって、多くの入出力端子数を有する半導体装置が必要になった。一般に、入出力端子はパッケージの周辺に一列配置するタイプと、周辺だけでなく内部まで多列に配置するタイプがある。前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）が代表的である。これを多端子化する場合は、端子ピッチを縮小することが必要であるが、０．５ｍｍピッチ以下の領域では、配線板との接続に高度な技術が必要になる。後者のアレイタイプは比較的大きなピッチで端子配置が可能なため、多ピン化に適している。
従来、アレイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は挿入型となり、表面実装には適していない。このため、表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と称するパッケージが開発されている。ＢＧＡの分類としては、（１）セラミックタイプ、（２）プリント配線板タイプ及び（３）ＴＡＢ（ｔａｐｅ ａｕｔｏｍａｔｅｄ ｂｏｎｄｉｎｇ）を使ったテープタイプなどがある。このうち、セラミックタイプについては、従来のＰＧＡに比べるとマザーボードとパッケージ間の距離が短くなるために、マザーボードとパッケージ間の熱応力差に起因するパッケージ反りが深刻な問題である。また、プリント配線板タイプについても、基板の反り、耐湿性、信頼性などに加えて基板厚さが厚いなどの問題があり、ＴＡＢ技術を適用したテープＢＧＡが提案されている。
パッケージサイズの更なる小型化に対応するものとして、半導体素子とほぼ同等サイズの、いわゆる素子サイズパッケージ（ＣＳＰ：Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案されている。これは、半導体素子の周辺部でなく、実装領域内に外部配線基板との接続部を有するパッケージである。
具体例としては、バンプ付きポリイミドフィルムを半導体素子の表面に接着し、素子と金リード線により電気的接続を図った後、エポキシ樹脂などをポッティングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．１４０，Ｐ１８−１９）や、仮基板上に半導体素子及び外部配線基板との接続部に相当する位置に金属バンプを形成し、半導体素子をフェースダウンボンディング後、仮基板上でトランスファモールドしたもの（Ｓｍａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃｋａｇｅ ＣＳＰ；Ｔｈｅ Ｓｅｃｏｎｄ ＶＬ ＳＩ Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐａｎ，ｐ４６−５０，１９９４）などである。
一方、前述のように、ＢＧＡやＣＳＰ分野でポリイミドテープをベースフィルムとして利用したパッケージが検討されている。この場合、ポリイミドテープとしては、ポリイミドフィルム上に接着剤層を介して銅箔をラミネートしたものが一般的であり、耐熱性や耐湿性などの観点から銅箔上に直接ポリイミド層を形成した、いわゆる２層フレキシブル基材が好ましい。
この２層フレキシブル基材の製造方法としては、▲１▼銅箔上にポリイミドの前駆体であるポリアミック酸を塗布した後熱硬化させる方法、▲２▼硬化したポリイミドフィルム上に真空成膜法や無電解めっき法などにより金属薄膜を形成する方法、の２つに大別される。
２層フレキシブル基材では、例えばレーザ加工を適用して所望する部分のポリイミドを除去して銅箔に達する凹部を設ける場合には、ポリイミドフィルムができる限り薄いことが好ましい。その反面、２層フレキシブル基材をリードフレーム状に加工してハンドリングする場合、ベースフィルム厚さが薄いとハンドリング性やフレームとしての剛直性に欠けるなどの問題がある。
以上のように小型化高集積度化に対応できる半導体装置として、種々の提案がされているが、性能、特性、生産性等全てにわたって満足するよう一層の改善が望まれている。
発明の開示
本発明は、小型化、高集積度化に対応できる半導体装置（半導体パッケージ）を、生産性良くかつ安定的に製造するための半導体素子搭載用配線基板と、該基板を用いた半導体装置と、それらの製造方法とを提供することを目的とする。
本発明では、絶縁基材と、該絶縁基材の表裏一方の面に設けられた配線を有する配線部材と、該絶縁基材内に埋め込まれた導体部材とを備え、導体部材の一端は絶縁基材表面に露出して上記配線に接続しており、他端は絶縁基材内に埋め込まれている配線基板が提供される。なお、本発明の配線基板は、絶縁基材の他方の面（すなわち、表裏のうち導体部材が露出していない面）に設けられた支持部材を、さらに備えていてもよい。
さらに本発明では、絶縁基材と、該絶縁基材の表裏一方の面に設けられた配線を有する配線部材と、該絶縁基材の他方の面に設けられた支持部材とを備える配線基板が提供される。この配線基板は、絶縁基材内に埋め込まれた、配線に接続した導体部材をさらに備えていてもよいが、導体部材が設けられていなくてもよい。導体部材を設ける場合、その一端は配線に接続している必要があるが、他端は絶縁基材に被覆されていてもよく、支持部材と導体部材とのエッチング条件が異なっていれば、導体部材の他端が支持部材に達していてもよい。
また、本発明では、上述した本発明の配線基板の製造方法として、
（１）表裏一方の面に突起状の導体部材を設けた配線部材と、絶縁基材とを、導体部材を内側にして対向させて積層させる積層工程を備える配線基板の製造方法、
（２）表裏一方の面に突起状の導体部材を設けた導体層と、絶縁基材とを、導体部材を内側にして対向させて積層させる積層工程、及び、導体層の不要な箇所を除去して配線部材を形成する配線部材形成工程を備える配線基板の製造方法、並びに、
（３）配線部材と、絶縁基材と、支持部材とをこの順で積層する積層工程を備える配線基板の製造方法、
が提供される。
さらに本発明では、上述した本発明の配線基板の配線部材表面に半導体素子を搭載する搭載工程、半導体素子と配線部材表面の配線とを電気的に接続する接続工程、半導体素子を封止部材により覆って封止する封止工程、及び、絶縁基材の一部を除去して導体部材の少なくとも一部を露出させる絶縁基材除去工程を備える半導体装置の製造方法が提供される。なお、半導体素子を封止部材により覆って封止する封止工程をさらに設けてもよい。この場合、封止工程と絶縁基材除去工程とは、いずれが先であっても構わない。
また本発明では本発明の配線基板の配線部材側表面に半導体素子を搭載する搭載工程、半導体素子と配線部材表面の配線とを電気的に接続する接続工程、支持部材の少なくとも一部を除去して絶縁基材の少なくとも一部を露出させる支持部材除去工程、絶縁基材の少なくとも一部を除去して貫通孔を形成し、配線の少なくとも一部を露出させる絶縁基材除去工程、及び、貫通孔を導体で充填して配線に接続した導体部材を形成する導体部材形成工程を備える半導体装置の製造方法が提供される。
なお、本発明の半導体装置の製造方法では、半導体素子の配線基板への搭載は、接着剤を介して行うことができるが、接着剤を介さずに行ってもよい。
さらに本発明では、上述した本発明の製造方法によって製造された半導体装置が提供される。
発明を実施するための最良の形態
本発明の配線基板は、絶縁基材と、配線部材と、導体部材とを備え、導体部材の一端が絶縁基材表面に露出して配線部材の配線に接続しており、他端が絶縁基材内に埋め込まれている。
この配線部材における絶縁基材の材質は、特に限定されるものではないが、例えば、エポキシ樹脂、ポリアミドイミド樹脂などを含む樹脂組成物、樹脂前駆体組成物又はその硬化物を用いることができる。樹脂組成物又は樹脂前駆体組成物はウィスカを含むことが好ましく、樹脂にはポリアミドイミドを用いることが特に好ましい。絶縁基材の樹脂は硬化前又は半硬化状態であっても構わないが、半導体装置においては硬化後であることが望ましい。
本発明において絶縁基材として好適なエポキシ樹脂硬化物は、エポキシ樹脂及び硬化剤を含むエポキシ樹脂組成物を硬化させることにより得られる。このエポキシ樹脂組成物（好ましくは熱硬化性樹脂組成物）には、さらに必要に応じて、硬化促進剤、触媒、エラストマ、難燃剤などを配合してもよい。
ここで用いることのできるエポキシ樹脂は、分子内にエポキシ基を有するものであればどのようなものでもよく、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、脂環式エポキシ樹脂、脂肪族鎖状エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡノボラック型エポキシ樹脂、ビフェノールのジグリシジルエーテル化物、ナフタレンジオールのジグリシジルエーテル化物、フェノール類のジグリシジルエーテル化物、アルコール類のジグリシジルエーテル化物、及びこれらのアルキル置換体、ハロゲン化物、水素添加物などがある。これらは併用してもよく、エポキシ樹脂以外の成分が不純物として含まれていてもよい。
本発明において、ハロゲン化ビスフェノールＡ型エポキシ樹脂、ハロゲン化ビスフェノールＦ型エポキシ樹脂、ハロゲン化ビスフェノールＳ型エポキシ樹脂、テトラブロモビスフェノールＡ等のハロゲン化ビスフェノール化合物とエピクロルヒドリンを反応させて得られるべきエポキシ樹脂のようにエーテル基が結合しているベンゼン環のエーテル基に対してオルト位が塩素、臭素等のハロゲン原子で置換されているエポキシ樹脂を使用すると、バイアホール等の形成に際して行われる除去処理において、エポキシ樹脂硬化物の分解及び／又は溶解の効率が特によい。
本発明で使用するエポキシ樹脂用硬化剤は、エポキシ樹脂を硬化させるものであれば、限定することなく使用でき、例えば、多官能フェノール類、アミン類、イミダゾール化合物、酸無水物、有機リン化合物及びこれらのハロゲン化物などがある。
多官能フェノール類の例として、単環二官能フェノールであるヒドロキノン、レゾルシノール、カテコール、多環二官能フェノールであるビスフェノールＡ、ビスフェノールＦ、ナフタレンジオール類、ビフェノール類、及びこれらのハロゲン化物、アルキル基置換体などがある。さらに、これらのフェノール類とアルデヒド類との重縮合物であるノボラック、レゾールがある。
アミン類の例としては、脂肪族又は芳香族の第一級アミン、第二級アミン、第三級アミン、第四級アンモニウム塩及び脂肪族環状アミン類、グアニジン類、尿素誘導体等がある。これらの化合物には、Ｎ、Ｎ−ベンジルジメチルアミン、２−（ジメチルアミノメチル）フェノール、２，４，６−トリス（ジメチルアミノメチル）フェノール、テトラメチルグアニジン、トリエタノールアミン、Ｎ、Ｎ’−ジメチルピペラジン、１、４−ジアザビシクロ［２，２，２］オクタン、１，８−ジアザビシクロ［５，４，０］−７−ウンデセン、１，５−ジアザビシクロ［４，４，０］−５−ノネン、ヘキサメチレンテトラミン、ピリジン、ピコリン、ピペリジン、ピロリジン、ジメチルシクロヘキシルアミン、ジメチルヘキシルアミン、シクロヘキシルアミン、ジイソブチルアミン、ジ−ｎ−ブチルアミン、ジフェニルアミン、Ｎ−メチルアニリン、トリ−ｎ−プロピルアミン、トリ−ｎ−オクチルアミン、トリ−ｎ−ブチルアミン、トリフェニルアミン、テトラメチルアンモニウムクロライド、テトラメチルアンモニウムブロマイド、テトラメチルアンモニウムアイオダイド、トリエチレンテトラミン、ジアミノジフェニルメタン、ジアミノジフェニルエーテル、ジシアンジアミド、トリルビグアニド、グアニル尿素、ジメチル尿素等が挙げられる。
イミダゾール化合物の例としては、イミダゾール、２−エチルイミダゾール、２−エチル−４−メチルイミダゾール、２−メチルイミダゾール、２−フェニルイミダゾール、２−ウンデシルイミダゾール、１−ベンジル−２−メチルイミダゾール、２−ヘプタデシルイミダゾール、４，５−ジフェニルイミダゾール、２−メチルイミダゾリン、２−フェニルイミダゾリン、２−ウンデシルイミダゾリン、２−ヘプタデシルイミダゾリン、２−イソプロピルイミダゾール、２，４−ジメチルイミダゾール、２−フェニル−４−メチルイミダゾール、２−エチルイミダゾリン、２−フェニル−４−メチルイミダゾリン、ベンズイミダゾール、１−シアノエチルイミダゾールなどがある。
酸無水物の例としては、無水フタル酸、ヘキサヒドロ無水フタル酸、ピロメリット酸二無水物、ベンゾフェノンテトラカルボン酸二無水物等がある。
有機リン化合物としては、有機基を有するリン化合物であれば特に限定されずに使用でき、例えば、ヘキサメチルリン酸トリアミド、リン酸トリ（ジクロロプロピル）、リン酸トリ（クロロプロピル）、亜リン酸トリフェニル、リン酸トリメチル、フェニルフォスフォン酸、トリフェニルフォスフィン、トリ−ｎ−ブチルフォスフィン、ジフェニルフォスフィンなどがある。
これらの硬化剤は、１種類を単独で用いてもよく、２種以上を組み合わせて用いてもよい。
これらエポキシ樹脂用硬化剤の配合量は、エポキシ基の硬化反応を進行させることができれば、特に限定することなく使用できるが、好ましくは、エポキシ基１モルに対して、０．０１〜５．０当量の範囲で、特に好ましくは０．８〜１．２当量の範囲で使用する。
また、エポキシ樹脂組成物には、必要に応じて硬化促進剤を配合してもよい。代表的な硬化促進剤として、第三級アミン、イミダゾール類、第四級アンモニウム塩等があるが、これに限定されるものではない。
エポキシ樹脂組成物の硬化反応は、反応が進行するのであればどのような温度で行ってもよいが、一般には室温〜２５０℃の範囲で硬化させることが好ましい。またこの硬化反応は、加圧下、大気圧下又は減圧下に行うことができる。
絶縁基材にポリアミドイミド樹脂を用いる場合には、シリコーン変性ポリアミドイミドを用いるのが好ましい。このシリコーン変性ポリアミドイミドは、シロキサン結合、イミド結合及びアミド結合を有する重合体であり、その製造方法には、
（１）シロキサン結合を有するジイミドジカルボン酸を含むジイミドジカルボン酸１ａとジイソシアネート化合物１ｂとを反応させる方法、
（２）シロキサン結合を有するジアミンを含むジアミン化合物２ａとトリカルボン酸クロライド２ｂとを反応させる方法、
（３）シロキサン結合を有するジイソシアネートを含むジイソシアネート化合物３ａとトリカルボン酸無水物３ｂとを反応させる方法、
の３つの方法がある。
上記（１）の方法により得られるシリコーン変性ポリアミドイミドについて詳述すると、シロキサン結合を有するジイミドジカルボン酸１ａを含むジイミドジカルボン酸として、例えば、次の化合物がある。
シロキサン結合を有するジイミドジカルボン酸以外のジイミドジカルボン酸のうちイミド基を連結する２価の残基が芳香族であるジイミドジカルボン酸の例としては、つぎの（１式）及び（２式）のものが挙げられる。

Figure 2003021668
また、シロキサン結合を有するジイミドジカルボン酸の例として、１式においてＲ１が２価の脂肪族基（酸素を含んでいてもよい）のものがある。２価の脂肪族基としては、プロピレン基、ヘキサメチレン基、オクタメチレン基、デカメチレン基、オクタデカメチレン基等のアルキレン基、アルキレン基の両端に酸素が結合した基などがある。
Figure 2003021668
上記の２価の有機基Ｒ１及びＲ２としては、プロピレン基等のアルキレン基、フェニレン基、アルキル基置換フェニレン基等が挙げられる。
また、ジイソシアネート化合物１ａとしては、芳香族ジイソシアネート化合物として、つぎの（３式）のものが挙げられる。
Figure 2003021668
また、Ｒ９としては、アルキレン基等の２価の脂肪族基又はシクロアルキレン基等の２価の脂環式基がある脂肪族ジイソシアネート化合物又は脂環式ジイソシアネート化合物がある。
シロキサン結合を有するジイミドジカルボン酸及びそれ以外のジイミドジカルボン酸は、それぞれ、シロキサン結合を有するジアミン化合物及びこれ以外のジアミンと無水トリメリット酸を反応させて得ることができる。
シロキサン結合を有するジイミドジカルボン酸及びそれ以外のジイミドジカルボン酸は混合物として使用することが好ましい。
シロキサン結合を有するジアミン化合物及びこれ以外のジアミンの混合物と無水トリメリット酸を反応させて得られるジイミドジカルボン酸混合物を使用することが特に好ましい。
シロキサン結合を有するジアミン化合物以外のジアミンとしては、芳香族ジアミンが好ましく、特に、芳香族環を３個以上有するジアミンが好ましい。シロキサン結合を有するジアミン化合物以外のジアミンのうち芳香族ジアミンが５０〜１００モル％になるように使用することが好ましい。
また、（Ａ）シロキサン結合を有するジアミン化合物以外のジアミン及び（Ｂ）シロキサンジアミンは（Ａ）／（Ｂ）が９９．９／０．１〜０．１／９９．９モル比）となるように使用することが好ましい。さらに、（Ａ）シロキサン結合を有するジアミン化合物以外のジアミン及び（Ｂ）シロキサンジアミンと無水トリメリット酸は、（Ａ）＋（Ｂ）の合計１モルに対して無水トリメリット酸２．０５〜２．２０の割合で反応させることが好ましい。
ジイソシアネート化合物としては、芳香族ジイソシアネート化合物が好ましく、ジイソシアネート化合物のうち芳香族ジイソシアネート化合物を５０〜１００モル％使用することが好ましい。
ジイミドジカルボン酸全体とジイソシアネート化合物とは前者１モルに対して後者１．０５〜１．５０モルになるように反応させることが好ましい。
ジアミン化合物と無水トリメリット酸とは、非プロトン性極性溶媒の存在下に、５０〜９０℃で反応させ、さらに水と共沸可能な芳香族炭化水素を非プロトン性極性溶媒の０．１〜０．５重量比で投入し、１２０〜１８０℃で反応を行い、イミドジカルボン酸とシロキサンジイミドジカルボン酸を含む混合物を製造し、これとジイソシアネート化合物との反応を行うことが好ましい。ジイミドジカルボン酸を製造した後、その溶液から芳香族炭化水素を除去することが好ましい。
イミドジカルボン酸とジイソシアネート化合物との反応温度は、低いと反応時間が長くなることや、高すぎるとイソシアネート同士で反応するのでこれらを防止するため、１００〜２００℃で反応させることが好ましい。
芳香族ジアミンとしては、フェニレンジアミン、ビス（４−アミノフェニル）メタン、２，２−ビス（４−アミノフェニル）プロパン、ビス（４−アミノフェニル）カルボニル、ビス（４−アミノフェニル）スルホン、ビス（４−アミノフェニル）エーテル等があり、特に、芳香族環を３個以上有するジアミンとしては、２，２−ビス［４−（４−アミノフェノキシ）フェニル］プロパン（以下、ＢＡＰＰと略す）、ビス［４−（３−アミノフェノキシ）フェニル］スルホン、ビス［４−（４−アミノフェノキシ）フェニル］スルホン、２，２−ビス［４−（４−アミノフェノキシ）フェニル］ヘキサフルオロプロパン、ビス［４−（４−アミノフェノキシ）フェニル］メタン、４，４’−ビス（４−アミノフェノキシ）ビフェニル、ビス［４−（４−アミノフェノキシ）フェニル］エーテル、ビス［４−（４−アミノフェノキシ）フェニル］ケトン、１，３−ビス（４−アミノフェノキシ）ベンゼン等がある。
脂肪族ジアミンとしては、ヘキサメチレンジアミン、オクタメチレンジアミン、デカメチレンジアミン、オクタデカメチレンジアミン、末端アミノ化プロピレングリコール等がある。また、脂環式ジアミンとしては、１，４−ジアミノシクロヘキサン等がある。
シロキサンジアミンとしてはつぎの一般式（４式）で表されるものを用いることができる。
Figure 2003021668
このようなシロキサンジアミンとしては（５式）で示すものが挙げられる。これらの中でもジメチルシロキサン系両末端アミンであるアミノ変性反応性シリコーンオイルＸ−２２−１６１ＡＳ（アミン当量４５０）、Ｘ−２２−１６１Ａ（アミン当量８４０）、Ｘ−２２−１６１Ｂ（アミン当量１５００）、以上信越化学工業株式会社製商品名、ＢＹ１６−８５３（アミン当量６５０）、ＢＹ１６−８５３Ｂ（アミン当量２２００）以上東レダウコーニングシリコーン株式会社製商品名などが市販品として挙げられる。
Figure 2003021668
芳香族ジイソシアネートとして具体的には、４，４’−ジフェニルメタンジイソシアネート（以下ＭＤＩと略す）、２，４−トリレンジイソシアネート、２，６−トリレンジイソシアネート、ナフタレン−１，５−ジイソシアネート、２，４−トリレンダイマー等が例示できる。特にＭＤＩは、分子構造においてイソシアネート基が離れており、ポリアミドイミドの分子中におけるアミド基やイミド基の濃度が相対的に低くなり、溶解性が向上するため好ましい。
脂肪族又は脂環式ジイソシアネートとしては、ヘキサメチレンジイソシアネート、イソホロンジイソシアネート、メチレンビス（シクロヘキシルジイソシアネート）等がある。
非プロトン性極性溶媒として、ジメチルアセトアミド、ジメチルホルムアミド、ジメチルスルホキシド、Ｎ−メチル−２−ピロリドン、４−ブチロラクトン、スルホラン、シクロヘキサノン等が例示できる。イミド化反応には、高温を要するため沸点の高い、Ｎ−メチル−２−メチルピロリドン（以下ＮＭＰと略す）が、特に好ましい。これらの混合溶媒中に含まれる水分量はＴＭＡが水和して生成するトリメリット酸により、充分に反応が進行せず、ポリマの分子量低下の原因になるため０．２重量％以下で管理されていることが好ましい。また、非プロトン性極性溶媒は、特に制限されないが、芳香族環を３個以上有するジアミンとシロキサンジアミン及び無水トリメリット酸を合わせた重量の割合が、多いと無水トリメリット酸の溶解性が低下し充分な反応が行えなくなることや、低いと工業的製造法として不利であることから、１０重量％〜７０重量％の範囲になることが好ましい。
水と共沸可能な芳香族炭化水素として、ベンゼン、キシレン、エチルベンゼン、トルエン等の芳香族炭化水素が例示でき、特に沸点が比較的低く、作業環境上有害性の少ないトルエンが好ましく、使用量は、非プロトン性極性溶媒の０．１〜０．５重量比（１０〜５０重量％）の範囲が好ましい。
つぎに、前記（２）の方法により得られるシリコーン変性ポリアミドイミドについて説明すると、シロキサン結合を有するジアミンを含むジアミン化合物２ａとして、シロキサン結合を有するジアミン、前記（５式）で示される化合物がある。また、その他のジアミンとして、上述したジアミンも使用できる。
トリカルボン酸クロライド２ｂには、トリメリット酸クロライド等があり、良く知られた酸クロライド法により製造することができる。
つぎに、前記（３）の方法により得られるシリコーン変性ポリアミドイミドについて説明すると、３ａシロキサン結合を有するジイソシアネートを含むジイソシアネート化合物として、シロキサン結合を有するジイソシアネート化合物、前記（４式）で示されるシロキサンジアミンに対応するジイソシアネート化合物、その他のジイソシアネート化合物として、前記したものを使用することができる。
トリカルボン酸無水物３ｂには、無水トリメリット酸等があり、従来から良く知られたジアミン化合物とジイソシアネート化合物の反応により製造することができる。
また、絶縁基材として、ウィスカを含む樹脂組成物を用いてもよい。特に樹脂が単独でフィルム形成能を有しない場合、ウィスカを配合することが有効である。なお、ここでいうフィルム形成能とは、ワニスをキャリアフィルムに塗工するときに、所定の厚さに制御することが容易であり、加熱乾燥して半硬化状にした後の搬送、切断における作業性が良好であって、積層工程に用いた場合に樹脂の割れや欠落を生じにくく、その後の加熱加圧成形時に層間絶縁層の最小厚さを確保できることを言う。フィルム形成能を有しない樹脂は、通常、分子量が３０，０００を越えない程度の低分子量であることが多い。
具体的には、ガラスクロス基材に含浸させた熱硬化性樹脂が絶縁基材として好ましく、熱硬化性樹脂としては、例えば、エポキシ樹脂、ビストリアジン樹脂、ポリイミド樹脂、フェノール樹脂、メラミン樹脂、珪素樹脂、不飽和ポリエステル樹脂、シアン酸エステル樹脂、イソシアネート樹脂、又はこれらの変性樹脂等を使用することができる。
この中で、積層板の特性を向上する上で、特にエポキシ樹脂、ポリイミド樹脂、又はビストリアジン樹脂は好適である。
さらには、エポキシ樹脂としては、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡノボラック型エポキシ樹脂、サリチルアルデヒドノボラック型エポキシ樹脂、ビスフェノールＦノボラック型エポキシ樹脂、脂環式エポキシ樹脂、グリシジルエステル型エポキシ樹脂、グリシジルアミン型エポキシ樹脂、ヒダントイン型エポキシ樹脂、イソシアヌレート型エポキシ樹脂、脂肪族環状エポキシ樹脂、及び、これらのハロゲン化物、水素添加物、から選択された１以上のものを使用することができる。なかでも、ビスフェノールＡノボラック型エポキシ樹脂と、サリチルアルデヒドノボラック型エポキシ樹脂は、耐熱性に優れ好ましい。
絶縁基材を構成する樹脂組成物に配合するウィスカは、電気絶縁性セラミック系ウィスカであり、弾性率が２００ＧＰａ以上であることが好ましい。２００ＧＰａ未満では、配線板材料あるいは配線板として用いたときに十分な剛性が得られない場合がある。
このようなものとして、例えば、硼酸アルミニウム、ウォラストナイト、チタン酸カリウム、塩基性硫酸マグネシウム、窒化ケイ素及びα−アルミナの中から選ばれた１以上のものを用いることができる。なかでも、硼酸アルミニウムウィスカと、チタン酸カリウムウィスカは、モース硬度が、一般的なプリプレグ基材に用いるＥガラスとほぼ同等であり、従来のプリプレグと同様のドリル加工性を得ることができる。硼酸アルミニウムウィスカは、弾性率がほぼ４００ＧＰａと高く、樹脂ワニスと混合し易く、さらに好ましい。
このウィスカの平均直径は、０．３μｍ〜３μｍであることが好ましく、さらには、０．５μｍ〜１μｍの範囲がさらに好ましい。このウィスカの平均直径が、０．３μｍ以下であると、樹脂ワニスへの混合が困難となり、３μｍを越えると、微視的な樹脂への分散が十分でなく、表面の凹凸が大きくなり好ましくない。
また、この平均直径と平均長さの比は、１０以上であることが、さらに剛性を高めることができるため好ましく、２０以上であればさらに好ましい。この比が１０未満であると、繊維としての補強効果が小さくなる。この平均長さの上限は、１００μｍであり、さらに好ましくは５０μｍである。この上限を越えると、樹脂ワニス中への分散が困難となる他、２つの導体回路に１つのウィスカが接触する確率が高くなり、ウィスカの繊維に沿って銅イオンのマイグレーションが発生する確率が高くなる。
また、配線基板の剛性、耐熱性及び耐湿性を高めるために、樹脂との濡れ性や結合性に優れたカップリング剤で表面処理した電気絶縁性のウィスカを使用することが好ましく、このようなカップリング剤として、シリコン系カップリング剤、チタン系カップリング剤、アルミニウム系カップリング剤、ジルコニウム系カップリング剤、ジルコアルミニウム系カップリング剤、クロム系カップリング剤、ボロン系カップリング剤、リン系カップリング剤、アミノ酸系カップリング剤等から選択して使用することができる。
このような樹脂の硬化剤としては、従来使用しているものが使用でき、樹脂がエポキシ樹脂の場合、例えば、ジシアンジアミド、ビスフェノールＡ，ビスフェノールＦ、ポリビニルフェノール、ノボラック樹脂、ビスフェノールＡノボラック樹脂、並びにこれらのフェノール樹脂のハロゲン化物等を使用できる。なかでも、ビスフェノールＡノボラック樹脂は、耐熱性に優れ好ましい。
この硬化剤の前記樹脂に対する割合は、従来使用している割合でよく、樹脂１００重量部に対して、２〜１００重量部の範囲が好ましく、さらには、ジシアンジアミドでは、２〜５重量部、それ以外の硬化剤では、３０〜８０重量部の範囲が好ましい。
硬化促進剤としては、樹脂がエポキシ樹脂の場合、イミダゾール化合物、有機リン化合物、第３級アミン、第４級アンモニウム塩等を用いることができる。
この硬化促進剤の前記樹脂に対する割合は、従来使用している割合でよく、樹脂１００重量部に対して、０．０１〜２０重量部の範囲が好ましく、０．１〜１．０の範囲がより好ましい。
これらは、溶剤に希釈して用い、この溶剤には、アセトン、メチルエチルケトン、トルエン、キシレン、メチルイソブチレン、酢酸エチル、エチレングリコールモノメチルエーテル、メタノール、エタノール、Ｎ，Ｎ−ジメチルホルムアミド、Ｎ，Ｎ−ジメチルアセトアミド等を使用できる。
この希釈剤の前記樹脂に対する割合は、従来使用している割合でよく、樹脂１００重量部に対して、１〜２００重量部の範囲が好ましく、３０〜１００重量部の範囲がさらに好ましい。
熱硬化性樹脂とウィスカの割合は、硬化した樹脂中のウィスカの体積分率が５％〜５０％の範囲となるように調整することが好ましい。硬化した樹脂中のウィスカの体積分率が５％未満であると、銅箔付プリプレグ（銅箔／熱硬化性樹脂層）が切断時に樹脂が細かく砕けて飛散するなど、取扱いが著しく困難な場合があり、配線板としたときに剛性が低くなる。一方ウィスカの体積分率が５０％を越えると、加熱加圧成形時の穴や回路間隙への埋め込みが不十分となり、成形後にボイドやかすれを発生し、絶縁性が低下する場合がある。また、樹脂とウィスカの割合は、硬化した樹脂中のウィスカの体積分率は、２０〜４０％であることが、さらに好ましい。
本発明に用いられる絶縁基材は、例えば、樹脂と溶剤からなるワニスにウィスカを混合し、撹拌によりウィスカをワニス中に均一に分散させ、それを銅箔などの支持部材の片面に塗工し、加熱乾燥により溶剤を除去するとともに樹脂を半硬化状にして形成できる。
支持部材に上述の樹脂組成物を塗布して絶縁基材を形成する場合、樹脂組成物の塗布方法は特に限定されるものではないが、例えば、ブレードコータ、ロッドコータ、ナイフコータ、スクイズコータ、リバースロールコータ、トランスファロールコータ等の支持部材（例えば銅箔）と平行な面方向にせん断力を負荷できるか、又は、銅箔の面に垂直な方向に圧縮力を負荷できる塗布方法を採用することができる。
本発明の配線基板では、絶縁基材の導体部材が露出していない面に支持部材を設けることができる。ここで用いられる支持部材は、ある程度の剛性があれば、その材質は特に限定されるものではないが、例えば、金属、樹脂及びセラミックのうちの少なくともいずれかを含むことができる。本発明における支持部材としては、特に金属板又はプラスチック板が好適である。
金属板としては、銅板、鉄板、アルミニウム板やそれらの金属の合金板が経済的に好ましい。また、プラスチック板としては、熱硬化性樹脂板、熱可塑性樹脂板などを用いることができる。
ここで熱硬化性樹脂には、フェノール樹脂、尿素樹脂、メラミン樹脂、アルキド樹脂、アクリル樹脂、不飽和ポリエステル樹脂、ジアリルフタレート樹脂、エポキシ樹脂、シリコーン樹脂、シクロペンタジエンから合成した樹脂、トリス（２−ヒドロキシエチル）イソシアヌラートを含む樹脂、芳香族ニトリルから合成した樹脂、３量化芳香族ジシアナミド樹脂、トリアリルトリメタクリレートを含む樹脂、フラン樹脂、ケトン樹脂、キシレン樹脂、縮合多環芳香族を含む熱硬化性樹脂などを用いることができる。
熱可塑性樹脂としては、ポリエチレン、ポリプロピレンや、４−メチルペンテン−１樹脂、ポリブテン−１樹脂、及び高圧法エチレンコポリマーなどのポリオレフィン樹脂、スチレン系樹脂、ポリ塩化ビニル、ポリ塩化ビニリデン、ポリビニルアルコール、ポリアクリロニトリル、ポリアクリル酸系プラスチック、ジエン系プラスチック、ポリアミド、ポリエステル、ポリカーボネート、ポリアセタール、フッ素系樹脂、ポリウレタン系プラスチック、及び、ポリスチレン系熱可塑性エラストマ、ポリオレフィン系熱可塑性エラストマ、ポリウレタン系熱可塑性エラストマ、ポリエステル系熱可塑性エラストマ、ポリアミド系熱可塑性エラストマ、低結晶性１，２−ポリブタジエン、塩素化ポリマ系熱可塑性エラストマ、フッ素系熱可塑性エラストマ、あるいはイオン架橋熱可塑性エラストマなどの熱可塑性エラストマなどを用いることができる。
さらに、これらの樹脂を、ガラスファイバやセルロースなどの絶縁性のファイバで織った布、織ってない紙に含浸したもの、ガラスチョップトストランドや絶縁性ウィスカなどの短繊維を混合したもの、又は、フィルム状に成型したものを、支持部材として用いてもよい。
本発明における配線部材は、１層の配線層のみからなっていてもよく、複数の配線層と、該配線層間を絶縁するための層間絶縁層と、層間絶縁層内に設けられた、配線層間を接続するためのバイアホールとを備える多層配線構造体であってもよい。配線層は、複数の回路を備えることができ、通常、銅箔等の導体膜をエッチング等によりパターン化して形成することができる。また、配線部材として多層配線構造体を形成する場合、その形成方法は特に限定されるものでなく、配線層の形成、層間絶縁層の形成及びバイアホールの形成を所定回数繰り返すといった、通常の薄膜プロセスを用いることができる。なお、配線層の形成は、例えば、配線層となる導体層の表面に所定のパターンの金めっき層を形成した後、この金めっき層をエッチングレジストとして導体層をエッチングしてパターン化することによって行ってもよい。
本発明の配線基板では、導体部材が絶縁基材に埋め込まれている。導体部材の厚さは、０．０１ｍｍ〜０．１５ｍｍであることが好ましく、絶縁基材の厚さと導体部材の厚さとの差は、０ｍｍより大きく０．１ｍｍ以下であることが好ましい。導体部材の厚さが０．０１ｍｍ未満では、これに半導体素子を搭載して最終的に得られる半導体装置における絶縁基材の厚さが十分な絶縁性が得られる程厚くできない場合があり、０．１５ｍｍより厚いと、導体部材の形成精度が十分でない場合がある。また、絶縁基材の厚さと導体部材の厚さとの差は、導体部材の一端が絶縁基材に被覆される程度であれば足り、０．１ｍｍを超えると、導体部材を露出させるための研磨量が大きすぎて工業的な生産効率を悪化させる場合がある。なお、絶縁基材裏面に支持部材が設けられている場合には、導体部材と絶縁基材の厚さが同じ（すなわち、導体部材が絶縁基材を貫通している状態）であってもよい。
導体部材が絶縁基材内に埋め込まれている本発明の配線基板では、絶縁基材が比較的厚い状態で半導体素子の搭載等の工程に供することができることから、それらの工程や搬送時等に附加される応力等に耐える十分な強度を得ることができる。特に、絶縁基材裏面（表裏のうち配線部材が設けられていない側の面）に支持部材を設ければ、強度が増すため好ましい。絶縁基材裏面に支持部材が設けられている本発明の配線基板を用いれば、配線部材や絶縁基材が薄くても、それらの工程や搬送時等に附加される応力等に耐える十分な強度を得ることができる。
さらに本発明の配線基板によれば、素子搭載後に絶縁基材の一部を除去し、導体部材を露出させて外部電極とすることから、最終的に得られる半導体装置における絶縁基材の厚さを薄くすることができ、パッケージの小型化に資することができる。
また、本発明の配線基板を用いて半導体装置を作製する場合、絶縁基材から端部を露出させた導体部材を外部電極として用いるため、この外部電極端部に、配線を露出させることなくバンプを形成することができる。
本発明の配線基板は、表裏一方の面に突起状の導体部材を設けた配線部材と、絶縁基材とを、導体部材を内側にして対向させて積層させる積層工程を備える配線基板の製造方法によって作製することができる。また、本発明の配線基板は、表裏一方の面に突起状の導体部材を設けた導体層と、絶縁基材とを、導体部材を内側にして対向させて積層させる積層工程、及び、導体層の不要な箇所を除去して配線層を形成する配線層形成工程を備える配線基板の製造方法によって作製することができる。
絶縁基材と配線部材との接着は、例えば、熱硬化性樹脂組成物からなる硬化前の接着剤を絶縁基材として用い、これを配線部材に重ね合わせて加熱加圧して硬化させるといった手法をとることができる。絶縁基材として用いる硬化前の接着剤に自己支持性がない場合には、支持部材表面に硬化前の接着剤を成膜して、これを絶縁基材とすればよい。この場合には、支持部材、絶縁基材、配線部材がこの順で積層され、絶縁基材中に導体部材が埋め込まれた配線基板が得られる。
なお、配線基板に支持部材が設けられている場合には、積層工程を、配線層／導体層の導体部材が設けられた面と、絶縁基材の支持部材が設けられていない面とを対向させて積層させる工程とすればよい。
また、配線層／導体層が薄すぎて自己支持性がない場合などには、配線層／導体層の他方の面（すなわち導体部材が設けられていない面）に仮支持板を設けてもよい。このようにする場合、本発明の配線基板製造方法は、積層工程の後に、仮支持板を除去する工程をさらに備えることが望ましい。
本発明における導体部材は、配線層／導体層表面に設けられた突起状部材である。この導体部材は、めっきにより形成してもよく、導体膜の一部を除去することにより形成してもよい。
また、本発明の配線基板製造方法は、導体板の一部を除去することにより配線層及び／又は導体部材を形成するエッチング工程を、さらに備えていてもよい。この場合、導体板としては、この順で積層された第１の導体層、第２の導体層及び第３の導体層からなる積層板を用いることができる。このような３層積層板を用いる場合、エッチング工程は、第１の導体層の一部をエッチングして配線層を形成する配線層形成工程と、第３の導体層の一部をエッチングして導体部材を形成する導体部材形成工程と、第２の導体層の露出箇所をエッチング除去するエッチングバリア除去工程とを備えることが望ましい。ここで配線層形成工程は、第１の導体層表面に金めっきパターンを形成し、該めっきパターンをエッチングレジストとして上記第１の導体層をエッチングすることにより配線層を形成する工程とすることができる。
また、本発明の配線基板製造方法は、導体板の一部を除去することにより導体部材を形成する導体部材形成工程を、さらに備えていてもよい。この場合、導体板としては、この順で積層された第１の導体層、第２の導体層及び第３の導体層からなる積層板を用いることができる。このような３層積層板を用いる場合、導体部材形成工程は、第３の導体層の一部をエッチングして上記導体部材を形成する工程と、第２の導体層の露出箇所をエッチング除去する工程とを備えることが望ましい。
本発明の配線基板は、半導体素子を搭載して樹脂封止型半導体装置を製造するのに特に適している。そこで本発明では、上述した本発明の配線基板の配線層表面に半導体素子を搭載する搭載工程、半導体素子と配線層表面の配線とを電気的に接続する接続工程、及び、絶縁基材の一部を除去して上記導体部材の少なくとも一部を露出させる絶縁基材除去工程を備える半導体装置の製造方法、並びに、該方法により製造された半導体装置が提供される。本発明の製造方法により作製された半導体装置では、導体部材は半導体装置の外部電極（外部接続端子）として機能する。
なお、配線基板が支持部材を備える場合、上述した本発明の半導体装置の製造方法は、支持部材の少なくとも一部を除去して絶縁基材の少なくとも一部を露出させる支持部材除去工程をさらに備えることが望ましい。この支持部材除去工程における上記支持部材の除去は、例えば、研磨、化学エッチング及び機械加工の少なくともいずれかにより行うことができる。
また、絶縁基材除去工程における上記絶縁基材の除去は、研磨、レーザ照射及びエッチングの少なくともいずれかにより行うことができる。
絶縁基材の除去によって少なくとも一部が露出した導体部材は、外部電極として機能する。このため、絶縁基材除去工程の後に、導体部材の露出箇所に、金めっき層を形成する工程、及び／又は、導体部材の露出箇所に、はんだボールを形成する工程をさらに設けてもよい。金めっき層を形成する場合、その下地としてニッケルめっきを行ってもよい。
本発明では、一つの配線基板に複数の半導体素子を搭載してもよく、半導体素子のほかに受動部品をさらに搭載してもよい。半導体素子と配線層の配線との接続は、ワイヤボンディングによって行ってもよく、また、素子のバンプを直接配線に接続するフリップ素子接続により行ってもよい。
本発明の半導体装置の製造方法は、半導体素子を封止部材により覆って封止する封止工程をさらに備えることが望ましい。この場合、封止部材を研磨して半導体素子の少なくとも一部（例えば背面）を露出させる工程をさらに備えることが望ましい。このように半導体素子の一部が露出していれば、放熱特性に優れる半導体装置が得られる。
本発明の半導体装置は、具体的には、例えばつぎのようにして得ることができる。すなわち、まず、支持部材である金属板に、将来外部電極となる柱状の導体部材を形成した導体層（例えば金属層）を、導体部材が支持部材に接するように重ねて、絶縁基材である接着性樹脂を介して貼り合わせる。次に、金属層の不要部分を除去して複数の回路を含む配線層からなる配線部材を形成する。これにより、本発明の半導体素子搭載用配線基板が得られる。なお、層間絶縁層を介しながら配線層を複数積層して、配線部材が多層配線を含むようにしてもよい。続いて、得られた配線基板に半導体素子を搭載し、配線層の回路に半導体素子を電気的に接続した後、半導体素子を樹脂封止（モールド封止）し、支持部材を除去することにより、樹脂封止型半導体装置が得られる。
また、外部電極となる柱状の導体部材を、比較的厚い金属層の片面から、導体部材となる箇所以外の箇所を厚さ方向に部分的にエッチング除去して導体部材を形成した後、この導体部材を形成した金属層と支持部材とを、導体部材が支持部材に接するようにして重ね合わせ、絶縁基材である接着性樹脂を介して貼り合わせ、導体部材を形成した金属層のエッチングされずに残っている厚さ部分の金属層の不要箇所をエッチング除去して配線層からなる配線部材を形成することにより、本発明の半導体素子搭載用配線基板を得ることもできる。上述の場合と同様、得られた配線基板に半導体素子を搭載し、配線層の回路に半導体素子を電気的に接続した後、半導体素子を樹脂封止（モールド封止）し、支持部材を除去することにより、樹脂封止型半導体装置が得られる。
この方法の場合、上述の比較的厚い金属層として、配線層となる第１の導体層と、導体部材となる第３の導体層と、第１及び第３の導体層とはエッチング条件の異なる第２の導体層とを、第１の導体層／第２の導体層／第３の導体層の順に積層した積層膜を用いることもできる。すなわち、この３層積層膜の第３の導体層の不要箇所を除去して、外部電極となる柱状の導体部材を形成し、これによって露出した第２の導体層をエッチング除去した後、この導体部材を形成した３層積層膜と支持部材とを、導体部材が支持部材に接するように重ね、絶縁基材である接着性樹脂を介して貼り合わせ、第１の導体層の不要箇所を除去して複数の回路を含む配線層からなる配線部材を形成することにより、本発明の半導体素子搭載用配線基板を得ることができる。上述の場合と同様、得られた配線基板に半導体素子を搭載し、配線層の回路に半導体素子を電気的に接続した後、半導体素子を樹脂封止（モールド封止）し、支持部材を除去することにより、樹脂封止型半導体装置が得られる。
このように、支持部材を備える配線基板を用いて半導体装置を作製する場合には、通常、素子搭載後に支持部材を除去した後、絶縁基材の表面を研磨すれば、導体部材端部を容易に露出させることができる。また、支持部材を除去した後、埋包された導体部材にレーザを照射してその一部を露出させるようにしてもよい。
本発明では、導体部材を備えない本発明の配線基板を用いて半導体装置を製造することもできる。すなわち、配線部材と絶縁基材と支持部材とがこの順で積層されてなる配線基板を用い、その配線基板上に半導体素子を搭載し、半導体素子と配線部材表面の配線とを電気的に接続し、支持部材の少なくとも一部を除去して絶縁基材の少なくとも一部を露出させ、絶縁基材の少なくとも一部を除去し貫通孔を形成して配線の少なくとも一部を露出させ、当該貫通孔を導体で充填して配線に接続した導体部材を形成することにより半導体装置を得ることができる。
なお、貫通孔の形成は、研磨、エッチング、レーザ加工などどのような方法により行っても構わない。例えばレーザを照射して貫通孔をあける場合にも、レーザの種類は特に限定されるものではなく、炭酸ガスレーザ、ＵＶ−ＹＡＧレーザ等を適宜用いることができる。
孔あけ条件は、絶縁基材及び配線層の厚さ及び材質により適宜調整すればよく、実験的に求めるのが好ましい。照射するレーザのエネルギー量としては、０．００１Ｗ〜１Ｗの範囲内であって、レーザ発振用の電源をパルス状に印加し、一度に大量のエネルギーが集中しないよう制御することが望ましい。
なお、レーザは、配線部材の配線に達する貫通孔をあけ、しかも孔径をできるだけ小さくするために、レーザ発振用の電源を駆動するパルス波形デューティー比で１／１０００〜１／１０の範囲で、１〜２０ショット（パルス）照射することが好ましい。波形デューティー比が１／１０００未満であると孔をあけるのに時間がかかりすぎ効率的でなく、１／１０を越えると照射エネルギーが大きすぎて穴径が１ｍｍ以上に大きくなり実用的でない場合がある。ショット（パルス）数は、穴内の接着剤が内層回路に達するところまで蒸発できるようにする数を実験的に求めればよく、１ショット未満では穴があけられず、２０ショットを越えると、１ショットのパルスの波形デューティー比が１／１０００近くであっても穴径が大きくなり実用的でない場合がある。
このようにして貫通孔を形成した後、貫通孔内の接着剤のかすを除去するためにデスミア処理を行うことが望ましい。このデスミア処理は、一般的な酸性の酸化性粗化液やアルカリ性の酸化性粗化液を用いることができる。例えば、酸性の酸化性粗化液としては、クロム／硫酸粗化液があり、アルカリ性の酸化粗化液は過マンガン酸カリウム粗化液等を用いることができる。
また、接着剤を酸化性の粗化液で粗化した後、絶縁樹脂表面の酸化性粗化液を化学的に中和することが望ましいが、これも一般的な手法を取り入れることができる。例えば、クロム／硫酸粗化液を用いたときには、亜硫酸水素ナトリウム１０ｇ／ｌを用いて室温で５分間処理し、また、過マンガン酸カリウム粗化液を用いたときには、硫酸１５０ｍｌ／ｌと過酸化水素水１５ｍｌ／ｌの水溶液に室温で５分間浸漬して中和を完了させるなどである。
実施例
＜実施例１＞
本実施例では、図１ａ〜図１ｇに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔の表裏一方の面に０．００１ｍｍの厚さのニッケル層（図示せず）をめっきした後、その表面に厚さ０．００９ｍｍの銅膜をめっきした。次に、電解銅箔の他方の面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、バンプのパターンを形成し、電解銅箔をアルカリエッチャントでエッチングして高さ０．０３５ｍｍのバンプ（導体部材）３を形成した後、レジストを剥離し、露出したニッケル層を銅のエッチング速度が遅いニッケルエッチング液により除去した。
続いて、得られたバンプ３付き銅膜と、支持部材である厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、絶縁基材である厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）を介して、バンプ３が接着剤２に埋め込まれるようにプレスラミネートした。
次に、銅メッキ膜に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線めっき用のレジストパターンを形成した後、これに厚さ０．００３ｍｍ以上のニッケル（図示せず）と、厚さ０．０００３ｍｍ以上の純度９９．９％以上の金（図示せず）とをめっきし、アルカリエッチャントで銅をエッチングして配線パターンからなる配線層である配線部材４を得た。これにより、図１ａに示す配線基板１１０が得られた。
続いて、バンプ３を内蔵した配線４を有する配線基板１１０上に、ＬＳＩ（大規模集積回路）素子６を、半導体用の非導電性の接着剤フィルム（ダイボンド材）５を用いて搭載した後（図１ｂ）、ＬＳＩ素子の端子と配線端子４とをワイヤ１００により接続した（図１ｃ）。
このようにして形成した組立体を、トランスファモールド金型にセットして半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止し、金属シート１をエッチングして除去して接着剤２の表面を露出させた後（図１ｅ）、接着剤表面を研磨して、バンプの頂上を露出させた（図１ｆ）。
最後に、露出したバンプの頂部にはんだボール８を配置しリフローし、図１ｇに示す樹脂封止型半導体装置１２０を得た。はんだボール８は、ＬＳＩ素子６の内側に配置されるファンインタイプである。得られた半導体装置１２０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例２＞
本実施例では、図２ａ〜図２ｆに示すようにして、樹脂封止型半導体装置を作製した。
実施例１と同様にして、金属支持部材１と配線４とバンプ３とを備える配線基板１１０を作製し（図２ａ）、この基板１１０の配線４上に、端子部に金バンプ２００を備えるＬＳＩ素子６を搭載して、金バンプ２００と配線４とを、熱圧着により相互接続させた後（図２ｂ）、ＬＳＩ素子６と配線基板との間に、液状エポキシ樹脂（アンダーフィル材）１１をフィルして硬化させた（図２ｃ）。
このようにして作製された組立て体をトランスファモールド金型に装着し、半導体封止エポキシ樹脂７（日立化成工業（株）製ＣＥＬ４００）で封止した後（図２ｄ）、金属支持部材である金属シート１のみを酸系エッチング液で除去し、接着剤２を露出させた。
続いて、絶縁基材である接着剤層２を、バンプ３の頂上が露出するように機械的に研磨した後（図２ｅ）、はんだボール８をバンプ３の頂上に配置して、その位置に再溶融し、図２ｆに示す樹脂封止型半導体装置１３０を得た。得られた半導体装置１３０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例３＞
本実施例では、図３ａ〜図３ｆに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０２０ｍｍの電解銅箔の片面に、厚さ０．００１ｍｍのニッケル層（図示せず）をめっきにより成膜し、このニッケル層表面に、厚さ０．０１２ｍｍの銅層をめっきにより成膜した。次に、電解銅箔の他方の面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、バンプ３のエッチングパターンを形成した後、アルカリエッチング液でエッチングして、導体部材であるバンプ３（高さ０．０２０ｍｍ）を形成した。
続いて、得られたバンプ３付き銅膜と、厚さ０．１００ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、絶縁基材である厚さ０．０３０ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）を介して、バンプ３が接着剤２に埋まるようにプレス積層した。
次に、銅膜表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線４のエッチングパターンを形成した後、アルカリエッチング液でエッチングして、配線４を形成した。続いて、レジストを除去し、ニッケル選択エッチング液によってニッケル層を除去した。
次に、配線４上に液状コーティング樹脂をスクリーン印刷法によって塗布して、配線４の接続部位を露出させるように絶縁層（ソルダレジスト）１０を形成した後、配線４の露出箇所に、０．００３ｍｍ以上のニッケル膜（図示せず）と、純度９９．９％以上、厚さ０．０００３ｍｍ以上の金膜（図示せず）とを順次めっきにより積層した。これにより、図３ａに示す配線基板３００が得られた。
続いて、得られた配線基板３００の絶縁層１０表面に、半導体用銀ペースト５を用いてＬＳＩ素子６を搭載し（図３ｂ）、ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図３ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止した（図３ｄ）。その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ（図３ｅ）、露出した接着剤２表面を研磨して、バンプ３の頂上を露出させた。
最後に、はんだボール８をバンプ３の頂上に配置してリフローし、図３ｆに示す樹脂封止型半導体装置３１０を得た。得られた半導体装置３１０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例４＞
本実施例では、図４ａ〜図４ｇに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔の片面に、厚さ０．００１ｍｍのニッケル層（図示せず）をめっきし、このニッケル層表面に厚さ０．００９ｍｍの銅膜をめっきした。次に、電解銅箔の他方の面に感光性ドライフィルムレジスト（フォテックＲＹ−３０２５、日立化成工業（株）製）をラミネートし、露光して現像し、バンプ３のエッチングパターンを形成した。続いて、アルカリエッチング液で銅箔をエッチングしてバンプ３を形成した後、レジストを除去し、ニッケル選択エッチング液によってニッケル層を除去した。
次に、得られたバンプ３付き銅膜と、厚さ０．１００ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０４０ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）を介して、バンプ３が接着剤２に埋まるようにプレス積層した。続いて、銅膜表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、パッド４ａのエッチングパターンを形成した後、アルカリエッチング液で銅膜をエッチングして配線層を構成するパッド４ａを形成した。続いて、レジストを除去し、ニッケル選択エッチング液によりニッケル層を除去した後、パッド４ａ表面に、０．００３ｍｍ以上のニッケル膜（図示せず）と、純度９９．９％以上、厚さ０．０００３ｍｍ以上の金膜（図示せず）とを、順次めっきした。これにより、図４ａに示す配線基板４００が得られた。
続いて、得られた配線基板４００の絶縁基材である接着剤２表面に、半導体用銀ペースト５を用いてＬＳＩ素子６を搭載し（図４ｂ）、ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図４ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止した（図４ｄ）。その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ（図４ｅ）、露出した接着剤２表面を研磨して、バンプ３の頂上を露出させた（図４ｆ）。
最後に、はんだボール８をバンプ３の頂上に配置してリフローし、図４ｇに示す樹脂封止型半導体装置４１０を得た。なお、はんだボール８はＬＳＩ素子６の外側に配置されるファンアウトタイプである。得られた半導体装置４１０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例５＞
本実施例では、図５ａ〜図５ｆに示すようにして、樹脂封止型半導体装置を作製した。
まず、実施例１と同様にして配線基板５００を作製した。ただし、実施例１では、バンプ３を配線４の内側領域（すなわち、素子搭載領域に近い側の配線部分）に形成したが、本実施例では、図５ａに示すように、バンプ３を配線４の外側領域（すなわち、素子搭載領域から遠い側の配線部分）に形成した。
続いて、配線基板５００の素子搭載領域に、半導体用非導電性フィルム５ａを介してＬＳＩ素子６を搭載した後（図５ｂ）、ＬＳＩ素子６の端子と配線４の接続領域とをボンディングワイヤ１００によって接続した（図５ｃ）。なお、本実施例では、配線４の接続領域はバンプ３よりも内側（すなわち素子６に近い側）に設けられている。
このようにして形成した組立体をトランスファモールド金型にセットし、半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止した（図５ｄ）。その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ、露出した接着剤２表面を研磨して、バンプ３の頂上を露出させた（図５ｅ）。
最後に、はんだボール８をバンプ３の頂上に配置してリフローし、図５ｆに示す樹脂封止型半導体装置５１０を得た。なお、はんだボール８はＬＳＩ素子６の外側に配置されるファンアウトタイプである。得られた半導体装置５１０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例６＞
本実施例では、図６ａ〜図６ｇに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０１８ｍｍの電解銅箔の片面に、厚さ０．００１ｍｍのニッケル層（図示せず）をめっきした後、該ニッケル層表面に、厚さ０．００９ｍｍの銅膜をめっきした。次に、銅めっき膜の表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線２１のエッチングパターンを形成した後、アルカリエッチング液で銅めっき膜をエッチングして、配線２１を形成した。
得られた配線２１付き電解銅箔と、厚さ０．０２５ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０２５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）を介して、配線２１が接着剤２に埋まるようにプレス積層した。
次に、銅箔のみをアルカリエッチャントでエッチングしてニッケル層を露出させ、該ニッケル層を銅のエッチング性が少ないニッケル剥離液で除去して、銅配線２１を露出させた後、銅配線２１表面に、０．００３ｍｍ以上のニッケル膜と、純度９９．９％以上、厚さ０．０００３ｍｍ以上の金膜とをめっきにより形成した。これにより、図６ａに示す半導体素子搭載用配線基板６００が得られた。
続いて、得られた配線基板６００の絶縁基材側表面に、半導体用非導電性フィルム５ａを用いてＬＳＩ素子６を搭載し（図６ｂ）、ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図６ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止した（図６ｄ）。その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ（図６ｅ）、接着剤２の所定箇所にレーザを照射して貫通孔６１をあけ、配線２１の一部を露出させた（図６ｆ）。
最後に、はんだを貫通孔６１の底部にある配線２１の露出箇所に配置してリフローした。これにより、貫通孔６１内にはんだが充填された導体部材６２が形成されるとともに、その端部にはんだボール８が形成され、図６ｇに示す樹脂封止型半導体装置６１０が得られた。なお、はんだボール８はＬＳＩ素子６の内側に配置されるファンインタイプである。得られた半導体装置６１０では、配線２１は導体部材６２とはんだボール８とを介して外部の配線に接続される。
＜実施例７＞
本実施例では、図７ａ〜図７ｇに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）と、厚さ０．０１２ｍｍの銅箔とを、厚さ０．０２５ｍｍの接着剤フィルム２（日立化成工業（株）製ＳＰＡＩ）を介してプレス積層した。次に、銅箔の表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて、現像し、配線４を形成するためのめっきレジストパターンを形成した。
続いて、銅箔の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜とをめっきにより順次積層した後、めっきレジストを剥離し、金めっきをエッチングレジストとしてアルカリエッチャントで銅をエッチングして、配線パターン４を得た。これにより、図７ａに示す配線基板７００が得られた。
この配線基板７００を用い、実施例２と同様にして、端子部に金バンプ２００を備えるＬＳＩ素子６を搭載し、金バンプ２００と配線４とを、熱圧着により相互接続させた後（図７ｂ）ＬＳＩ素子６と配線基板との間に液状エポキシ樹脂１１を充填して硬化させ（図７ｃ）、半導体封止エポキシ樹脂（日立化成工業（株）製ＣＥＬ４００）で封止した（図７ｄ）。
その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ（図７ｅ）、接着剤２の所定箇所にレーザを照射して貫通孔６１をあけ、配線４の一部を露出させた（図７ｆ）。
最後に、はんだを貫通孔６１の底部にある配線４の露出箇所に配置してリフローした。これにより、貫通孔６１内にはんだが充填された導体部材６２が形成されるとともに、その端部にはんだボール８が形成され、図７ｇに示す樹脂封止型半導体装置７１０が得られた。なお、はんだボール８はＬＳＩ素子６の内側に配置されるファンインタイプである。得られた半導体装置７１０では、配線４は導体部材６２とはんだボール８とを介して外部の配線に接続される。
＜実施例８＞
本実施例では、図８ａ〜図８ｆに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０１２ｍｍの銅箔に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、バンプ３のめっきレジストパターンを形成した。次に、銅箔の露出箇所に、硫酸銅めっき浴により銅めっきを行った後、めっきレジストを剥離して、めっきバンプ３を得た。
得られたバンプ３付き銅箔と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）を介して、接着剤２にバンプ３を埋め込むようにプレスラミネートした。引き続いて、銅箔側に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線４用のめっきレジストパターンを形成した。
次いで、銅箔の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜をめっきにより順次積層した後、アルカリエッチャントで銅箔をエッチングして、配線パターン４を得た。これにより、図８ａに示すバンプ３が絶縁基材２に埋め込まれた配線基板８００が得られた。
続いて、得られた配線基板８００の絶縁基材側表面に、半導体用非導電性接着剤フィルム５ａを用いてＬＳＩ素子６を搭載し（図８ｂ）、ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図８ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により封止した（図８ｄ）。その後、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ、露出した接着剤２表面を研磨して、バンプ３の頂上を露出させた（図８ｅ）。
最後に、はんだボール８をバンプ３の頂上に配置してリフローし、図８ｆに示す樹脂封止型半導体装置８１０を得た。なお、はんだボール８はＬＳＩ素子６の内側と外側とに配置されるファンインアウトタイプである。得られた半導体装置８１０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例９＞
本実施例では、図９ａ〜図９ｇに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔の片面に、０．００１ｍｍの厚さのニッケル層（図示せず）をめっきし、このニッケル層表面に厚さ０．００９ｍｍの銅膜をめっきした。次に、電解銅箔表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、バンプ３形成用のエッチングレジストパターンを形成した。次に、電解銅箔をアルカリエッチャントでエッチングして、高さ０．０３５ｍｍのバンプ３を形成した後、レジストを剥離し、露出したニッケルを銅のエッチング速度が遅いニッケルエッチング液により除去した。
続いて、得られたバンプ３付き銅膜と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ３が接着剤２に埋め込まれるようにプレスラミネートした。その後、銅膜側に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線４形成用のめっきレジストパターンを形成し、銅膜の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜を順次めっきした。次いで、めっきレジストを剥離した後、アルカリエッチャントで銅をエッチングして配線パターン４を得た。これにより図９ａに示すバンプ３が絶縁基材２に埋め込まれた配線基板９００が得られた。
続いて、得られた配線基板９００の絶縁基材側表面に、それぞれ半導体用非導電性接着剤フィルム５ａを用いて複数のＬＳＩ素子６を搭載し（図９ｂ）、各ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図９ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、すべての素子６を半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により一括封止した後（図９ｄ）、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させた（図９ｅ）。
続いて、露出した接着剤２表面を研磨してバンプ３の頂上を露出させ、はんだボール８をバンプ３の頂上に配置してリフローした（図９ｆ）。なお、はんだボール８はＬＳＩ素子６の内側に配置されるファンインタイプである。最後に、封止済み組立て体９１０を個片に切り分けて、図９ｇに示す複数の樹脂封止型半導体装置９２０を得た。得られた半導体装置９２０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例１０＞
本実施例では、図１０ａ〜図１０ｆに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔の片面に０．００１ｍｍの厚さのニッケル層（図示せず）をめっきした後、このニッケル層表面に、厚さ０．００９ｍｍの銅をめっきした。次に、電解銅箔表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、バンプ３形成用のエッチングレジストパターンを形成した。次に、電解銅箔をアルカリエッチャントでエッチングして、高さ０．０３５ｍｍのバンプ３を形成した後、レジストを剥離し、露出したニッケルを銅のエッチング速度が遅いニッケルエッチング液により除去した。
続いて、得られたバンプ３付き銅膜と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ３が接着剤２に埋め込まれるようにプレスラミネートした。
次に、銅膜表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させ、現像して、配線４形成用のめっきレジストパターンを形成した。続いて、銅膜の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜を順次めっきし、めっきレジストを剥離した後、アルカリエッチャントで銅をエッチングして、配線パターン４を得た。これにより、図１０ａに示すバンプ３が絶縁基材２に埋め込まれた配線基板１０００が得られた。
続いて、得られた配線基板１０００の絶縁基材側表面に、それぞれ半導体用非導電性接着剤フィルム５ａを用いて複数のＬＳＩ素子６を搭載し（図１０ｂ）、各ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図１０ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、すべての素子６を半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により一括封止した後（図１０ｄ）、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ、露出した接着剤２表面を研磨してバンプ３の頂上を露出させた（図１０ｅ）。
最後に、はんだボール８をバンプ３の頂上に配置してリフローした後、封止済み組立て体を個片に切り分けて、図１０ｆに示す複数の半導体装置１０１０を得た。はんだボール８はＬＳＩ素子６の内側及び外側に配置されるファンインアウトタイプである。得られた半導体装置１０１０では、配線４はバンプ３とはんだボール８とを介して外部の配線に接続される。
＜実施例１１＞
本実施例では、図１１ａ〜図１１ｆに示すようにして、樹脂封止型半導体装置を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔の片面に０．００１ｍｍの厚さのニッケル層（図示せず）をめっきした後、このニッケル層表面に、厚さ０．００９ｍｍの銅をめっきした。次に、電解銅箔表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バンプ３形成用のエッチングレジストパターンを形成した。続いて、銅をアルカリエッチャントでエッチングして高さ０．０３５ｍｍのバンプ３を形成した後、レジストを剥離し、露出したニッケルを銅のエッチング速度が遅いニッケルエッチング液により除去した。
次に、得られたバンプ３付き銅膜と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ３が接着剤２に埋め込まれるようにプレスラミネートした。
続いて、銅膜表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のめっきレジストパターンを形成した後、銅膜の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜とを、順次めっきして積層した。次に、レジストパターンを剥離した後、アルカリエッチャントで銅をエッチングして、配線パターン４を得た。これにより、図１１ａに示すバンプ３を絶縁基材２に内蔵する配線基板１１００が得られた。
続いて、得られた配線基板１１００の絶縁基材側表面に、それぞれ半導体用非導電性接着剤フィルム５ａを用いて複数のＬＳＩ素子６を搭載し（図１１ｂ）、各ＬＳＩ素子６の端子と配線４とをボンディングワイヤ１００によって接続した（図１１ｃ）。
このようにして形成した組立体をトランスファモールド金型にセットし、すべての素子６を半導体封止樹脂７（日立化成工業（株）製ＣＥＬ−４００）により一括封止した後（図１１ｄ）、支持部材である金属シート１をエッチングして除去し、接着剤２の表面を露出させ、露出した接着剤２表面を研磨してバンプ３の頂上を露出させた（図１１ｅ）。
最後に、露出したバンプ３の頂部にニッケル金をフラッシュめっきし、端子９を形成した後、封止済み組立て体を個片に切り分けて、図１１ｆに示す複数の半導体装置１１１０を得た。端子９はＬＳＩ素子６の内側及び外側に配置されるファンインアウトタイプである。得られた半導体装置１１１０では、配線４はバンプ３と端子９とを介して外部の配線に接続される。
＜実施例１２＞
本実施例では、図１２ａ〜図１２ｇに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に０．００１ｍｍの厚さのニッケル層３２をめっきした後、このニッケル層表面に、厚さ０．００９ｍｍの銅膜３３をめっきした（図１２ａ）。次に、電解銅箔３１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バンプ４２形成用のエッチングパターン３４を形成した（図１２ｂ）。続いて、銅箔をアルカリエッチャントでエッチングして、高さ０．０３５ｍｍのバンプ４２を形成した後（図１２ｃ）、レジスト３４を剥離し、露出したニッケル３２を銅のエッチング速度が遅いニッケルエッチング液により除去した（図１２ｄ）。
次に、得られたバンプ４２付き銅膜３３と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ４２を埋め込むようにしてプレスラミネートした。
続いて、銅膜３３表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用めっきレジストパターン３７を形成した後、銅膜３３の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜３５と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜３６とを、順次めっきにより積層した。次いで、めっきレジスト３７を剥離した後、アルカリエッチャントで銅膜３３の露出箇所をエッチング除去して、銅箔３３、ニッケル膜３５及び金膜３６からなる３層構造の配線パターン４を得た。これにより、図１２ｇに示す配線基板１２００が得られた。
＜実施例１３＞
本実施例では、図１３ａ〜図１３ｇに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔４１の片面に０．００１ｍｍの厚さのニッケル層３２をめっきした後、このニッケル層３２の表面に、感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＨ−９０５０）をラミネートし、露光させて現像し、バンプ４３形成用のめっきレジストパターン４４を形成した（図１３ｂ）。続いて、ニッケル層３２の露出箇所に、厚さ０．０３５ｍｍの銅膜をめっきしてバンプ４３を形成した後（図１３ｃ）、レジスト４４を剥離し、露出したニッケル層３２を銅のエッチング速度が遅いニッケルエッチング液により除去した（図１３ｄ）。
次に、得られたバンプ４３付き銅箔４１と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ４３が接着剤２に埋め込まれるようにプレスラミネートした（図１３ｅ）。
引き続いて、銅箔４１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用めっきレジストパターン３７を形成した後、銅箔４１の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜３５と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜３６とを、順次めっきして積層した（図１３ｆ）。次いで、めっきレジスト３７を剥離した後、アルカリエッチャントで銅箔４１をエッチングして、銅箔３３、ニッケル膜３５及び金膜３６からなる３層構造の配線パターン４を得た。これにより、図１３ｇに示す配線基板１３００が得られた。
＜実施例１４＞
本実施例では、図１４ａ〜図１４ｇに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＨ−９０５０）をラミネートし、露光させて現像し、バンプ４３形成用めっきレジストパターン４４を形成した（図１４ｂ）。続いて、銅箔３１の露出箇所に、厚さ０．０３５ｍｍの銅膜をめっきにより形成してバンプ４３を得た後（図１４ｃ）、レジスト４４を剥離した（図１４ｄ）。
次に、得られたバンプ４３付き銅箔３１と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ４３が接着剤２に埋め込まれるようにプレスラミネートした（図１４ｅ）。
引き続いて、銅箔３１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のめっきレジストパターン３７を形成した後、銅箔３１の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜３５と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜３６とを、順次めっきして積層した（図１４ｆ）。次いで、めっきレジスト３７を剥離した後、アルカリエッチャントで銅箔３１の露出箇所をエッチング除去して、銅箔３１、ニッケル膜３５及び金膜３６からなる３層構造の配線パターン４を得た。これにより、図１４ｇに示す配線基板１４０が得られた。
＜実施例１５＞
本実施例では、図１５ａ〜図１５ｇに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バンプ４０形成用のエッチングレジストパターン３４を形成した（図１５ｂ）。続いて、銅箔３１を０．０３０ｍｍの深さにエッチングしてバンプ４０を形成した後（図１５ｃ）、レジスト３４を剥離した（図１５ｄ）。
次に、得られたバンプ４０付き銅箔３１と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ４０が接着剤２に埋め込まれるようにプレスラミネートした（図１５ｅ）。
引き続いて、銅箔３１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のめっきレジストパターン３７を形成した後（図１５ｆ）、銅箔３１の露出箇所に、厚さ０．００３ｍｍ以上のニッケル膜と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜とを、順次めっきして積層した。次いで、めっきレジスト３７を剥離した後、銅箔３１の露出箇所をアルカリエッチャントでエッチングして、銅箔３１、ニッケル膜３５及び金膜３６からなる３層構造の配線パターン４を得た。これにより、図１５ｇに示す配線基板１５０が得られた。
＜実施例１６＞
本実施例では、図１６ａ〜図１６ｈに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に、０．００１ｍｍの厚さのニッケル層３２をめっきした後、このニッケル層３２の表面に厚さ０．００９ｍｍの銅膜３３をめっきした（図１６ａ）。次に、銅膜３３表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のエッチングレジストパターン３７を形成した後（図１６ｂ）、銅膜３３の露出箇所をエッチング除去し、レジストパターン３７を剥離して配線４を形成した（図１６ｃ）。
次に、配線４と配線４の間で露出したニッケル層３２との表面に、感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＨ−９０５０）をラミネートし、露光させて現像し、バンプ４６形成用のめっきレジストパターン３４を形成した後（図１６ｄ）、配線４の露出箇所に厚さ０．０３５ｍｍの銅をめっきし、バンプ４６を形成し（図１６ｅ）、レジスト３４を剥離した。
続いて、得られた配線４及びバンプ４６付き銅箔３１と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ４６を接着剤２に埋め込むようにプレスラミネートした後（図１６ｇ）、銅箔３１をアルカリエッチャントでエッチングしてニッケル層３２を露出させ、この露出したニッケル層３２を銅のエッチング速度が遅いニッケルエッチング液により除去した。次いで、配線４表面に厚さ０．００３ｍｍ以上のニッケル膜（図示せず）と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜（図示せず）とをめっきした。これにより、図１６ｈに示す配線基板１６０が得られた。
＜実施例１７＞
本実施例では、図１７ａ〜図１７ｅに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に０．００１ｍｍの厚さのニッケル層３２をめっきした後、このニッケル層３２表面に厚さ０．００９ｍｍの銅膜３３をめっきした。次に、電解銅箔３１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バンプ３形成用のエッチングレジストパターンを形成した。続いて、銅箔３１の露出箇所をアルカリエッチャントでエッチングして、高さ０．０３５ｍｍのバンプ３を形成した後、レジストを剥離した。
次に、得られたバンプ３つき銅膜３３と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ３を接着剤２に埋め込むようにプレスラミネートした。
引き続いて、銅膜３３表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のエッチングレジストパターンを形成した後、銅膜３３の露出箇所をアルカリエッチャントでエッチングして１層目の配線４を形成し、露出したニッケル層３２を選択的にエッチング除去した（図１７ａ）。
次に、配線４を覆うようにＲＣＣ（樹脂コート銅箔）４６を積層して樹脂層３９及び銅層４５を形成した後（図１７ｂ）、銅層４５表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バイアホール４８用貫通孔４７のエッチングレジストパターンを形成した。
続いて、露出した銅層４５を酸エッチャントでエッチングし、さらに樹脂層３９にＣＯ２レーザで孔開けして、１層目の配線４に達する直径０．１５ｍｍの貫通孔４７を銅層４５及び樹脂層３９に形成した後、貫通孔４７内のクリーニングを通常の方法で行い、貫通孔４７内壁に厚さ０．０１５ｍｍで銅めっき膜４９を形成してバイアホール４８を形成した（図１７ｄ）。
次に、銅めっき膜４９表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用エッチングレジストパターンを形成した後、露出箇所の銅層４９，４５をアルカリエッチャントでエッチングして銅層４９，４５からなる２層目の配線４を形成した。次いで、２層目の配線４の表面に厚さ０．００３ｍｍ以上のニッケル膜（図示せず）と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜（図示せず）とをめっきした。これにより、図１７ｅに示す配線基板１７０が得られた。
＜実施例１８＞
本実施例では、図１８ａ〜図１８ｅに示すようにして、半導体素子搭載用配線基板を作製した。
まず、厚さ０．０３５ｍｍの電解銅箔３１の片面に０．００１ｍｍの厚さのニッケル層３２をめっきした後、このニッケル層３２の表面に、厚さ０．００９ｍｍの銅膜３３をめっきした（図１８ａ）。次に、銅膜３３表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用のエッチングレジストパターンを形成した。続いて、銅膜３３の露出箇所をアルカリエッチャントでエッチングして１層目の配線４を形成した後、レジストを剥離した（図１８ｂ）。
次に、得られた配線４付き銅箔３１の表面に、配線４を覆うように、ＲＣＣ（樹脂コート銅箔）４６を積層して、樹脂層３９及び銅層４５を形成した（図１８ｃ）。続いて、銅層４５表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、バイアホール４８形成用貫通孔４７のエッチングレジストパターンを形成した。次に、銅層４５の露出箇所を酸エッチャントでエッチングし、さらに樹脂層３９にＣＯ２レーザで孔開けして、１層目の配線４に達する直径０．１５ｍｍの貫通孔４７を銅層４５及び樹脂層３９に形成した後（図１８ｄ）、貫通孔４７内のクリーニングを通常の方法で行い、貫通孔４７内壁に厚さ０．０１５ｍｍで銅めっき膜４９を形成してバイアホール４８を形成した（図１８ｅ）。
次に、銅めっき膜４９表面及び銅箔３１表面に感光性ドライフィルムレジスト（日立化成工業（株）製フォテックＲＹ−３０２５）をラミネートし、露光させて現像し、配線４形成用エッチングレジストパターン及びバンプ３形成用エッチングレジストパターンを形成した。
続いて、露出箇所の銅層４９，４５及び銅箔３１をアルカリエッチャントでエッチングして銅層４９，４５からなる２層目の配線４するとともに、バンプ３を形成し、さらにニッケルの露出箇所を選択エッチングして除去した後、レジストを剥離した（図１８ｆ）。
次いで、得られたバンプ３付き配線部材と、厚さ０．０５０ｍｍの金属シート１（ステンレススチールＳＵＳ３０４）とを、厚さ０．０５ｍｍの接着剤２（日立化成工業（株）製ＳＰＡＩ）により、バンプ３を接着剤２に埋め込むようにプレスラミネートした。続いて、２層目の配線４の表面に厚さ０．００３ｍｍ以上のニッケル膜（図示せず）と、厚さ０．０００３ｍｍ以上、純度９９．９％以上の金膜（図示せず）とをめっきした。これにより、図１８ｇに示す配線基板１８０が得られた。
産業上の利用可能性
上述のように、本発明によれば、小型化、高集積度化に柔軟に対応することができる半導体装置を、生産性良くかつ安定的に製造することができる。
【図面の簡単な説明】
図１ａ〜図１ｇは、本発明による半導体装置の製造工程を示す断面図である。
図２ａ〜図２ｆは、本発明による半導体装置の製造工程を示す断面図である。
図３ａ〜図３ｆは、本発明による半導体装置の製造工程を示す断面図である。
図４ａ〜図４ｇは、本発明による半導体装置の製造工程例を示す断面図である。
図５ａ〜図５ｆは、本発明による半導体装置の製造工程例を示す断面図である。
図６ａ〜図６ｇは、本発明による半導体装置の製造工程例を示す断面図である。
図７ａ〜図７ｇは、本発明による半導体装置の製造工程例を示す断面図である。
図８ａ〜図８ｆは、本発明による半導体装置の製造工程例を示す断面図である。
図９ａ〜図９ｇは、本発明による半導体装置の製造工程例を示す断面図である。
図１０ａ〜図１０ｆは、本発明による半導体装置の製造工程例を示す断面図である。
図１１ａ〜図１１ｆは、本発明による配線基板の製造工程例を示す断面図である。
図１２ａ〜図１２ｇは、本発明による配線基板の製造工程例を示す断面図である。
図１３ａ〜図１３ｇは、本発明による配線基板の製造工程例を示す断面図である。
図１４ａ〜図１４ｇは、本発明による配線基板の製造工程例を示す断面図である。
図１５ａ〜図１５ｇは、本発明による配線基板の製造工程例を示す断面図である。
図１６ａ〜図１６ｈは、本発明による配線基板の製造工程例を示す断面図である。
図１７ａ〜図１７ｅは、本発明による配線基板の製造工程例を示す断面図である。
図１８ａ〜図１８ｇは、本発明による配線基板の製造工程例を示す断面図である。Technical field
The present invention relates to a wiring board, a semiconductor device using the wiring board, and a method for manufacturing the same.
Background art
As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor device having a large number of input / output terminals is required. In general, there are a type in which input / output terminals are arranged in one line around the package, and a type in which input / output terminals are arranged in multiple lines not only in the periphery but also inside. The former is typically a QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in the region of 0.5 mm pitch or less, advanced technology is required for connection with a wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch.
Conventionally, the array type is generally a PGA (Pin Grid Array) having connection pins, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason, a package called a surface mountable BGA (Ball Grid Array) has been developed. The BGA is classified into (1) a ceramic type, (2) a printed wiring board type, and (3) a tape type using TAB (tape automated bonding). Among them, in the ceramic type, since the distance between the motherboard and the package is shorter than that of the conventional PGA, package warpage caused by a difference in thermal stress between the motherboard and the package is a serious problem. In addition, the printed wiring board type also has problems such as a large substrate thickness in addition to substrate warpage, moisture resistance, reliability, and the like, and a tape BGA to which TAB technology is applied has been proposed.
A so-called element size package (CSP: Chip Size Package) having a size substantially equal to that of a semiconductor element has been proposed as a device capable of further reducing the package size. This is a package having a connection portion with an external wiring board in a mounting region, not in a peripheral portion of a semiconductor element.
As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor element, the element is electrically connected to the element by a gold lead wire, and then epoxy resin or the like is potted and sealed (NIKKEI MATERIALS & TECHNOLOGY 94. 4, No. 140, pp. 18-19) and forming a metal bump on a temporary substrate at a position corresponding to a connection portion between a semiconductor element and an external wiring board, and performing face-down bonding of the semiconductor element and then transferring the semiconductor element onto the temporary substrate. And a molded product (Smallest Flip-Chip-Like Package CSP; The Second VL SI Packaging Works of Japan, p46-50, 1994).
On the other hand, as described above, packages using a polyimide tape as a base film are being studied in the BGA and CSP fields. In this case, the polyimide tape is generally a laminate of copper foil on a polyimide film via an adhesive layer, and a polyimide layer is formed directly on the copper foil from the viewpoint of heat resistance and moisture resistance. A so-called two-layer flexible substrate is preferred.
The method for producing the two-layer flexible base material includes: (1) a method of applying a polyamic acid, which is a precursor of polyimide, on a copper foil and then thermally curing the same; (2) a vacuum film forming method on the cured polyimide film; A method of forming a metal thin film by an electroless plating method or the like.
In the case of a two-layer flexible substrate, for example, in the case where a polyimide is removed from a desired portion by applying laser processing to provide a concave portion reaching the copper foil, it is preferable that the polyimide film be as thin as possible. On the other hand, when the two-layer flexible base material is processed into a lead frame shape and handled, if the base film is thin, there are problems such as lack of handleability and rigidity as a frame.
As described above, various proposals have been made for a semiconductor device which can cope with miniaturization and high integration. However, further improvement is desired so as to satisfy all of performance, characteristics, productivity and the like.
Disclosure of the invention
The present invention relates to a semiconductor element mounting wiring board for manufacturing a semiconductor device (semiconductor package) capable of responding to miniaturization and high integration with good productivity and stability, a semiconductor device using the board, An object of the present invention is to provide a method for manufacturing the same.
In the present invention, an insulating base, a wiring member having wiring provided on one of the front and back surfaces of the insulating base, and a conductive member embedded in the insulating base are provided, and one end of the conductive member is insulated. A wiring board is provided which is exposed on the surface of the base material and connected to the wiring, and the other end is embedded in the insulating base material. Note that the wiring board of the present invention may further include a support member provided on the other surface of the insulating base material (that is, the surface of the front and back surfaces where the conductor member is not exposed).
Further, in the present invention, a wiring board including an insulating base, a wiring member having wiring provided on one of the front and back surfaces of the insulating base, and a supporting member provided on the other surface of the insulating base is provided. Provided. The wiring board may further include a conductor member embedded in the insulating base material and connected to the wiring, but may not include the conductor member. When a conductor member is provided, one end of the conductor member needs to be connected to the wiring, but the other end may be covered with an insulating base material. The other end of the member may reach the support member.
Further, in the present invention, as a method of manufacturing the wiring board of the present invention described above,
(1) A method for manufacturing a wiring board, comprising a laminating step of laminating a wiring member provided with a protruding conductor member on one of the front and back surfaces and an insulating base material with the conductor member facing inward and facing each other;
(2) A laminating step of laminating a conductor layer having a protruding conductor member on one of the front and back surfaces and an insulating base material with the conductor member facing inside, and removing unnecessary portions of the conductor layer. And a method for manufacturing a wiring board comprising a wiring member forming step of forming a wiring member, and
(3) a method of manufacturing a wiring board including a laminating step of laminating a wiring member, an insulating base material, and a support member in this order;
Is provided.
Further, in the present invention, the mounting step of mounting the semiconductor element on the wiring member surface of the wiring board of the present invention described above, the connecting step of electrically connecting the semiconductor element and the wiring on the wiring member surface, and the sealing of the semiconductor element by the sealing member A method of manufacturing a semiconductor device, comprising: a sealing step of covering and sealing; and an insulating base material removing step of removing at least a part of the conductor member by removing a part of the insulating base material. Note that a sealing step of covering and sealing the semiconductor element with a sealing member may be further provided. In this case, any of the sealing step and the insulating base material removing step may be performed first.
Further, in the present invention, a mounting step of mounting a semiconductor element on the wiring member side surface of the wiring board of the present invention, a connecting step of electrically connecting the semiconductor element and the wiring on the wiring member surface, and removing at least a part of the support member. A supporting member removing step of exposing at least a part of the insulating base material, forming a through hole by removing at least a part of the insulating base material, and an insulating base material removing step of exposing at least a part of the wiring; There is provided a method of manufacturing a semiconductor device including a conductor member forming step of forming a conductor member connected to a wiring by filling a hole with a conductor.
In the method of manufacturing a semiconductor device according to the present invention, the semiconductor element can be mounted on the wiring board via an adhesive, but may be mounted without an adhesive.
Further, the present invention provides a semiconductor device manufactured by the above-described manufacturing method of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
The wiring board of the present invention includes an insulating base material, a wiring member, and a conductor member, one end of the conductor member is exposed on the surface of the insulating base material and connected to the wiring of the wiring member, and the other end is connected to the insulating base. Embedded in the material.
Although the material of the insulating base material in the wiring member is not particularly limited, for example, a resin composition containing an epoxy resin, a polyamideimide resin, or the like, a resin precursor composition, or a cured product thereof can be used. The resin composition or the resin precursor composition preferably contains whiskers, and it is particularly preferable to use polyamideimide for the resin. The resin of the insulating base material may be in a state before curing or in a semi-cured state, but is preferably after curing in a semiconductor device.
In the present invention, an epoxy resin cured product suitable as an insulating substrate is obtained by curing an epoxy resin composition containing an epoxy resin and a curing agent. The epoxy resin composition (preferably a thermosetting resin composition) may further contain a curing accelerator, a catalyst, an elastomer, a flame retardant, and the like, if necessary.
The epoxy resin that can be used here may be any epoxy resin having an epoxy group in the molecule, such as a bisphenol A epoxy resin, a bisphenol F epoxy resin, a bisphenol S epoxy resin, an alicyclic epoxy resin. Resin, aliphatic chain epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, diglycidyl ether compound of biphenol, diglycidyl ether compound of naphthalene diol, diglycidyl ether compound of phenol And diglycidyl ethers of alcohols, and alkyl-substituted, halogenated and hydrogenated products thereof. These may be used in combination, and components other than the epoxy resin may be contained as impurities.
In the present invention, a halogenated bisphenol A type epoxy resin, a halogenated bisphenol F type epoxy resin, a halogenated bisphenol S type epoxy resin, an epoxy resin to be obtained by reacting a halogenated bisphenol compound such as tetrabromobisphenol A with epichlorohydrin When an epoxy resin in which the ortho position is substituted with a halogen atom such as chlorine or bromine with respect to the ether group of the benzene ring to which the ether group is bonded is used, in the removal treatment performed when forming a via hole or the like, The efficiency of decomposition and / or dissolution of the cured epoxy resin is particularly good.
The curing agent for an epoxy resin used in the present invention can be used without limitation as long as it cures an epoxy resin.For example, polyfunctional phenols, amines, imidazole compounds, acid anhydrides, organic phosphorus compounds and There are these halides and the like.
Examples of polyfunctional phenols include monocyclic bifunctional phenols such as hydroquinone, resorcinol, catechol, and polycyclic bifunctional phenols such as bisphenol A, bisphenol F, naphthalene diols, biphenols, and halides thereof, and alkyl group substitution. There is a body. Further, there are novolaks and resols which are polycondensates of these phenols and aldehydes.
Examples of amines include aliphatic or aromatic primary amines, secondary amines, tertiary amines, quaternary ammonium salts and aliphatic cyclic amines, guanidines, urea derivatives and the like. These compounds include N, N-benzyldimethylamine, 2- (dimethylaminomethyl) phenol, 2,4,6-tris (dimethylaminomethyl) phenol, tetramethylguanidine, triethanolamine, N, N'- Dimethylpiperazine, 1,4-diazabicyclo [2,2,2] octane, 1,8-diazabicyclo [5,4,0] -7-undecene, 1,5-diazabicyclo [4,4,0] -5-nonene , Hexamethylenetetramine, pyridine, picoline, piperidine, pyrrolidine, dimethylcyclohexylamine, dimethylhexylamine, cyclohexylamine, diisobutylamine, di-n-butylamine, diphenylamine, N-methylaniline, tri-n-propylamine, tri-n -Octylamine, tri-n-butyla Examples include min, triphenylamine, tetramethylammonium chloride, tetramethylammonium bromide, tetramethylammonium iodide, triethylenetetramine, diaminodiphenylmethane, diaminodiphenylether, dicyandiamide, tolylbiguanide, guanylurea, and dimethylurea.
Examples of imidazole compounds include imidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-methylimidazole, 2-phenylimidazole, 2-undecylimidazole, 1-benzyl-2-methylimidazole, Heptadecyl imidazole, 4,5-diphenylimidazole, 2-methylimidazoline, 2-phenylimidazoline, 2-undecylimidazoline, 2-heptadecylimidazoline, 2-isopropylimidazole, 2,4-dimethylimidazole, 2-phenyl-4 -Methylimidazole, 2-ethylimidazoline, 2-phenyl-4-methylimidazoline, benzimidazole, 1-cyanoethylimidazole and the like.
Examples of the acid anhydride include phthalic anhydride, hexahydrophthalic anhydride, pyromellitic dianhydride, benzophenonetetracarboxylic dianhydride and the like.
As the organic phosphorus compound, any phosphorus compound having an organic group can be used without any particular limitation. For example, hexamethylphosphoric triamide, tri (dichloropropyl) phosphate, tri (chloropropyl) phosphate, phosphorous acid Examples include triphenyl, trimethyl phosphate, phenylphosphonic acid, triphenylphosphine, tri-n-butylphosphine, diphenylphosphine, and the like.
One of these curing agents may be used alone, or two or more thereof may be used in combination.
The amount of the curing agent for the epoxy resin can be used without any particular limitation as long as the curing reaction of the epoxy group can proceed, but preferably 0.01 to 5.0 with respect to 1 mol of the epoxy group. It is used in the range of equivalents, particularly preferably in the range of 0.8 to 1.2 equivalents.
Moreover, you may mix | blend a hardening accelerator with an epoxy resin composition as needed. Representative curing accelerators include, but are not limited to, tertiary amines, imidazoles, quaternary ammonium salts, and the like.
The curing reaction of the epoxy resin composition may be performed at any temperature as long as the reaction proceeds, but it is generally preferable to cure the epoxy resin composition at room temperature to 250 ° C. This curing reaction can be performed under pressure, under atmospheric pressure, or under reduced pressure.
When a polyamide-imide resin is used for the insulating base material, it is preferable to use a silicone-modified polyamide-imide. This silicone-modified polyamide imide is a polymer having a siloxane bond, an imide bond, and an amide bond.
(1) a method of reacting a diimide dicarboxylic acid 1a containing a diimide dicarboxylic acid having a siloxane bond with a diisocyanate compound 1b,
(2) a method of reacting a diamine compound 2a containing a diamine having a siloxane bond with a tricarboxylic acid chloride 2b;
(3) a method of reacting a diisocyanate compound 3a containing a diisocyanate having a siloxane bond with a tricarboxylic anhydride 3b;
There are three methods.
The silicone-modified polyamideimide obtained by the method (1) will be described in detail. Examples of the diimidedicarboxylic acid containing the diimidedicarboxylic acid 1a having a siloxane bond include the following compounds.
Among the diimide dicarboxylic acids other than the diimide dicarboxylic acid having a siloxane bond, examples of the diimide dicarboxylic acid in which the divalent residue linking the imide group is aromatic include the following (formula 1) and (formula 2) Is mentioned.
Figure 2003021668
As an example of a diimide dicarboxylic acid having a siloxane bond, R 1 Is a divalent aliphatic group (which may contain oxygen). Examples of the divalent aliphatic group include an alkylene group such as a propylene group, a hexamethylene group, an octamethylene group, a decamethylene group, and an octadecamethylene group, and a group in which oxygen is bonded to both ends of an alkylene group.
Figure 2003021668
The above divalent organic group R 1 And R 2 Examples thereof include an alkylene group such as a propylene group, a phenylene group, and an alkyl-substituted phenylene group.
Examples of the diisocyanate compound 1a include the following (formula 3) as an aromatic diisocyanate compound.
Figure 2003021668
Also, R 9 Examples thereof include an aliphatic diisocyanate compound or an alicyclic diisocyanate compound having a divalent aliphatic group such as an alkylene group or a divalent alicyclic group such as a cycloalkylene group.
The diimide dicarboxylic acid having a siloxane bond and the other diimide dicarboxylic acid can be obtained by reacting a diamine compound having a siloxane bond and another diamine with trimellitic anhydride, respectively.
It is preferable to use a diimide dicarboxylic acid having a siloxane bond and other diimide dicarboxylic acids as a mixture.
It is particularly preferable to use a diimide dicarboxylic acid mixture obtained by reacting a mixture of a diamine compound having a siloxane bond and other diamines with trimellitic anhydride.
As the diamine other than the diamine compound having a siloxane bond, an aromatic diamine is preferable, and a diamine having three or more aromatic rings is particularly preferable. It is preferable that the aromatic diamine is used in an amount of 50 to 100 mol% among the diamines other than the diamine compound having a siloxane bond.
Further, the diamine other than the diamine compound having a siloxane bond (A) and the siloxane diamine (B) have a ratio (A) / (B) of 99.9 / 0.1 to 0.1 / 99.9 (molar ratio). It is preferably used. Further, (A) a diamine other than the diamine compound having a siloxane bond, (B) a siloxane diamine and trimellitic anhydride are used in an amount of 2.05 to 2 with respect to a total of 1 mol of (A) + (B). The reaction is preferably performed at a ratio of .20.
As the diisocyanate compound, an aromatic diisocyanate compound is preferable, and among the diisocyanate compounds, it is preferable to use 50 to 100 mol% of the aromatic diisocyanate compound.
It is preferable that the entire diimide dicarboxylic acid and the diisocyanate compound are reacted so that the former is 1 mol and the latter is 1.05 to 1.50 mol.
The diamine compound and trimellitic anhydride are reacted at 50 to 90 ° C. in the presence of an aprotic polar solvent, and an aromatic hydrocarbon capable of azeotroping with water is further reacted with an aprotic polar solvent of from 0.1 to It is preferable that the mixture is charged at a weight ratio of 0.5 and reacted at 120 to 180 ° C. to produce a mixture containing imide dicarboxylic acid and siloxane diimide dicarboxylic acid, and the mixture is reacted with a diisocyanate compound. After the diimide dicarboxylic acid is produced, it is preferable to remove the aromatic hydrocarbon from the solution.
When the reaction temperature of the imidodicarboxylic acid and the diisocyanate compound is low, the reaction time is prolonged. When the reaction temperature is too high, isocyanates react with each other.
Examples of the aromatic diamine include phenylenediamine, bis (4-aminophenyl) methane, 2,2-bis (4-aminophenyl) propane, bis (4-aminophenyl) carbonyl, bis (4-aminophenyl) sulfone, and bis (4-aminophenyl) sulfone. (4-aminophenyl) ether and the like. In particular, as a diamine having three or more aromatic rings, 2,2-bis [4- (4-aminophenoxy) phenyl] propane (hereinafter abbreviated as BAPP), Bis [4- (3-aminophenoxy) phenyl] sulfone, bis [4- (4-aminophenoxy) phenyl] sulfone, 2,2-bis [4- (4-aminophenoxy) phenyl] hexafluoropropane, bis [ 4- (4-aminophenoxy) phenyl] methane, 4,4'-bis (4-aminophenoxy) biphenyl, bis [4 -(4-aminophenoxy) phenyl] ether, bis [4- (4-aminophenoxy) phenyl] ketone, 1,3-bis (4-aminophenoxy) benzene and the like.
Examples of the aliphatic diamine include hexamethylene diamine, octamethylene diamine, decamethylene diamine, octadecamethylene diamine, and propylene glycol having an aminated terminal. In addition, examples of the alicyclic diamine include 1,4-diaminocyclohexane.
As the siloxane diamine, those represented by the following general formula (4) can be used.
Figure 2003021668
Examples of such a siloxane diamine include those represented by (Formula 5). Among them, amino-modified reactive silicone oils X-22-161AS (amine equivalent 450), X-22-161A (amine equivalent 840), X-22-161B (amine equivalent 1500) which are dimethylsiloxane-based both terminal amines, As mentioned above, commercially available products include trade names of Shin-Etsu Chemical Co., Ltd., BY16-853 (amine equivalent: 650), and BY16-853B (amine equivalent: 2,200) or more, manufactured by Toray Dow Corning Silicone Co., Ltd.
Figure 2003021668
Specific examples of the aromatic diisocyanate include 4,4′-diphenylmethane diisocyanate (hereinafter abbreviated as MDI), 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate, naphthalene-1,5-diisocyanate, 2,4 -Tolylene dimer and the like. In particular, MDI is preferred because the isocyanate group is separated in the molecular structure, the concentration of the amide group or imide group in the molecule of the polyamideimide becomes relatively low, and the solubility is improved.
Examples of the aliphatic or alicyclic diisocyanate include hexamethylene diisocyanate, isophorone diisocyanate, and methylene bis (cyclohexyl diisocyanate).
Examples of the aprotic polar solvent include dimethylacetamide, dimethylformamide, dimethylsulfoxide, N-methyl-2-pyrrolidone, 4-butyrolactone, sulfolane, cyclohexanone and the like. N-methyl-2-methylpyrrolidone (hereinafter abbreviated as NMP), which has a high boiling point because an imidation reaction requires a high temperature, is particularly preferable. The amount of water contained in these mixed solvents is controlled at 0.2% by weight or less because trimellitic acid generated by hydration of TMA does not sufficiently react and causes a decrease in the molecular weight of the polymer. Is preferred. In addition, the aprotic polar solvent is not particularly limited, but the solubility of trimellitic anhydride is reduced when the weight ratio of the total of the diamine having three or more aromatic rings, the siloxane diamine, and trimellitic anhydride is large. However, it is preferable that the amount be in the range of 10% by weight to 70% by weight, since a sufficient reaction cannot be performed, and a low level is disadvantageous as an industrial production method.
Examples of aromatic hydrocarbons that can be azeotroped with water include aromatic hydrocarbons such as benzene, xylene, ethylbenzene, and toluene. Particularly, toluene having a relatively low boiling point and less harmful to the working environment is preferable. And the aprotic polar solvent is preferably in the range of 0.1 to 0.5% by weight (10 to 50% by weight).
Next, the silicone-modified polyamideimide obtained by the method (2) will be described. As the diamine compound 2a containing a diamine having a siloxane bond, there are a diamine having a siloxane bond and a compound represented by the above formula (5). Further, as the other diamine, the above-described diamine can also be used.
Tricarboxylic acid chloride 2b includes trimellitic acid chloride and the like, and can be produced by a well-known acid chloride method.
Next, the silicone-modified polyamideimide obtained by the method (3) will be described. As the diisocyanate compound containing a diisocyanate having a siloxane bond, a diisocyanate compound having a siloxane bond and a siloxane diamine represented by the above formula (4) are used. As the corresponding diisocyanate compound and other diisocyanate compounds, those described above can be used.
Tricarboxylic anhydride 3b includes trimellitic anhydride and the like, and can be produced by a reaction of a conventionally well-known diamine compound and a diisocyanate compound.
Further, a resin composition containing whiskers may be used as the insulating base material. Particularly when the resin alone does not have a film forming ability, it is effective to mix whiskers. In addition, the film forming ability here, when coating the varnish on the carrier film, it is easy to control the predetermined thickness, and after heating and drying to transport to a semi-cured state, in cutting, It means that the workability is good, the resin is hardly cracked or chipped when used in the laminating step, and the minimum thickness of the interlayer insulating layer can be secured at the time of the subsequent heat and pressure molding. Resins having no film-forming ability usually have a low molecular weight of not exceeding 30,000 in many cases.
Specifically, a thermosetting resin impregnated in a glass cloth base material is preferable as the insulating base material, and examples of the thermosetting resin include an epoxy resin, a bistriazine resin, a polyimide resin, a phenol resin, a melamine resin, and silicon. Resins, unsaturated polyester resins, cyanate ester resins, isocyanate resins, or modified resins thereof can be used.
Among them, epoxy resin, polyimide resin, or bistriazine resin is particularly suitable for improving the characteristics of the laminate.
Furthermore, as the epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, salicylaldehyde novolak type epoxy resin, bisphenol F novolak type Epoxy resin, alicyclic epoxy resin, glycidyl ester type epoxy resin, glycidylamine type epoxy resin, hydantoin type epoxy resin, isocyanurate type epoxy resin, aliphatic cyclic epoxy resin, and halides and hydrogenated products thereof One or more selected ones can be used. Among them, bisphenol A novolak type epoxy resin and salicylaldehyde novolak type epoxy resin are preferable because of their excellent heat resistance.
The whiskers to be added to the resin composition constituting the insulating base material are electrically insulating ceramic whiskers, and preferably have an elastic modulus of 200 GPa or more. If it is less than 200 GPa, sufficient rigidity may not be obtained when used as a wiring board material or a wiring board.
As such a material, for example, one or more materials selected from aluminum borate, wollastonite, potassium titanate, basic magnesium sulfate, silicon nitride, and α-alumina can be used. Among them, aluminum borate whiskers and potassium titanate whiskers have Mohs hardness almost equal to E glass used for a general prepreg base material, and can obtain the same drill workability as conventional prepreg. Aluminum borate whiskers are more preferable because they have a high elastic modulus of approximately 400 GPa and are easily mixed with the resin varnish.
The average diameter of the whiskers is preferably from 0.3 μm to 3 μm, and more preferably from 0.5 μm to 1 μm. When the average diameter of the whiskers is 0.3 μm or less, mixing with the resin varnish becomes difficult. When the average diameter exceeds 3 μm, the microscopic dispersion in the resin is insufficient, and the unevenness of the surface becomes large, which is not preferable. .
In addition, the ratio of the average diameter to the average length is preferably 10 or more because the rigidity can be further increased, and more preferably 20 or more. When this ratio is less than 10, the reinforcing effect as a fiber becomes small. The upper limit of this average length is 100 μm, and more preferably 50 μm. If the upper limit is exceeded, dispersion into the resin varnish becomes difficult, and the probability that one whisker contacts two conductor circuits increases, and the probability of migration of copper ions along the fibers of the whisker increases. Become.
In addition, in order to increase the rigidity, heat resistance and moisture resistance of the wiring board, it is preferable to use an electrically insulating whisker surface-treated with a coupling agent having excellent wettability and bondability with a resin. As coupling agents, silicon-based coupling agents, titanium-based coupling agents, aluminum-based coupling agents, zirconium-based coupling agents, zirconium-based coupling agents, chromium-based coupling agents, boron-based coupling agents, and phosphorus-based coupling agents It can be used by selecting from coupling agents, amino acid-based coupling agents, and the like.
As the curing agent for such a resin, those conventionally used can be used. When the resin is an epoxy resin, for example, dicyandiamide, bisphenol A, bisphenol F, polyvinyl phenol, novolak resin, bisphenol A novolak resin, and And the like of a phenol resin. Among them, bisphenol A novolak resin is preferable because of its excellent heat resistance.
The ratio of the curing agent to the resin may be a conventionally used ratio, and is preferably in the range of 2 to 100 parts by weight with respect to 100 parts by weight of the resin. Further, in the case of dicyandiamide, 2 to 5 parts by weight, For other curing agents, the range is preferably 30 to 80 parts by weight.
When the resin is an epoxy resin, an imidazole compound, an organic phosphorus compound, a tertiary amine, a quaternary ammonium salt, or the like can be used as the curing accelerator.
The ratio of the curing accelerator to the resin may be a conventionally used ratio, and is preferably in the range of 0.01 to 20 parts by weight, and more preferably in the range of 0.1 to 1.0, based on 100 parts by weight of the resin. More preferred.
These are used after being diluted in a solvent, and include acetone, methyl ethyl ketone, toluene, xylene, methyl isobutylene, ethyl acetate, ethylene glycol monomethyl ether, methanol, ethanol, N, N-dimethylformamide, N, N-dimethyl. Acetamide and the like can be used.
The ratio of the diluent to the resin may be a conventionally used ratio, and is preferably in the range of 1 to 200 parts by weight, more preferably 30 to 100 parts by weight, per 100 parts by weight of the resin.
The ratio between the thermosetting resin and the whisker is preferably adjusted so that the volume fraction of the whisker in the cured resin is in the range of 5% to 50%. If the volume fraction of whiskers in the cured resin is less than 5%, the prepreg with copper foil (copper foil / thermosetting resin layer) is extremely difficult to handle, such as when the resin is finely crushed and scattered when cut. The rigidity is reduced when the wiring board is used. On the other hand, if the volume fraction of the whisker exceeds 50%, filling in holes and circuit gaps at the time of heat and pressure molding becomes insufficient, and voids and blurring may occur after the molding, resulting in a decrease in insulation. Further, as for the ratio of the resin to the whisker, the volume fraction of the whisker in the cured resin is more preferably 20 to 40%.
The insulating base material used in the present invention is, for example, whiskers are mixed with a varnish made of a resin and a solvent, and the whiskers are uniformly dispersed in the varnish by stirring, and the whiskers are coated on one surface of a supporting member such as a copper foil. The resin can be formed in a semi-cured state while removing the solvent by heating and drying.
When the above-described resin composition is applied to a supporting member to form an insulating base material, a method for applying the resin composition is not particularly limited, and examples thereof include a blade coater, a rod coater, a knife coater, a squeeze coater, and a reverse coater. A coating method capable of applying a shearing force in a direction parallel to a support member (for example, copper foil) such as a roll coater or a transfer roll coater, or applying a compressive force in a direction perpendicular to the surface of the copper foil. Can be.
In the wiring board of the present invention, the support member can be provided on the surface of the insulating base material where the conductor member is not exposed. The material of the support member used here is not particularly limited as long as it has a certain degree of rigidity. For example, the support member can include at least one of a metal, a resin, and a ceramic. As the support member in the present invention, a metal plate or a plastic plate is particularly suitable.
As the metal plate, a copper plate, an iron plate, an aluminum plate and an alloy plate of these metals are economically preferable. In addition, as the plastic plate, a thermosetting resin plate, a thermoplastic resin plate, or the like can be used.
Here, the thermosetting resin includes phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2- (Hydroxyethyl) resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xylene resin, heat containing condensed polycyclic aromatic A curable resin or the like can be used.
Examples of the thermoplastic resin include polyethylene, polypropylene, polyolefin resin such as 4-methylpentene-1 resin, polybutene-1 resin, and high-pressure ethylene copolymer, styrene resin, polyvinyl chloride, polyvinylidene chloride, polyvinyl alcohol, and poly (vinyl alcohol). Acrylonitrile, polyacrylic plastic, diene plastic, polyamide, polyester, polycarbonate, polyacetal, fluoroplastic, polyurethane plastic, polystyrene thermoplastic elastomer, polyolefin thermoplastic elastomer, polyurethane thermoplastic elastomer, polyester Thermoplastic elastomer, Polyamide thermoplastic elastomer, Low crystalline 1,2-polybutadiene, Chlorinated polymer thermoplastic elastomer, Fluorine thermoplastic elastomer Stoma, or such as a thermoplastic elastomer, such as ion crosslinked thermoplastic elastomer can be used.
In addition, these resins, cloth woven with insulating fibers such as glass fiber or cellulose, those impregnated in non-woven paper, mixed with short fibers such as glass chopped strands and insulating whiskers, or What was molded into a film shape may be used as a support member.
The wiring member according to the present invention may be composed of only one wiring layer, a plurality of wiring layers, an interlayer insulating layer for insulating the wiring layers, and a wiring layer provided in the interlayer insulating layer. May be a multi-layer wiring structure including a via hole for connecting the wiring structure. The wiring layer can include a plurality of circuits, and can usually be formed by patterning a conductive film such as a copper foil by etching or the like. In the case of forming a multilayer wiring structure as a wiring member, the forming method is not particularly limited, and a normal thin film, such as repeating formation of a wiring layer, formation of an interlayer insulating layer and formation of a via hole a predetermined number of times, is used. A process can be used. The wiring layer is formed, for example, by forming a gold plating layer of a predetermined pattern on the surface of the conductor layer to be a wiring layer, and then etching the conductor layer using the gold plating layer as an etching resist to form a pattern. May go.
In the wiring board of the present invention, the conductor member is embedded in the insulating base material. The thickness of the conductor member is preferably from 0.01 mm to 0.15 mm, and the difference between the thickness of the insulating base material and the thickness of the conductor member is preferably greater than 0 mm and 0.1 mm or less. If the thickness of the conductor member is less than 0.01 mm, the thickness of the insulating base material in the semiconductor device finally obtained by mounting the semiconductor element on the conductor member may not be so thick as to obtain sufficient insulation. If it is thicker than .15 mm, the accuracy of forming the conductor member may not be sufficient. Further, the difference between the thickness of the insulating base material and the thickness of the conductive member is sufficient if one end of the conductive member is covered with the insulating base material, and if the thickness exceeds 0.1 mm, polishing for exposing the conductive member is performed. If the amount is too large, industrial production efficiency may be deteriorated. When the support member is provided on the back surface of the insulating base material, the thickness of the conductive member and the thickness of the insulating base material may be the same (that is, the state where the conductive member penetrates the insulating base material). .
In the wiring board of the present invention in which the conductor member is embedded in the insulating base material, the insulating base material can be provided to a process such as mounting of a semiconductor element in a relatively thick state. Sufficient strength to withstand the applied stress and the like can be obtained. In particular, it is preferable to provide a support member on the back surface of the insulating base material (the surface of the front and back sides on which the wiring member is not provided) because the strength increases. If the wiring board of the present invention in which the support member is provided on the back surface of the insulating base material is used, even if the wiring member or the insulating base material is thin, sufficient strength to withstand the stress or the like applied during the process or transportation thereof Can be obtained.
Further, according to the wiring board of the present invention, a part of the insulating base material is removed after the device is mounted, and the conductor member is exposed to form an external electrode, so that the thickness of the insulating base material in the finally obtained semiconductor device is obtained. Can be made thinner, which can contribute to downsizing of the package.
When a semiconductor device is manufactured using the wiring board of the present invention, a conductor member having an end exposed from an insulating base material is used as an external electrode. Can be formed.
The wiring board according to the present invention is a method for manufacturing a wiring board, comprising a laminating step of laminating a wiring member having a projecting conductor member on one of the front and back surfaces, and an insulating base material facing each other with the conductor member inside. Can be produced by Also, the wiring board of the present invention is a laminating step of laminating a conductor layer provided with a protruding conductor member on one of the front and back surfaces, and an insulating base material with the conductor member inside and facing each other; Can be manufactured by a method of manufacturing a wiring board including a wiring layer forming step of forming a wiring layer by removing unnecessary portions.
The bonding between the insulating base material and the wiring member is performed by, for example, using an uncured adhesive made of a thermosetting resin composition as the insulating base material, and superimposing the adhesive on the wiring member, and heating and pressing to cure the wiring member. Can be taken. When the adhesive before curing used as the insulating base material has no self-supporting property, the adhesive before curing may be formed on the surface of the support member and used as the insulating base material. In this case, the support member, the insulating base material, and the wiring member are laminated in this order, and a wiring board in which the conductor member is embedded in the insulating base material is obtained.
When a support member is provided on the wiring board, the laminating step is performed by opposing the surface of the wiring layer / conductor layer on which the conductor member is provided and the surface of the insulating base material on which the support member is not provided. What is necessary is just to make it the process of making it laminate.
In the case where the wiring layer / conductor layer is too thin and has no self-supporting property, a temporary support plate may be provided on the other surface of the wiring layer / conductor layer (that is, the surface on which the conductor member is not provided). . In this case, it is preferable that the method for manufacturing a wiring board of the present invention further includes a step of removing the temporary support plate after the laminating step.
The conductor member according to the present invention is a protruding member provided on the wiring layer / conductor layer surface. This conductor member may be formed by plating or by removing a part of the conductor film.
Further, the method for manufacturing a wiring board of the present invention may further include an etching step of forming a wiring layer and / or a conductive member by removing a part of the conductive plate. In this case, as the conductor plate, a laminated plate including the first conductor layer, the second conductor layer, and the third conductor layer laminated in this order can be used. In the case of using such a three-layer laminate, the etching step includes etching a part of the first conductor layer to form a wiring layer, and etching a part of the third conductor layer. It is preferable to include a conductor member forming step of forming the conductor member, and an etching barrier removing step of etching and removing an exposed portion of the second conductor layer. Here, the wiring layer forming step may be a step of forming a gold plating pattern on the surface of the first conductor layer and forming the wiring layer by etching the first conductor layer using the plating pattern as an etching resist. it can.
The method for manufacturing a wiring board according to the present invention may further include a conductor member forming step of forming a conductor member by removing a part of the conductor plate. In this case, as the conductor plate, a laminated plate including the first conductor layer, the second conductor layer, and the third conductor layer laminated in this order can be used. In the case of using such a three-layer laminate, the conductor member forming step includes a step of forming a part of the third conductor layer by etching the part of the third conductor layer and a step of etching and removing an exposed portion of the second conductor layer. It is desirable to include a step.
The wiring board of the present invention is particularly suitable for mounting a semiconductor element to manufacture a resin-sealed semiconductor device. Therefore, in the present invention, the mounting step of mounting the semiconductor element on the surface of the wiring layer of the wiring board of the present invention, the connecting step of electrically connecting the semiconductor element and the wiring on the surface of the wiring layer, and A method of manufacturing a semiconductor device including an insulating base material removing step of exposing at least a part of the conductor member by removing a portion, and a semiconductor device manufactured by the method are provided. In the semiconductor device manufactured by the manufacturing method of the present invention, the conductor member functions as an external electrode (external connection terminal) of the semiconductor device.
In the case where the wiring substrate includes a supporting member, the above-described method for manufacturing a semiconductor device of the present invention further includes a supporting member removing step of removing at least a part of the supporting member and exposing at least a part of the insulating base material. It is desirable. The removal of the support member in the support member removal step can be performed, for example, by at least one of polishing, chemical etching, and machining.
The removal of the insulating base material in the insulating base material removing step can be performed by at least one of polishing, laser irradiation, and etching.
The conductor member at least partially exposed by removing the insulating base material functions as an external electrode. Therefore, after the insulating base material removing step, a step of forming a gold plating layer on the exposed portion of the conductor member and / or a step of forming a solder ball on the exposed portion of the conductor member may be further provided. When forming a gold plating layer, nickel plating may be performed as a base.
In the present invention, a plurality of semiconductor elements may be mounted on one wiring board, and passive components may be further mounted in addition to the semiconductor elements. The connection between the semiconductor element and the wiring of the wiring layer may be performed by wire bonding, or may be performed by flip element connection in which the bump of the element is directly connected to the wiring.
The method for manufacturing a semiconductor device of the present invention preferably further includes a sealing step of covering and sealing the semiconductor element with a sealing member. In this case, it is preferable to further include a step of polishing the sealing member to expose at least a part (for example, a back surface) of the semiconductor element. If a part of the semiconductor element is exposed as described above, a semiconductor device having excellent heat radiation characteristics can be obtained.
Specifically, the semiconductor device of the present invention can be obtained, for example, as follows. That is, first, a conductor layer (for example, a metal layer) in which a columnar conductor member to be an external electrode in the future is formed on a metal plate as a support member so that the conductor member is in contact with the support member, is an insulating base material. Laminate via adhesive resin. Next, an unnecessary portion of the metal layer is removed to form a wiring member including a wiring layer including a plurality of circuits. Thereby, the wiring board for mounting a semiconductor element of the present invention is obtained. Note that a plurality of wiring layers may be stacked with an interlayer insulating layer interposed therebetween so that the wiring member includes multilayer wiring. Subsequently, the semiconductor element is mounted on the obtained wiring board, and after the semiconductor element is electrically connected to the circuit of the wiring layer, the semiconductor element is sealed with resin (mold sealing), and the supporting member is removed. Thus, a resin-sealed semiconductor device is obtained.
Further, the columnar conductor member serving as the external electrode is formed by partially etching away a portion other than the portion serving as the conductor member from one surface of the relatively thick metal layer in the thickness direction to form the conductor member. The metal layer on which the member is formed and the support member are overlapped so that the conductor member is in contact with the support member, and bonded via an adhesive resin which is an insulating base material, and the metal layer on which the conductor member is formed is not etched. By removing an unnecessary portion of the metal layer of the remaining thickness portion by etching to form a wiring member made of a wiring layer, the wiring board for mounting a semiconductor element of the present invention can also be obtained. As described above, the semiconductor element is mounted on the obtained wiring board, and the semiconductor element is electrically connected to the circuit of the wiring layer. Then, the semiconductor element is sealed with resin (mold sealing), and the supporting member is removed. By doing so, a resin-sealed semiconductor device is obtained.
In the case of this method, as the above-mentioned relatively thick metal layer, the first conductor layer serving as a wiring layer, the third conductor layer serving as a conductor member, and the first and third conductor layers have different etching conditions. It is also possible to use a laminated film in which a second conductor layer and a first conductor layer / second conductor layer / third conductor layer are laminated in this order. That is, unnecessary portions of the third conductor layer of the three-layer laminated film are removed to form columnar conductor members serving as external electrodes, and the exposed second conductor layer is removed by etching. The three-layer laminated film on which the member is formed and the support member are overlapped so that the conductor member is in contact with the support member, and bonded via an adhesive resin as an insulating base material to remove unnecessary portions of the first conductor layer. By forming a wiring member composed of a wiring layer including a plurality of circuits, the wiring board for mounting a semiconductor element of the present invention can be obtained. As described above, the semiconductor element is mounted on the obtained wiring board, and the semiconductor element is electrically connected to the circuit of the wiring layer. Then, the semiconductor element is sealed with resin (mold sealing), and the supporting member is removed. By doing so, a resin-sealed semiconductor device is obtained.
As described above, when a semiconductor device is manufactured using a wiring board having a support member, the end of the conductor member can be easily formed by polishing the surface of the insulating base material after removing the support member after mounting the element. Can be exposed. After removing the support member, the embedded conductor member may be irradiated with laser to expose a part thereof.
In the present invention, a semiconductor device can also be manufactured using the wiring board of the present invention without a conductor member. That is, a wiring board is used in which a wiring member, an insulating base material, and a support member are laminated in this order, a semiconductor element is mounted on the wiring board, and the semiconductor element and the wiring on the surface of the wiring member are electrically connected. Removing at least a portion of the support member to expose at least a portion of the insulating base material, removing at least a portion of the insulating base material to form a through-hole, and exposing at least a portion of the wiring; A semiconductor device can be obtained by filling a hole with a conductor to form a conductor member connected to a wiring.
Note that the through holes may be formed by any method such as polishing, etching, and laser processing. For example, when a laser is irradiated to form a through hole, the type of laser is not particularly limited, and a carbon dioxide laser, a UV-YAG laser, or the like can be used as appropriate.
The drilling conditions may be appropriately adjusted depending on the thickness and material of the insulating base material and the wiring layer, and are preferably determined experimentally. The energy amount of the laser to be irradiated is in the range of 0.001 W to 1 W, and it is preferable to control the laser oscillation power supply so that a large amount of energy is not concentrated at once by applying a pulsed power.
In order to make a through hole reaching the wiring of the wiring member and to make the hole diameter as small as possible, the laser should be driven at a pulse waveform duty ratio of 1/1000 to 1/10 for driving a power supply for laser oscillation. It is preferable to irradiate up to 20 shots (pulses). If the waveform duty ratio is less than 1/1000, it takes too much time to drill holes, which is not efficient. If it exceeds 1/10, the irradiation energy is too large and the hole diameter becomes 1 mm or more, which is not practical. is there. The number of shots (pulses) may be experimentally determined as a number that allows the adhesive in the holes to evaporate to reach the inner layer circuit. Even if the pulse duty ratio of the pulse is close to 1/1000, the hole diameter becomes large and may not be practical.
After forming the through-holes in this manner, desmearing is desirably performed to remove the adhesive residue in the through-holes. For this desmear treatment, a general acidic oxidizing roughening solution or an alkaline oxidizing roughening solution can be used. For example, as the acidic oxidizing roughening solution, there is a chromium / sulfuric acid roughening solution, and as the alkaline oxidizing roughening solution, a potassium permanganate roughening solution or the like can be used.
Further, it is desirable that after the adhesive is roughened with an oxidizing roughening liquid, the oxidizing roughening liquid on the surface of the insulating resin is chemically neutralized, but this can also adopt a general method. For example, when a roughening solution of chromium / sulfuric acid is used, the solution is treated with 10 g / l of sodium bisulfite at room temperature for 5 minutes, and when a roughening solution of potassium permanganate is used, 150 ml / l of sulfuric acid and peroxide are used. For example, it is immersed in an aqueous solution of 15 ml / l of hydrogen water at room temperature for 5 minutes to complete the neutralization.
Example
<Example 1>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 1A to 1G.
First, a 0.001 mm thick nickel layer (not shown) was plated on one of the front and back surfaces of a 0.035 mm thick electrolytic copper foil, and then a 0.009 mm thick copper film was plated on the surface. . Next, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the other surface of the electrolytic copper foil, exposed and developed to form a bump pattern. Was etched with an alkali etchant to form a bump (conductor member) 3 having a height of 0.035 mm, the resist was peeled off, and the exposed nickel layer was removed with a nickel etching solution having a low copper etching rate.
Subsequently, the obtained copper film with bumps 3 and a metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm as a supporting member were bonded to an adhesive 2 having a thickness of 0.05 mm (Hitachi, an insulating base material). Press lamination was performed via SPAI manufactured by Kasei Kogyo Co., Ltd. so that the bumps 3 were embedded in the adhesive 2.
Next, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the copper plating film, exposed and developed to form a resist pattern for wiring plating. Nickel (not shown) having a thickness of 0.003 mm or more and gold (not shown) having a thickness of not less than 99.9% and having a thickness of not less than 0.0003 mm, and etching copper with an alkali etchant to form a wiring pattern A wiring member 4 as a wiring layer was obtained. Thereby, the wiring board 110 shown in FIG. 1A was obtained.
Subsequently, an LSI (Large Scale Integrated Circuit) element 6 is mounted on a wiring board 110 having a wiring 4 with a built-in bump 3 using a non-conductive adhesive film (die bonding material) 5 for a semiconductor. (FIG. 1b), the terminal of the LSI element and the wiring terminal 4 were connected by a wire 100 (FIG. 1c).
The assembly thus formed is set in a transfer mold, sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.), and the metal sheet 1 is removed by etching. After exposing the surface of the adhesive 2 (FIG. 1e), the surface of the adhesive was polished to expose the top of the bump (FIG. 1f).
Finally, solder balls 8 were arranged on the tops of the exposed bumps and reflowed to obtain a resin-sealed semiconductor device 120 shown in FIG. 1g. The solder ball 8 is of a fan-in type disposed inside the LSI element 6. In the obtained semiconductor device 120, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 2>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 2A to 2F.
In the same manner as in Example 1, a wiring board 110 including the metal support member 1, the wiring 4, and the bumps 3 is manufactured (FIG. 2A). After mounting the element 6 and interconnecting the gold bump 200 and the wiring 4 by thermocompression bonding (FIG. 2B), a liquid epoxy resin (underfill material) 11 is applied between the LSI element 6 and the wiring board. Filled and cured (FIG. 2c).
The assembly thus manufactured is mounted on a transfer mold and sealed with a semiconductor sealing epoxy resin 7 (CEL400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 2D), and then a metal supporting member is formed. Only the sheet 1 was removed with an acid-based etching solution to expose the adhesive 2.
Subsequently, after the adhesive layer 2 as an insulating base material is mechanically polished so that the top of the bump 3 is exposed (FIG. 2E), the solder ball 8 is arranged on the top of the bump 3 and is positioned at that position. The resin was melted again to obtain a resin-sealed semiconductor device 130 shown in FIG. 2F. In the obtained semiconductor device 130, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 3>
In this example, a resin-encapsulated semiconductor device was manufactured as shown in FIGS. 3A to 3F.
First, a nickel layer (not shown) having a thickness of 0.001 mm is formed on one surface of an electrolytic copper foil having a thickness of 0.020 mm by plating, and a copper layer having a thickness of 0.012 mm is formed on the surface of the nickel layer. A film was formed by plating. Next, after laminating a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) on the other surface of the electrolytic copper foil, exposing and developing, and forming an etching pattern of the bump 3, The bumps 3 (0.020 mm in height) as conductor members were formed by etching with an alkali etching solution.
Subsequently, the obtained copper film with bumps 3 and a metal sheet 1 (stainless steel SUS304) having a thickness of 0.100 mm were bonded to an adhesive 2 having a thickness of 0.030 mm as an insulating base material (Hitachi Chemical Industry Co., Ltd.). ) Press lamination via SPAI) such that the bumps 3 were embedded in the adhesive 2.
Next, a photosensitive dry film resist (Photech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper film, exposed and developed to form an etching pattern of the wiring 4, and then an alkaline etching solution is used. The wiring 4 was formed by etching. Subsequently, the resist was removed, and the nickel layer was removed with a nickel selective etching solution.
Next, a liquid coating resin is applied on the wiring 4 by a screen printing method, and an insulating layer (solder resist) 10 is formed so as to expose a connection portion of the wiring 4. A nickel film (not shown) having a thickness of 003 mm or more and a gold film (not shown) having a purity of 99.9% or more and a thickness of 0.0003 mm or more were sequentially laminated by plating. Thus, the wiring substrate 300 shown in FIG. 3A was obtained.
Subsequently, the LSI element 6 is mounted on the surface of the insulating layer 10 of the obtained wiring board 300 using the silver paste 5 for a semiconductor (FIG. 3B), and the terminals of the LSI element 6 and the wiring 4 are connected by the bonding wires 100. (FIG. 3c).
The assembly thus formed was set in a transfer mold, and sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 3D). Thereafter, the metal sheet 1 serving as the support member was removed by etching, the surface of the adhesive 2 was exposed (FIG. 3E), and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3.
Finally, the solder balls 8 were arranged on the tops of the bumps 3 and reflowed to obtain a resin-sealed semiconductor device 310 shown in FIG. 3F. In the obtained semiconductor device 310, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 4>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 4A to 4G.
First, a nickel layer (not shown) having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil having a thickness of 0.035 mm, and a copper film having a thickness of 0.009 mm was plated on the surface of the nickel layer. Next, a photosensitive dry film resist (Photec RY-3025, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the other surface of the electrolytic copper foil, exposed and developed to form an etching pattern of the bump 3. Subsequently, after the copper foil was etched with an alkali etching solution to form the bumps 3, the resist was removed, and the nickel layer was removed with a nickel selective etching solution.
Next, the obtained copper film with bumps 3 and a metal sheet 1 (stainless steel SUS304) having a thickness of 0.100 mm were bonded to an adhesive 2 (SPAI manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 0.040 mm. Then, press lamination was performed so that the bumps 3 were embedded in the adhesive 2. Subsequently, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper film, exposed and developed to form an etching pattern of the pad 4a. The film was etched to form a pad 4a constituting a wiring layer. Subsequently, after removing the resist and removing the nickel layer with a nickel selective etching solution, a nickel film (not shown) having a thickness of 0.003 mm or more, a purity of 99.9% or more, and a thickness of 0.1 mm are formed on the surface of the pad 4a. Gold films (not shown) of 0003 mm or more were sequentially plated. Thereby, the wiring board 400 shown in FIG. 4A was obtained.
Subsequently, the LSI element 6 is mounted on the surface of the adhesive 2 which is an insulating base material of the obtained wiring board 400 using the silver paste 5 for semiconductor (FIG. 4B), and the terminals of the LSI element 6 and the wiring 4 are connected. The connection was made by a bonding wire 100 (FIG. 4c).
The assembly thus formed was set in a transfer mold and sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 4D). Thereafter, the metal sheet 1 as a support member was removed by etching, the surface of the adhesive 2 was exposed (FIG. 4E), and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3 (FIG. 4E). 4f).
Finally, the solder balls 8 were arranged on the tops of the bumps 3 and reflowed to obtain a resin-sealed semiconductor device 410 shown in FIG. 4g. The solder balls 8 are of a fan-out type arranged outside the LSI element 6. In the obtained semiconductor device 410, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 5>
In this example, a resin-encapsulated semiconductor device was manufactured as shown in FIGS. 5A to 5F.
First, a wiring board 500 was manufactured in the same manner as in Example 1. However, in the first embodiment, the bumps 3 are formed in the inner region of the wiring 4 (that is, the wiring portion on the side closer to the element mounting region). However, in the present embodiment, as shown in FIG. (I.e., the wiring portion far from the element mounting region).
Subsequently, after the LSI element 6 is mounted on the element mounting area of the wiring substrate 500 via the semiconductor non-conductive film 5a (FIG. 5B), the terminal of the LSI element 6 and the connection area of the wiring 4 are connected with the bonding wire 100. (FIG. 5c). In this embodiment, the connection region of the wiring 4 is provided inside the bump 3 (that is, on the side closer to the element 6).
The assembly thus formed was set in a transfer mold and sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 5D). Thereafter, the metal sheet 1 serving as the support member was removed by etching, the surface of the adhesive 2 was exposed, and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3 (FIG. 5E).
Finally, the solder balls 8 were arranged on the tops of the bumps 3 and reflowed to obtain a resin-sealed semiconductor device 510 shown in FIG. 5F. The solder balls 8 are of a fan-out type arranged outside the LSI element 6. In the obtained semiconductor device 510, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 6>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 6A to 6G.
First, a nickel layer (not shown) having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil having a thickness of 0.018 mm, and then a copper film having a thickness of 0.009 mm was plated on the surface of the nickel layer. . Next, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper plating film, exposed and developed to form an etching pattern of the wiring 21, and then alkali etching is performed. The wiring 21 was formed by etching the copper plating film with the solution.
The obtained electrolytic copper foil with the wiring 21 and a metal sheet 1 (stainless steel SUS304) having a thickness of 0.025 mm are connected to each other via an adhesive 2 having a thickness of 0.025 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Then, press lamination was performed so that the wiring 21 was embedded in the adhesive 2.
Next, only the copper foil is etched with an alkaline etchant to expose the nickel layer, and the nickel layer is removed with a nickel stripper having a low copper etching property to expose the copper wiring 21, and then the surface of the copper wiring 21 is exposed. Then, a nickel film having a thickness of 0.003 mm or more and a gold film having a purity of 99.9% or more and a thickness of 0.0003 mm or more were formed by plating. As a result, the semiconductor element mounting wiring board 600 shown in FIG. 6A was obtained.
Subsequently, the LSI element 6 is mounted on the insulating substrate side surface of the obtained wiring board 600 by using the non-conductive film for semiconductor 5a (FIG. 6B), and the terminals of the LSI element 6 and the wiring 4 are bonded with bonding wires. 100 (FIG. 6c).
The assembly thus formed was set in a transfer mold and sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 6D). Thereafter, the metal sheet 1 serving as a support member is removed by etching, the surface of the adhesive 2 is exposed (FIG. 6E), a predetermined portion of the adhesive 2 is irradiated with a laser to form a through hole 61, and a wiring 21 is formed. A portion was exposed (FIG. 6f).
Finally, the solder was placed on the exposed portion of the wiring 21 at the bottom of the through hole 61 and reflowed. As a result, the conductor member 62 filled with solder was formed in the through-hole 61, and the solder ball 8 was formed at the end thereof. Thus, the resin-sealed semiconductor device 610 shown in FIG. 6G was obtained. The solder balls 8 are of a fan-in type arranged inside the LSI element 6. In the obtained semiconductor device 610, the wiring 21 is connected to the external wiring via the conductor member 62 and the solder ball 8.
<Example 7>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 7A to 7G.
First, a metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm, a copper foil having a thickness of 0.012 mm and an adhesive film 2 having a thickness of 0.025 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.) And press-laminated. Next, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the copper foil, exposed and developed, and a plating resist pattern for forming the wiring 4 was formed. .
Subsequently, a nickel film having a thickness of 0.003 mm or more and a gold film having a thickness of 0.0003 mm or more and a purity of 99.9% or more are sequentially laminated on exposed portions of the copper foil by plating, and then the plating resist is peeled off. Then, the copper was etched with an alkali etchant using gold plating as an etching resist to obtain a wiring pattern 4. Thereby, the wiring board 700 shown in FIG. 7A was obtained.
Using this wiring board 700, an LSI element 6 having a gold bump 200 on a terminal portion is mounted in the same manner as in Example 2, and the gold bump 200 and the wiring 4 are interconnected by thermocompression bonding (FIG. 7B). ) The liquid epoxy resin 11 was filled between the LSI element 6 and the wiring board and cured (FIG. 7C), and sealed with a semiconductor sealing epoxy resin (CEL400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 7D).
Thereafter, the metal sheet 1 serving as a support member is removed by etching, the surface of the adhesive 2 is exposed (FIG. 7E), a predetermined portion of the adhesive 2 is irradiated with a laser to make a through hole 61, and a wiring 4 is formed. A portion was exposed (FIG. 7f).
Finally, the solder was placed at the exposed portion of the wiring 4 at the bottom of the through hole 61 and reflowed. As a result, the conductor member 62 filled with solder was formed in the through-hole 61, and the solder ball 8 was formed at the end thereof. Thus, the resin-sealed semiconductor device 710 shown in FIG. 7G was obtained. The solder balls 8 are of a fan-in type arranged inside the LSI element 6. In the obtained semiconductor device 710, the wiring 4 is connected to the external wiring via the conductor member 62 and the solder ball 8.
Example 8
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 8A to 8F.
First, a photosensitive dry film resist (FOTEC RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on a copper foil having a thickness of 0.012 mm, exposed, and developed to form a plating resist pattern of the bump 3. Next, after the exposed portion of the copper foil was subjected to copper plating using a copper sulfate plating bath, the plating resist was peeled off to obtain a plated bump 3.
The obtained copper foil with the bumps 3 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were connected via an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Press lamination was performed so that the bumps 3 were embedded in the adhesive 2. Subsequently, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the copper foil side, exposed, and developed to form a plating resist pattern for the wiring 4.
Next, a nickel film having a thickness of 0.003 mm or more and a gold film having a thickness of 0.0003 mm or more and a purity of 99.9% or more are sequentially laminated by plating on the exposed portion of the copper foil, and then the copper foil is removed with an alkali etchant. By etching, a wiring pattern 4 was obtained. As a result, a wiring board 800 in which the bumps 3 shown in FIG. 8A were embedded in the insulating base material 2 was obtained.
Subsequently, the LSI element 6 is mounted on the insulating substrate side surface of the obtained wiring board 800 using the non-conductive adhesive film for semiconductor 5a (FIG. 8B), and the terminals of the LSI element 6 and the wiring 4 are connected. The connection was made by a bonding wire 100 (FIG. 8c).
The assembly thus formed was set in a transfer mold, and sealed with a semiconductor sealing resin 7 (CEL-400, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 8D). Thereafter, the metal sheet 1 as a support member was removed by etching, the surface of the adhesive 2 was exposed, and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3 (FIG. 8E).
Finally, the solder balls 8 were arranged on the tops of the bumps 3 and reflowed to obtain a resin-sealed semiconductor device 810 shown in FIG. 8F. The solder balls 8 are of a fan-in / out type that are arranged inside and outside the LSI element 6. In the obtained semiconductor device 810, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 9>
In this example, a resin-encapsulated semiconductor device was manufactured as shown in FIGS. 9A to 9G.
First, a nickel layer (not shown) having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil having a thickness of 0.035 mm, and a copper film having a thickness of 0.009 mm was plated on the surface of the nickel layer. Next, a photosensitive dry film resist (FOTEC RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the electrolytic copper foil, exposed, and developed to form an etching resist pattern for forming the bumps 3. Next, the electrolytic copper foil was etched with an alkali etchant to form a bump 3 having a height of 0.035 mm, the resist was peeled off, and the exposed nickel was removed with a nickel etching solution having a low copper etching rate.
Subsequently, the obtained copper film with the bumps 3 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded with an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Then, press lamination was performed so that the bumps 3 were embedded in the adhesive 2. Thereafter, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the copper film side, exposed, and developed to form a plating resist pattern for forming the wiring 4 to form a copper film. Exposed portions were sequentially plated with a nickel film having a thickness of 0.003 mm or more and a gold film having a thickness of 0.0003 mm or more and a purity of 99.9% or more. Next, after the plating resist was removed, copper was etched with an alkaline etchant to obtain a wiring pattern 4. As a result, a wiring substrate 900 in which the bumps 3 shown in FIG. 9A were embedded in the insulating base material 2 was obtained.
Subsequently, a plurality of LSI elements 6 are mounted on the insulating substrate side surface of the obtained wiring board 900 using the non-conductive adhesive film for semiconductor 5a (FIG. 9B). The wiring 4 was connected by a bonding wire 100 (FIG. 9C).
The assembly thus formed is set in a transfer mold, and all the elements 6 are collectively sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 9D). The metal sheet 1 as a support member was removed by etching to expose the surface of the adhesive 2 (FIG. 9E).
Subsequently, the exposed surface of the adhesive 2 was polished to expose the top of the bump 3, and the solder ball 8 was arranged on the top of the bump 3 and reflowed (FIG. 9f). The solder balls 8 are of a fan-in type arranged inside the LSI element 6. Finally, the sealed assembly 910 was cut into individual pieces to obtain a plurality of resin-sealed semiconductor devices 920 shown in FIG. 9g. In the obtained semiconductor device 920, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 10>
In this example, a resin-sealed semiconductor device was manufactured as shown in FIGS. 10A to 10F.
First, after a nickel layer (not shown) having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil having a thickness of 0.035 mm, copper having a thickness of 0.009 mm was plated on the surface of the nickel layer. Next, a photosensitive dry film resist (FOTEC RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the electrolytic copper foil, exposed, and developed to form an etching resist pattern for forming the bumps 3. Next, the electrolytic copper foil was etched with an alkali etchant to form a bump 3 having a height of 0.035 mm, the resist was peeled off, and the exposed nickel was removed with a nickel etching solution having a low copper etching rate.
Subsequently, the obtained copper film with the bumps 3 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded with an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Then, press lamination was performed so that the bumps 3 were embedded in the adhesive 2.
Next, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the copper film, exposed, and developed to form a plating resist pattern for forming the wiring 4. Subsequently, a nickel film having a thickness of 0.003 mm or more and a gold film having a thickness of not less than 0.0003 mm and a purity of 99.9% or more are sequentially plated on the exposed portions of the copper film, and a plating resist is peeled off. The wiring pattern 4 was obtained by etching the copper with an etchant. As a result, a wiring board 1000 in which the bumps 3 shown in FIG.
Subsequently, a plurality of LSI elements 6 are mounted on the insulating substrate side surface of the obtained wiring board 1000 using the non-conductive adhesive film for semiconductor 5a (FIG. 10b), and the terminals of each LSI element 6 are The wiring 4 was connected by a bonding wire 100 (FIG. 10c).
The assembly thus formed is set in a transfer mold, and all the elements 6 are collectively sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 10D). The metal sheet 1 as a support member was removed by etching, the surface of the adhesive 2 was exposed, and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3 (FIG. 10E).
Finally, after the solder balls 8 were arranged on the tops of the bumps 3 and reflowed, the sealed assembly was cut into individual pieces to obtain a plurality of semiconductor devices 1010 shown in FIG. 10F. The solder balls 8 are of a fan-in / out type arranged inside and outside the LSI element 6. In the obtained semiconductor device 1010, the wiring 4 is connected to an external wiring via the bump 3 and the solder ball 8.
<Example 11>
In this example, a resin-encapsulated semiconductor device was manufactured as shown in FIGS. 11A to 11F.
First, after a nickel layer (not shown) having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil having a thickness of 0.035 mm, copper having a thickness of 0.009 mm was plated on the surface of the nickel layer. Next, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the electrolytic copper foil, exposed and developed to form an etching resist pattern for forming bumps 3. Subsequently, the copper was etched with an alkaline etchant to form a bump 3 having a height of 0.035 mm, the resist was peeled off, and the exposed nickel was removed with a nickel etching solution having a low copper etching rate.
Next, the obtained copper film with the bumps 3 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded with an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Then, press lamination was performed so that the bumps 3 were embedded in the adhesive 2.
Subsequently, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper film, exposed and developed to form a plating resist pattern for forming the wiring 4, and then the copper film is formed. The nickel film having a thickness of not less than 0.003 mm and the gold film having a thickness of not less than 0.0003 mm and a purity of not less than 99.9% were sequentially plated and laminated on the exposed portions. Next, after removing the resist pattern, copper was etched with an alkali etchant to obtain a wiring pattern 4. As a result, a wiring board 1100 in which the bumps 3 shown in FIG.
Subsequently, a plurality of LSI elements 6 are mounted on the insulating substrate side surface of the obtained wiring board 1100 using the non-conductive adhesive film for semiconductor 5a (FIG. 11b), and the terminals of each LSI element 6 are The wiring 4 was connected by a bonding wire 100 (FIG. 11c).
The assembly thus formed is set in a transfer mold, and all the elements 6 are collectively sealed with a semiconductor sealing resin 7 (CEL-400 manufactured by Hitachi Chemical Co., Ltd.) (FIG. 11D). The metal sheet 1 as a support member was removed by etching, the surface of the adhesive 2 was exposed, and the exposed surface of the adhesive 2 was polished to expose the top of the bump 3 (FIG. 11e).
Finally, nickel gold was flash-plated on the exposed tops of the bumps 3 to form the terminals 9, and the sealed assembly was cut into individual pieces to obtain a plurality of semiconductor devices 1110 shown in FIG. 11f. The terminal 9 is of a fan-in / out type disposed inside and outside the LSI element 6. In the obtained semiconductor device 1110, the wiring 4 is connected to an external wiring via the bump 3 and the terminal 9.
<Example 12>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS. 12A to 12G.
First, a nickel layer 32 having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil 31 having a thickness of 0.035 mm, and then a copper film 33 having a thickness of 0.009 mm was plated on the surface of the nickel layer (FIG. 12a). Next, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the electrolytic copper foil 31, exposed and developed to form an etching pattern 34 for forming the bump 42 (FIG. 12b). Subsequently, the copper foil is etched with an alkali etchant to form a bump 35 having a height of 0.035 mm (FIG. 12C), the resist 34 is peeled off, and the exposed nickel 32 is removed by a nickel etching solution having a low copper etching rate. (FIG. 12d).
Next, the obtained copper film 33 with the bump 42 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Was press-laminated so that the bumps 42 were embedded.
Subsequently, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper film 33, exposed and developed to form a plating resist pattern 37 for forming the wiring 4, and then the copper is formed. At the exposed portion of the film 33, a nickel film 35 having a thickness of 0.003 mm or more and a gold film 36 having a thickness of 0.0003 mm or more and a purity of 99.9% or more were sequentially laminated by plating. Next, after the plating resist 37 was peeled off, the exposed portion of the copper film 33 was removed by etching with an alkali etchant to obtain a wiring pattern 4 having a three-layer structure including the copper foil 33, the nickel film 35, and the gold film 36. As a result, a wiring board 1200 shown in FIG. 12G was obtained.
<Example 13>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS. 13A to 13G.
First, after a nickel layer 32 having a thickness of 0.001 mm is plated on one surface of an electrolytic copper foil 41 having a thickness of 0.035 mm, a photosensitive dry film resist (Hitachi Chemical Industry Co., Ltd.) is formed on the surface of the nickel layer 32. (Phototec H-9050) was laminated, exposed and developed to form a plating resist pattern 44 for forming the bump 43 (FIG. 13B). Subsequently, a copper film having a thickness of 0.035 mm is plated on the exposed portion of the nickel layer 32 to form a bump 43 (FIG. 13C), the resist 44 is peeled off, and the exposed nickel layer 32 is etched at a copper etching rate. Was removed with a slow nickel etchant (FIG. 13d).
Next, the obtained copper foil 41 with the bump 43 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Thus, press lamination was performed so that the bumps 43 were embedded in the adhesive 2 (FIG. 13E).
Subsequently, a photosensitive dry film resist (Photech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 41, exposed and developed, and a plating resist pattern 37 for forming the wiring 4 is formed. A nickel film 35 having a thickness of 0.003 mm or more and a gold film 36 having a thickness of 0.0003 mm or more and a purity of 99.9% or more were sequentially plated and laminated on the exposed portions of the foil 41 (FIG. 13F). Next, after the plating resist 37 was peeled off, the copper foil 41 was etched with an alkaline etchant to obtain a wiring pattern 4 having a three-layer structure including the copper foil 33, the nickel film 35, and the gold film 36. Thus, a wiring board 1300 shown in FIG. 13G was obtained.
<Example 14>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS.
First, a photosensitive dry film resist (Photec H-9050 manufactured by Hitachi Chemical Co., Ltd.) is laminated on one side of an electrolytic copper foil 31 having a thickness of 0.035 mm, exposed and developed, and a plating resist pattern for forming the bump 43 is formed. 44 were formed (FIG. 14b). Subsequently, a 0.035 mm-thick copper film was formed on the exposed portion of the copper foil 31 by plating to obtain a bump 43 (FIG. 14C), and the resist 44 was peeled off (FIG. 14D).
Next, the obtained copper foil 31 with the bump 43 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Thus, press lamination was performed so that the bumps 43 were embedded in the adhesive 2 (FIG. 14E).
Subsequently, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 31, exposed and developed to form a plating resist pattern 37 for forming the wiring 4; A nickel film 35 having a thickness of 0.003 mm or more and a gold film 36 having a thickness of 0.0003 mm or more and a purity of 99.9% or more were sequentially plated and laminated on the exposed portions of the copper foil 31 (FIG. 14F). . Next, after the plating resist 37 was peeled off, the exposed portions of the copper foil 31 were removed by etching with an alkali etchant to obtain a wiring pattern 4 having a three-layer structure including the copper foil 31, the nickel film 35, and the gold film 36. Thus, the wiring board 140 shown in FIG. 14G was obtained.
<Example 15>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS. 15A to 15G.
First, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on one side of an electrolytic copper foil 31 having a thickness of 0.035 mm, exposed and developed, and an etching resist for forming the bump 40 is formed. A pattern 34 was formed (FIG. 15b). Subsequently, after the copper foil 31 was etched to a depth of 0.030 mm to form the bumps 40 (FIG. 15C), the resist 34 was peeled off (FIG. 15D).
Next, the obtained copper foil 31 with the bump 40 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Thus, press lamination was performed so that the bumps 40 were embedded in the adhesive 2 (FIG. 15E).
Subsequently, a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 31, exposed and developed to form a plating resist pattern 37 for forming the wiring 4 ( In FIG. 15f), a nickel film having a thickness of 0.003 mm or more and a gold film having a thickness of 0.0003 mm or more and a purity of 99.9% or more were sequentially laminated on the exposed portions of the copper foil 31. Next, after the plating resist 37 was removed, the exposed portions of the copper foil 31 were etched with an alkali etchant to obtain a wiring pattern 4 having a three-layer structure including the copper foil 31, the nickel film 35, and the gold film 36. Thus, the wiring board 150 shown in FIG. 15G was obtained.
<Example 16>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS.
First, a nickel layer 32 having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil 31 having a thickness of 0.035 mm, and a copper film 33 having a thickness of 0.009 mm was plated on the surface of the nickel layer 32. (FIG. 16a). Next, after laminating a photosensitive dry film resist (Fotech RY-3025 manufactured by Hitachi Chemical Co., Ltd.) on the surface of the copper film 33, exposing and developing, and forming an etching resist pattern 37 for forming the wiring 4 ( 16B), the exposed portion of the copper film 33 was removed by etching, and the resist pattern 37 was peeled off to form the wiring 4 (FIG. 16C).
Next, a photosensitive dry film resist (Photec H-9050, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the nickel layer 32 exposed between the wirings 4 and exposed, developed, and bumped. After forming a plating resist pattern 34 for forming 46 (FIG. 16d), copper having a thickness of 0.035 mm was plated on exposed portions of the wiring 4 to form bumps 46 (FIG. 16e), and the resist 34 was peeled off.
Subsequently, the obtained copper foil 31 with the wiring 4 and the bump 46 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (Hitachi Chemical Industry Co., Ltd.). After press-laminating the bumps 46 in the adhesive 2 by SPAI (FIG. 16g), the copper foil 31 is etched with an alkaline etchant to expose the nickel layer 32, and the exposed nickel layer 32 is It was removed by a nickel etching solution having a low etching rate. Next, a nickel film (not shown) having a thickness of 0.003 mm or more and a gold film (not shown) having a thickness of not less than 0.0003 mm and a purity of 99.9% or more were plated on the surface of the wiring 4. Thus, the wiring board 160 shown in FIG. 16H was obtained.
<Example 17>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS. 17A to 17E.
First, a nickel layer 32 having a thickness of 0.001 mm was plated on one surface of an electrolytic copper foil 31 having a thickness of 0.035 mm, and then a copper film 33 having a thickness of 0.009 mm was plated on the surface of the nickel layer 32. Next, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the electrolytic copper foil 31, exposed and developed to form an etching resist pattern for forming the bumps 3. Subsequently, the exposed portions of the copper foil 31 were etched with an alkali etchant to form the bumps 3 having a height of 0.035 mm, and then the resist was removed.
Next, the obtained copper film 33 with the bump 3 and the metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded to an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Was press-laminated so that the bumps 3 were embedded in the adhesive 2.
Subsequently, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper film 33, exposed and developed, and an etching resist pattern for forming the wiring 4 is formed. The exposed portion of the film 33 was etched with an alkali etchant to form the first layer wiring 4, and the exposed nickel layer 32 was selectively etched away (FIG. 17a).
Next, an RCC (resin-coated copper foil) 46 is laminated so as to cover the wiring 4 to form a resin layer 39 and a copper layer 45 (FIG. 17b), and then a photosensitive dry film resist (Hitachi Chemical Co., Ltd.) is formed on the surface of the copper layer 45. Industrial Co., Ltd., Photek RY-3025) was laminated, exposed and developed to form an etching resist pattern for the through hole 47 for the via hole 48.
Subsequently, the exposed copper layer 45 is etched with an acid etchant, and CO 2 After forming a through hole 47 having a diameter of 0.15 mm reaching the first layer wiring 4 in the copper layer 45 and the resin layer 39 by laser drilling, the inside of the through hole 47 is cleaned by an ordinary method, and A via hole 48 was formed by forming a copper plating film 49 with a thickness of 0.015 mm on the inner wall of the hole 47 (FIG. 17D).
Next, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper plating film 49, exposed and developed to form an etching resist pattern for forming the wiring 4 and then exposed. The copper layers 49 and 45 at the locations were etched with an alkali etchant to form a second-layer wiring 4 composed of the copper layers 49 and 45. Next, a nickel film (not shown) having a thickness of 0.003 mm or more and a gold film (not shown) having a thickness of 0.0003 mm or more and a purity of 99.9% or more are formed on the surface of the second-layer wiring 4. Plated. Thus, the wiring board 170 shown in FIG. 17E was obtained.
<Example 18>
In this example, a wiring board for mounting a semiconductor element was manufactured as shown in FIGS.
First, after plating a nickel layer 32 having a thickness of 0.001 mm on one surface of an electrolytic copper foil 31 having a thickness of 0.035 mm, a copper film 33 having a thickness of 0.009 mm was plated on the surface of the nickel layer 32. (FIG. 18a). Next, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the copper film 33, exposed and developed to form an etching resist pattern for forming the wiring 4. Subsequently, the exposed portion of the copper film 33 was etched with an alkali etchant to form the first layer wiring 4, and then the resist was stripped (FIG. 18B).
Next, an RCC (resin-coated copper foil) 46 was laminated on the surface of the obtained copper foil 31 with the wiring 4 so as to cover the wiring 4 to form a resin layer 39 and a copper layer 45 (FIG. 18C). . Subsequently, a photosensitive dry film resist (Photec RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper layer 45, exposed and developed to form an etching resist pattern of the through hole 47 for forming the via hole 48. did. Next, the exposed portion of the copper layer 45 is etched with an acid etchant, and CO 2 is added to the resin layer 39. 2 After forming a through hole 47 having a diameter of 0.15 mm reaching the first layer wiring 4 in the copper layer 45 and the resin layer 39 (FIG. 18D), the inside of the through hole 47 is cleaned by a normal method. A copper plating film 49 having a thickness of 0.015 mm was formed on the inner wall of the through hole 47 to form a via hole 48 (FIG. 18E).
Next, a photosensitive dry film resist (FOTEC RY-3025 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper plating film 49 and the surface of the copper foil 31, exposed and developed, and an etching resist pattern for forming the wiring 4 is formed. An etching resist pattern for forming the bump 3 was formed.
Subsequently, the exposed copper layers 49 and 45 and the copper foil 31 are etched with an alkali etchant to form a second-layer wiring 4 composed of the copper layers 49 and 45, and the bumps 3 are formed. After removal by selective etching, the resist was stripped (FIG. 18f).
Next, the obtained wiring member with bumps 3 and a metal sheet 1 (stainless steel SUS304) having a thickness of 0.050 mm were bonded with an adhesive 2 having a thickness of 0.05 mm (SPAI manufactured by Hitachi Chemical Co., Ltd.). Press lamination was performed so that the bumps 3 were embedded in the adhesive 2. Subsequently, a nickel film (not shown) having a thickness of 0.003 mm or more and a gold film (not shown) having a thickness of 0.0003 mm or more and a purity of 99.9% or more are formed on the surface of the second layer wiring 4. Was plated. As a result, a wiring board 180 shown in FIG. 18g was obtained.
Industrial applicability
As described above, according to the present invention, a semiconductor device that can flexibly cope with miniaturization and high integration can be manufactured with good productivity and in a stable manner.
[Brief description of the drawings]
1A to 1G are cross-sectional views illustrating the steps of manufacturing a semiconductor device according to the present invention.
2A to 2F are cross-sectional views illustrating the steps of manufacturing a semiconductor device according to the present invention.
3A to 3F are cross-sectional views illustrating the steps of manufacturing a semiconductor device according to the present invention.
4A to 4G are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
5A to 5F are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
6A to 6G are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
7A to 7G are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
8A to 8F are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
9A to 9G are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
10A to 10F are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.
11a to 11f are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
12a to 12g are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
13A to 13G are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
14A to 14G are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
15A to 15G are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
16a to 16h are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
17A to 17E are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.
18A to 18G are cross-sectional views illustrating an example of a manufacturing process of a wiring board according to the present invention.

Claims (35)

絶縁基材と、
上記絶縁基材の表裏一方の面に設けられた配線を有する配線部材と、
上記絶縁基材内に埋め込まれた導体部材とを備え、
上記導体部材の一端は上記絶縁基材表面に露出して上記配線に接続しており、他端は上記絶縁基材内に埋め込まれている配線基板。An insulating substrate;
A wiring member having wiring provided on one of the front and back surfaces of the insulating base material,
A conductor member embedded in the insulating base material,
A wiring board in which one end of the conductor member is exposed on the surface of the insulating base and connected to the wiring, and the other end is embedded in the insulating base. 上記絶縁基材は、エポキシ樹脂硬化物又はポリアミドイミド樹脂硬化物を含む請求項１記載の配線基板。The wiring board according to claim 1, wherein the insulating base material includes a cured epoxy resin or a cured polyamideimide resin. 絶縁基材と、
上記絶縁基材の表裏一方の面に設けられた配線を有する配線部材と、
上記絶縁基材の他方の面に設けられた支持部材と、
上記絶縁基材内に埋め込まれた、上記配線に接続した導体部材とを備える配線基板。An insulating substrate;
A wiring member having wiring provided on one of the front and back surfaces of the insulating base material,
A support member provided on the other surface of the insulating base material,
A wiring board comprising: a conductor member embedded in the insulating base material and connected to the wiring. 上記支持部材は、金属、樹脂及びセラミックのうちの少なくともいずれかを含む請求項３記載の配線基板。The wiring board according to claim 3, wherein the support member includes at least one of a metal, a resin, and a ceramic. 上記配線部材は、
複数の配線層と、
上記配線層間を絶縁するための層間絶縁層と、
上記層間絶縁層内に設けられた、上記配線層間を接続するためのバイアホールとを備える請求項１〜４のいずれかに記載の配線基板。The wiring member,
Multiple wiring layers,
An interlayer insulating layer for insulating the wiring layers,
The wiring board according to claim 1, further comprising a via hole provided in the interlayer insulating layer for connecting the wiring layers. 上記導体部材の厚さは、０．０１ｍｍ〜０．１５ｍｍであり、
上記絶縁基材の厚さと上記導体部材の厚さとの差は、０．１ｍｍ以下である請求項１〜５のいずれかに記載の配線基板。The thickness of the conductor member is 0.01 mm to 0.15 mm,
The wiring board according to claim 1, wherein a difference between a thickness of the insulating base and a thickness of the conductor member is 0.1 mm or less. 第１の面に突起状の導体部材を設けた配線部材と、絶縁基材とを、上記導体部材を内側にして対向させて積層させる積層工程を備える請求項１〜６のいずれかに記載された配線基板の製造方法。The laminating step according to any one of claims 1 to 6, further comprising a laminating step of laminating a wiring member provided with a protruding conductor member on the first surface and an insulating base material so as to face each other with the conductor member inside. Method of manufacturing a wiring board. 上記絶縁基材の表裏一方の面には支持部材が設けられており、
上記積層工程は、上記配線部材の上記導体部材が設けられた面と、上記絶縁基材の上記支持部材が設けられていない面とを対向させて積層させる工程である請求項７記載の配線基板の製造方法。A support member is provided on one of the front and back surfaces of the insulating base material,
8. The wiring board according to claim 7, wherein the laminating step is a step of laminating the surface of the wiring member on which the conductor member is provided and the surface of the insulating base material on which the support member is not provided. Manufacturing method. 上記配線部材の第２の面には仮支持板が設けられており、
上記積層工程の後、上記仮支持板を除去する工程をさらに備える請求項７又は８記載の配線基板の製造方法。A temporary support plate is provided on the second surface of the wiring member,
9. The method for manufacturing a wiring board according to claim 7, further comprising a step of removing said temporary support plate after said laminating step. 上記配線部材の上記面に上記導体部材をめっきにより形成する工程を、さらに備える請求項７〜９のいずれかに記載の配線基板の製造方法。The method for manufacturing a wiring board according to any one of claims 7 to 9, further comprising a step of forming the conductor member on the surface of the wiring member by plating. 上記配線部材の上記第１の面に設けられた導体膜の一部を除去することにより上記導体部材を形成する工程を、さらに備える請求項７〜９のいずれかに記載の配線基板の製造方法。10. The method of manufacturing a wiring board according to claim 7, further comprising a step of forming the conductor member by removing a part of the conductor film provided on the first surface of the wiring member. . 導体板の一部を除去することにより上記配線部材及び上記導体部材を形成するエッチング工程を、さらに備える請求項７〜９のいずれかに記載の配線基板の製造方法。The method of manufacturing a wiring board according to any one of claims 7 to 9, further comprising an etching step of forming the wiring member and the conductive member by removing a part of the conductive plate. 上記導体板は、この順で積層された第１の導体層、第２の導体層及び第３の導体層からなり、
上記エッチング工程は、
上記第１の導体層の一部をエッチングして上記配線部材を形成する配線部材形成工程と、
上記第３の導体層の一部をエッチングして上記導体部材を形成する導体部材形成工程と、
上記第２の導体層の露出箇所をエッチング除去するエッチングバリア除去工程とを備える請求項１２記載の配線基板の製造方法。The conductor plate includes a first conductor layer, a second conductor layer, and a third conductor layer laminated in this order;
The etching step is
A wiring member forming step of etching the part of the first conductor layer to form the wiring member;
A conductor member forming step of etching the part of the third conductor layer to form the conductor member;
13. The method of manufacturing a wiring board according to claim 12, further comprising: an etching barrier removing step of etching and removing an exposed portion of the second conductor layer. 上記配線部材形成工程は、上記第１の導体層表面に金めっきパターンを形成し、該めっきパターンをエッチングレジストとして上記第１の導体層をエッチングすることにより上記配線部材を形成する工程である請求項１３記載の配線基板の製造方法。The wiring member forming step is a step of forming the wiring member by forming a gold plating pattern on the surface of the first conductor layer and etching the first conductor layer using the plating pattern as an etching resist. Item 14. The method for manufacturing a wiring board according to Item 13. 表裏一方の面に突起状の導体部材を設けた導体層と、絶縁基材とを、上記導体部材を内側にして対向させて積層させる積層工程、及び、
上記導体層の不要な箇所を除去して配線部材を形成する配線部材形成工程を備える請求項１〜６のいずれかに記載された配線基板の製造方法。Laminating step of laminating a conductor layer provided with a protruding conductor member on one of the front and back surfaces, and an insulating substrate, with the conductor member facing inward and facing each other,
7. The method for manufacturing a wiring board according to claim 1, further comprising a wiring member forming step of forming a wiring member by removing unnecessary portions of the conductor layer. 上記配線部材形成工程は、上記導体層表面に金めっきパターンを形成し、該めっきパターンをエッチングレジストとして上記導体層をエッチングすることにより、上記不要な箇所を除去して上記配線部材を形成する工程である請求項１５記載の配線基板の製造方法。Forming the wiring member by forming a gold plating pattern on the surface of the conductor layer and etching the conductor layer using the plating pattern as an etching resist to remove the unnecessary portions; The method for manufacturing a wiring board according to claim 15, wherein 上記絶縁基材の表裏一方の面には支持部材が設けられており、
上記積層工程は、上記導体層の上記導体部材が設けられた面と、上記絶縁基材の上記支持部材が設けられていない面とを対向させて積層させる工程である請求項１５記載の配線基板の製造方法。A support member is provided on one of the front and back surfaces of the insulating base material,
16. The wiring board according to claim 15, wherein the laminating step is a step of laminating the surface of the conductor layer on which the conductor member is provided and the surface of the insulating base material on which the support member is not provided. Manufacturing method. 上記導体層の他方の面には仮支持板が設けられており、
上記積層工程の後、上記仮支持板を除去する工程をさらに備える請求項１５〜１７のいずれかに記載の配線基板の製造方法。A temporary support plate is provided on the other surface of the conductor layer,
The method according to claim 15, further comprising a step of removing the temporary support plate after the laminating step. 上記導体層の上記面に上記導体部材をめっきにより形成する工程を、さらに備える請求項１５〜１８のいずれかに記載の配線基板の製造方法。The method for manufacturing a wiring board according to claim 15, further comprising a step of forming the conductor member on the surface of the conductor layer by plating. 上記導体層の上記面に設けられた導体膜の一部を除去することにより上記導体部材を形成する導体部材形成工程を、さらに備える請求項１５〜１８のいずれかに記載の配線基板の製造方法。The method for manufacturing a wiring board according to any one of claims 15 to 18, further comprising a conductor member forming step of forming the conductor member by removing a part of a conductor film provided on the surface of the conductor layer. . 上記導体部材形成工程は、
この順で積層された第１の導体層、第２の導体層及び第３の導体層からなる導体板の、該第３の導体層の一部をエッチングして上記導体部材を形成する工程と、
上記第２の導体層の露出箇所をエッチング除去する工程とを備える請求項２０記載の配線基板の製造方法。The conductor member forming step,
A step of etching a part of the third conductor layer of the conductor plate including the first conductor layer, the second conductor layer, and the third conductor layer laminated in this order to form the conductor member; ,
21. The method of manufacturing a wiring board according to claim 20, further comprising a step of etching and removing an exposed portion of the second conductor layer. 配線部材と、絶縁基材と、支持部材とをこの順で積層させる積層工程を備える請求項３記載の配線基板の製造方法。The method for manufacturing a wiring board according to claim 3, further comprising a laminating step of laminating the wiring member, the insulating base material, and the support member in this order. 請求項１，２，５及び６のいずれかに記載の配線基板の上記配線部材表面に半導体素子を搭載する搭載工程と、
上記半導体素子と上記配線部材表面の配線とを電気的に接続する接続工程と、
上記絶縁基材の一部を除去して上記導体部材の少なくとも一部を露出させる絶縁基材除去工程とを備える半導体装置の製造方法。A mounting step of mounting a semiconductor element on the surface of the wiring member of the wiring board according to claim 1,
A connection step of electrically connecting the semiconductor element and the wiring on the surface of the wiring member,
A method of manufacturing a semiconductor device, comprising: removing an insulating base to expose at least a part of the conductor member. 請求項３又は４に記載の配線基板の上記配線部材表面に半導体素子を搭載する搭載工程と、
上記半導体素子と上記配線部材表面の配線とを電気的に接続する接続工程と、
上記支持部材の少なくとも一部を除去して上記絶縁基材の少なくとも一部を露出させる支持部材除去工程と、
上記絶縁基材の少なくとも一部を除去して上記導体部材の少なくとも一部を露出させる絶縁基材除去工程とを備える半導体装置の製造方法。A mounting step of mounting a semiconductor element on the surface of the wiring member of the wiring board according to claim 3 or 4,
A connection step of electrically connecting the semiconductor element and the wiring on the surface of the wiring member,
A supporting member removing step of removing at least a part of the supporting member and exposing at least a part of the insulating base material,
A method of manufacturing a semiconductor device, comprising: removing at least a part of the insulating base to expose at least a part of the conductor member. 請求項３記載の配線基板の配線部材側表面に半導体素子を搭載する搭載工程と、
上記半導体素子と上記配線部材表面の配線とを電気的に接続する接続工程と、
上記支持部材の少なくとも一部を除去して上記絶縁基材の少なくとも一部を露出させる支持部材除去工程と、
上記絶縁基材の少なくとも一部を除去して貫通孔を形成し、上記配線の少なくとも一部を露出させる絶縁基材除去工程と、
上記貫通孔を導体で充填して上記配線に接続した導体部材を形成する導体部材形成工程とを備える半導体装置の製造方法。A mounting step of mounting a semiconductor element on a wiring member side surface of the wiring board according to claim 3;
A connection step of electrically connecting the semiconductor element and the wiring on the surface of the wiring member,
A supporting member removing step of removing at least a part of the supporting member and exposing at least a part of the insulating base material,
Forming a through hole by removing at least a part of the insulating base material, an insulating base material removing step of exposing at least a part of the wiring,
A conductor member forming step of filling the through hole with a conductor to form a conductor member connected to the wiring. 上記搭載工程における搭載は、接着剤を介して行われる、請求項２３〜２５のいずれかに記載の半導体装置の製造方法。26. The method of manufacturing a semiconductor device according to claim 23, wherein the mounting in the mounting step is performed via an adhesive. 上記支持部材除去工程における上記支持部材の除去は、研磨、化学エッチング及び機械加工の少なくともいずれかにより行われる、請求項２４又は２５記載の半導体装置の製造方法。26. The method of manufacturing a semiconductor device according to claim 24, wherein the removal of the support member in the support member removing step is performed by at least one of polishing, chemical etching, and machining. 上記絶縁基材除去工程における上記絶縁基材の除去は、
研磨、レーザ照射及びエッチングの少なくともいずれかにより行われる、請求項２３〜２７のいずれかに記載の半導体装置の製造方法。Removal of the insulating base material in the insulating base material removing step,
The method of manufacturing a semiconductor device according to claim 23, wherein the method is performed by at least one of polishing, laser irradiation, and etching. 上記絶縁基材除去工程の後に、
上記導体部材の露出箇所に、金めっき層を形成する工程をさらに備える請求２３〜２７のいずれかに記載の半導体装置の製造方法。After the insulating substrate removing step,
The method of manufacturing a semiconductor device according to any one of claims 23 to 27, further comprising a step of forming a gold plating layer on an exposed portion of the conductor member. 上記絶縁基材除去工程の後に、
上記導体部材の露出箇所に、はんだボールを形成する工程をさらに備える請求項２３〜２７のいずれかに記載の半導体装置の製造方法。After the insulating substrate removing step,
28. The method of manufacturing a semiconductor device according to claim 23, further comprising a step of forming a solder ball at an exposed portion of the conductor member. 上記搭載工程は、
一つの上記配線基板に、複数の上記半導体素子を搭載する工程である、請求項２３〜２７のいずれかに記載の半導体装置の製造方法。The above mounting process is
28. The method of manufacturing a semiconductor device according to claim 23, comprising mounting a plurality of said semiconductor elements on one said wiring board. 上記搭載工程は、
一つの上記配線基板に、上記半導体素子のほかに、受動部品をさらに搭載する工程である、請求項２３〜２７のいずれかに記載の半導体装置の製造方法。The above mounting process is
28. The method of manufacturing a semiconductor device according to claim 23, further comprising a step of mounting a passive component on the one wiring board in addition to the semiconductor element. 上記半導体素子を封止部材により覆って封止する封止工程をさらに備える、請求項２３〜２７のいずれかに記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 23, further comprising a sealing step of covering and sealing the semiconductor element with a sealing member. 上記封止部材を研磨して上記半導体素子の少なくとも一部を露出させる工程をさらに備える、請求項３３記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 33, further comprising a step of polishing the sealing member to expose at least a part of the semiconductor element. 請求項２３〜３４のいずれかの方法により製造された半導体装置。A semiconductor device manufactured by the method according to claim 23.
JP2003525905A 2001-08-31 2001-08-31 Wiring board, semiconductor device, and manufacturing method thereof Pending JPWO2003021668A1 (en)

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