JPS649644A - Hybrid integrated circuit substrate - Google Patents

Hybrid integrated circuit substrate

Info

Publication number
JPS649644A
JPS649644A JP62164582A JP16458287A JPS649644A JP S649644 A JPS649644 A JP S649644A JP 62164582 A JP62164582 A JP 62164582A JP 16458287 A JP16458287 A JP 16458287A JP S649644 A JPS649644 A JP S649644A
Authority
JP
Japan
Prior art keywords
heat
substrate
generating part
ceramic
packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164582A
Other languages
Japanese (ja)
Inventor
Yuko Suzuki
Hidenori Tanizawa
Kenichiro Tsubone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62164582A priority Critical patent/JPS649644A/en
Publication of JPS649644A publication Critical patent/JPS649644A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass

Abstract

PURPOSE:To miniaturise the title hybrid integrated circuit substrate by lowering the height of package, to lower the height of the substrate by reducing the number of parts needed by a method wherein a ceramic transmission member, having excellent heat transmittivity, is buried exposing both end faces of the member for the purpose of cooling by heat transfer by contacting to the heat-generating part to be packaged on the surface. CONSTITUTION:A substrate element consisting of ceramic material and having a low specific inductive capacity is superposed on a ceramic substrate 20, and an inner layer pattern 5, a circuit pattern 6 and a through hole conductor, with which the above-mentioned materials are connected, are provided on the substrate 20. A through hole 21 is provided on the part where a heat-generating part 2, having a large quantity of heat value, and other heat-generating part 2 which is desirable to be cooled down, will be packaged. Also, a conductive member 30 has the coefficient of thermal expansion almost same as that of the ceramic substrate 20, the former consists of the ceramic material having excellent heat conductivity, its height is equal to the thickness of the ceramic substrate 20, and it is fitted into the through hole of the ceramic substrate 20. The heat-generating part 2, having a large quantity of heat power, and the selected heat-generating part 2 are packaged on the upper end part of the conductive member 30 by closely fixing the bottom faces of them respectively.
JP62164582A 1987-07-01 1987-07-01 Hybrid integrated circuit substrate Pending JPS649644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164582A JPS649644A (en) 1987-07-01 1987-07-01 Hybrid integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164582A JPS649644A (en) 1987-07-01 1987-07-01 Hybrid integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPS649644A true JPS649644A (en) 1989-01-12

Family

ID=15795909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164582A Pending JPS649644A (en) 1987-07-01 1987-07-01 Hybrid integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPS649644A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103809A (en) * 2013-11-25 2015-06-04 テザト−スペースコム・ゲーエムベーハー・ウント・コー・カーゲー Circuit board including ceramic inlay
JP2018530161A (en) * 2015-10-01 2018-10-11 エルジー イノテック カンパニー リミテッド Light emitting device, method for manufacturing light emitting device, and light emitting module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103809A (en) * 2013-11-25 2015-06-04 テザト−スペースコム・ゲーエムベーハー・ウント・コー・カーゲー Circuit board including ceramic inlay
US10292254B2 (en) 2013-11-25 2019-05-14 Tesat-Spacecom Gmbh & Co. Kg Circuit board with ceramic inlays
JP2018530161A (en) * 2015-10-01 2018-10-11 エルジー イノテック カンパニー リミテッド Light emitting device, method for manufacturing light emitting device, and light emitting module

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