JPS649583A - Data processing system by ic card - Google Patents

Data processing system by ic card

Info

Publication number
JPS649583A
JPS649583A JP62166053A JP16605387A JPS649583A JP S649583 A JPS649583 A JP S649583A JP 62166053 A JP62166053 A JP 62166053A JP 16605387 A JP16605387 A JP 16605387A JP S649583 A JPS649583 A JP S649583A
Authority
JP
Japan
Prior art keywords
data
memory access
card
normal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62166053A
Other languages
Japanese (ja)
Inventor
Akira Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62166053A priority Critical patent/JPS649583A/en
Publication of JPS649583A publication Critical patent/JPS649583A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the access time by parallel accessing and to improve the reliability of system by installing two systems of RAMs onto an IC card and writing same data therein. CONSTITUTION:The IC card 10 is provided with 1st and 2nd random access memories RAMs 12, 13 and terminal groups 14, 15 connecting to them respectively. The data processing unit is provided with 1st and 2nd memory access circuits 21, 22, 1st and 2nd contact groups 23, 24 and a control circuit 27, and in writing the data, the control circuit 27 writes the same write data to both the 1st memory access circuit 21 and the 2nd memory access circuit 22 and in case of data readout, the data is read from one memory access circuit and when it is normal, the result is processed as readout data and when not normal, the data read by the other memory access circuit is checked and when it is normal, the result is processed as the readout data. Thus, the reliability of the entire system is improved remarkably.
JP62166053A 1987-07-02 1987-07-02 Data processing system by ic card Pending JPS649583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62166053A JPS649583A (en) 1987-07-02 1987-07-02 Data processing system by ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62166053A JPS649583A (en) 1987-07-02 1987-07-02 Data processing system by ic card

Publications (1)

Publication Number Publication Date
JPS649583A true JPS649583A (en) 1989-01-12

Family

ID=15824090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62166053A Pending JPS649583A (en) 1987-07-02 1987-07-02 Data processing system by ic card

Country Status (1)

Country Link
JP (1) JPS649583A (en)

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