JPS6491249A - Logic circuit simulator - Google Patents

Logic circuit simulator

Info

Publication number
JPS6491249A
JPS6491249A JP62248855A JP24885587A JPS6491249A JP S6491249 A JPS6491249 A JP S6491249A JP 62248855 A JP62248855 A JP 62248855A JP 24885587 A JP24885587 A JP 24885587A JP S6491249 A JPS6491249 A JP S6491249A
Authority
JP
Japan
Prior art keywords
logic circuit
circuit simulator
production
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62248855A
Other languages
Japanese (ja)
Inventor
Kakagi Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62248855A priority Critical patent/JPS6491249A/en
Publication of JPS6491249A publication Critical patent/JPS6491249A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To shorten the time needed for production of a logic circuit by performing the open/close control between the input and output terminals of each programmable logic device PLD via a gate when plural PLDs are used for production of a logic circuit simulator. CONSTITUTION:When a logic circuit simulator is produced by PLD1 and 2, the proper connection is secured among input and output pins 1-2-1, 1-2-2, 1-1-1, 1-1-2, 2-2-1, 2-2-2, 2-1-1 and 2-1-2 of both PLD1 and 2 via gates. Thus the due output and input pins are connected to each other with due gates turned on. Thus it is possible to omit the time needed for reconnection of terminals carried out via a print circuit, etc., for each production of a logic circuit simulator.
JP62248855A 1987-10-01 1987-10-01 Logic circuit simulator Pending JPS6491249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62248855A JPS6491249A (en) 1987-10-01 1987-10-01 Logic circuit simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62248855A JPS6491249A (en) 1987-10-01 1987-10-01 Logic circuit simulator

Publications (1)

Publication Number Publication Date
JPS6491249A true JPS6491249A (en) 1989-04-10

Family

ID=17184426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62248855A Pending JPS6491249A (en) 1987-10-01 1987-10-01 Logic circuit simulator

Country Status (1)

Country Link
JP (1) JPS6491249A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386550A (en) * 1992-01-24 1995-01-31 Fujitsu Limited Pseudo-LSI device and debugging system incorporating same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4840367A (en) * 1971-09-25 1973-06-13
JPS5141501A (en) * 1974-10-07 1976-04-07 Isamu Koizumi 2 channeruhetsudofuonyoanpuno hoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4840367A (en) * 1971-09-25 1973-06-13
JPS5141501A (en) * 1974-10-07 1976-04-07 Isamu Koizumi 2 channeruhetsudofuonyoanpuno hoho

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386550A (en) * 1992-01-24 1995-01-31 Fujitsu Limited Pseudo-LSI device and debugging system incorporating same

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