JPS6486769A - Image display device - Google Patents

Image display device

Info

Publication number
JPS6486769A
JPS6486769A JP24548687A JP24548687A JPS6486769A JP S6486769 A JPS6486769 A JP S6486769A JP 24548687 A JP24548687 A JP 24548687A JP 24548687 A JP24548687 A JP 24548687A JP S6486769 A JPS6486769 A JP S6486769A
Authority
JP
Japan
Prior art keywords
synchronizing
picture
memories
displaying
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24548687A
Other languages
Japanese (ja)
Inventor
Hisaharu Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24548687A priority Critical patent/JPS6486769A/en
Publication of JPS6486769A publication Critical patent/JPS6486769A/en
Pending legal-status Critical Current

Links

Landscapes

  • Studio Circuits (AREA)

Abstract

PURPOSE:To prevent a joint part from being generated on a slave picture by providing a storage means having three memories, selecting the three memories sequentially in a prescribed order synchronizing with video signals for displaying the slave picture and a master picture, writing the video signal for displaying the slave picture field by field, and reading out stored data. CONSTITUTION:A control circuit 16 selects the three memories MEM 1-3 in a memory 17 sequentially in the prescribed order synchronizing with a horizontal synchronizing signal HD1 and a vertical synchronizing signal VD1 separated from a first video signal V1 for displaying the slave picture by a synchronizing separator circuit 15. And the digital output of the first video signal V1 is written on a selected memory field by field. Also, the three memories MEM1-3 in the memory 17 are selected sequentially in the prescribed order synchronizing with synchronizing signals HD2 and VD2 separated from a second video signal for displaying the master picture, and the stored data is read out. Therefore, since to simultaneous read and write is performed in each of the memories MEM1-3, no joint part is generated on the slave picture.
JP24548687A 1987-09-29 1987-09-29 Image display device Pending JPS6486769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24548687A JPS6486769A (en) 1987-09-29 1987-09-29 Image display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24548687A JPS6486769A (en) 1987-09-29 1987-09-29 Image display device

Publications (1)

Publication Number Publication Date
JPS6486769A true JPS6486769A (en) 1989-03-31

Family

ID=17134376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24548687A Pending JPS6486769A (en) 1987-09-29 1987-09-29 Image display device

Country Status (1)

Country Link
JP (1) JPS6486769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362687A (en) * 1989-07-29 1991-03-18 Sharp Corp Television receiver
US5208660A (en) * 1989-07-29 1993-05-04 Sharp Kabushiki Kaisha Television display apparatus having picture-in-picture display function and the method of operating the same
US7061543B1 (en) 1998-09-23 2006-06-13 Micronas Gmbh Method and circuit for image-in-image overlay

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362687A (en) * 1989-07-29 1991-03-18 Sharp Corp Television receiver
US5208660A (en) * 1989-07-29 1993-05-04 Sharp Kabushiki Kaisha Television display apparatus having picture-in-picture display function and the method of operating the same
US7061543B1 (en) 1998-09-23 2006-06-13 Micronas Gmbh Method and circuit for image-in-image overlay

Similar Documents

Publication Publication Date Title
MY107482A (en) Aspect ratio control for picture overlays.
EP0326327A3 (en) Apparatus for superimposing graphic title image signals onto a video signal
GB1357808A (en) Image signal reproducing apparatus
KR900004171A (en) All-in-one video recorder
CA2195158A1 (en) Moving Image Judging Apparatus
KR850005934A (en) Video signal processing device
JPS5780880A (en) Video signal reproducing device
MY114906A (en) Method and apparatus for displaying two video pictures simultaneously
JPS6486769A (en) Image display device
KR970008379B1 (en) Method and apparatus for decreasing side blank of wide screen
US5469269A (en) High speed optical information system and method
EP0585903A3 (en) Video signal memory equipment
CA2103394A1 (en) Apparatus for video signal processing
JPS5620391A (en) Two-screen television receiver
JPS6028389A (en) Still picture reproducing device
JPS6429064A (en) Image display
US5610840A (en) Signal processing device
JPS6432780A (en) Video printer
KR970057703A (en) Memory device of PDP TV
JP2817154B2 (en) Still image receiving device
JPS6045495B2 (en) Multi-memory driving method
JPS6464476A (en) Digital picture storage device and reproducing device
JPH04304787A (en) Title picture inserting device
KR940023196A (en) Image memory circuit for digital processing of interlaced video signals
JPH0278385A (en) Still picture processing circuit