JPS6486640A - Gpib addition circuit - Google Patents

Gpib addition circuit

Info

Publication number
JPS6486640A
JPS6486640A JP24263387A JP24263387A JPS6486640A JP S6486640 A JPS6486640 A JP S6486640A JP 24263387 A JP24263387 A JP 24263387A JP 24263387 A JP24263387 A JP 24263387A JP S6486640 A JPS6486640 A JP S6486640A
Authority
JP
Japan
Prior art keywords
talker
pseudo
gpib
signal
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24263387A
Other languages
Japanese (ja)
Inventor
Yasuaki Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24263387A priority Critical patent/JPS6486640A/en
Publication of JPS6486640A publication Critical patent/JPS6486640A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To initialize only an optional equipment by ORing a GPIB control signal inputted from a GPIB(General Purpose Interface Bus) bus and a pseudo control signal sent from a pseudo signal generating section at the input opera tion so as to input the result to the GPIB control section. CONSTITUTION:In bringing only a talker 3b in the initial state and in applying the power supply of, e.g., the talker 3b again from the nonpower supply, the talker 3b is initialized as follows. In applying the power supply of the talker 3b again, a pseudo signal generating section 15b generates a pseudo IFC(Inter Face Cliar) signal. The pseudo IFC signal is given to a GPIB control section 9b via an OR gate 21b and a bidirectional signal gate 19b to initialize the talker 3b. Thus, the power supply of an optional equipment is applied again in an optional timing without giving effect onto other equipment executing the data transfer and without deteriorating the throughput of the system operation such as the interruption of data transfer.
JP24263387A 1987-09-29 1987-09-29 Gpib addition circuit Pending JPS6486640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24263387A JPS6486640A (en) 1987-09-29 1987-09-29 Gpib addition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24263387A JPS6486640A (en) 1987-09-29 1987-09-29 Gpib addition circuit

Publications (1)

Publication Number Publication Date
JPS6486640A true JPS6486640A (en) 1989-03-31

Family

ID=17091956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24263387A Pending JPS6486640A (en) 1987-09-29 1987-09-29 Gpib addition circuit

Country Status (1)

Country Link
JP (1) JPS6486640A (en)

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