JPS648465B2 - - Google Patents
Info
- Publication number
- JPS648465B2 JPS648465B2 JP5345079A JP5345079A JPS648465B2 JP S648465 B2 JPS648465 B2 JP S648465B2 JP 5345079 A JP5345079 A JP 5345079A JP 5345079 A JP5345079 A JP 5345079A JP S648465 B2 JPS648465 B2 JP S648465B2
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- group compound
- etching
- ions
- ion irradiation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 13
- 150000001875 compounds Chemical class 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 8
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 13
- 239000000463 material Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
Description
【発明の詳細な説明】
この発明は、GaおよびAsの元素より成る化合
物半導体の表面を精密に加工する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for precisely processing the surface of a compound semiconductor composed of the elements Ga and As.
−族化合物半導体は電子材料や光学材料と
して広範な応用が期待されている材料である。特
に、砒化ガリウム（GaAs）を用いた論理集積回
路については、実用的観点からその高速性への期
待が増大しつつある。また、GaAs、GaP及びそ
れらの混晶であるGaAsP、及びAlAsとGaAsの
混晶であるAlGaAs等は従来より発光素子材料と
して用いられているが、これらの材料を用いた光
集積回路も活発な研究の対象になつている。上記
のような集積回路を製作するためには、これらの
材料の表面形状を制御性よく精密加工することが
必要である。 - group compound semiconductors are materials that are expected to have a wide range of applications as electronic and optical materials. In particular, expectations for high-speed performance of logic integrated circuits using gallium arsenide (GaAs) are increasing from a practical standpoint. In addition, GaAs, GaP, GaAsP, a mixed crystal thereof, and AlGaAs, a mixed crystal of AlAs and GaAs, have traditionally been used as light-emitting device materials, but optical integrated circuits using these materials are also gaining momentum. It has become the subject of research. In order to manufacture the above-mentioned integrated circuits, it is necessary to precisely process the surface shapes of these materials with good controllability.
第１図は、このような表面形状加工のために従
来用いられているエツチング法を示したものであ
る。 FIG. 1 shows an etching method conventionally used for processing such a surface shape.
まず、第１図ａのように、−族化合物半導
体の基板１の上にフオトレジスト材料等のマスク
２を形成し、適当な溶液中で基板１を溶解させ、
次にマスク２を再び適当な溶液で溶解し除去する
方法である。しかし、その際、第１図ｂのように
エツチングがマスクの下まで及ぶこと、また、エ
ツチング深さの制御がエツチング剤の組成、温
度、エツチング時間等のエツチング条件のみによ
つてなされていることにより、加工精度及び再現
性を高めるのは極めて困難であつた。 First, as shown in FIG. 1a, a mask 2 made of photoresist material or the like is formed on a substrate 1 of a - group compound semiconductor, and the substrate 1 is dissolved in an appropriate solution.
Next, the mask 2 is dissolved again in an appropriate solution and removed. However, in this case, the etching extends to the bottom of the mask as shown in Figure 1b, and the etching depth is controlled only by etching conditions such as the composition of the etching agent, temperature, and etching time. Therefore, it has been extremely difficult to improve processing accuracy and reproducibility.
この発明は、上記のような従来の方法の欠点を
除去し、加工精度と再現性を高めるための新規な
加工方法を提供することを目的とするものであ
る。以下この発明について説明する。 It is an object of the present invention to provide a novel processing method that eliminates the drawbacks of the conventional methods as described above and improves processing accuracy and reproducibility. This invention will be explained below.
第２図はこの発明の一実施例を示したものであ
る。まず、第２図ａのようにGaAsよりなる−
族化合物半導体の基板１１の上にマスク１２を
形成し、これに数keV〜数100keVのエネルギー
に加速されたイオン１３を照射する。照射された
イオン１３は基板１１内に侵入し、その部分の結
晶を破壊して損傷部分１４を形成する。次に、マ
スク１２を除去し、HClを含む水溶液中でエツチ
ングを行うと、第２図ｂのように損傷部分１４を
選択的に溶解することができ、マスク１２の形状
に対応したエツチングができる。その際、エツチ
ングされた表面に非溶解性の残渣が生じるが、
H2O2水溶液でリンスすることにより容易に除去
できる。損傷部分１４の深さは、照射するイオン
のイオン種、エネルギー、照射量等のイオン照射
条件で決定されるが、これらはすべて電気的に測
定制御できるので、不定な要素の多いエツチング
を用いる従来の方法より、加工精度を格段に改善
できる。 FIG. 2 shows an embodiment of the present invention. First, as shown in Figure 2a, - is made of GaAs.
A mask 12 is formed on a substrate 11 of a group compound semiconductor, and ions 13 accelerated to an energy of several keV to several 100 keV are irradiated onto the mask 12. The irradiated ions 13 penetrate into the substrate 11 and destroy the crystal in that portion, forming a damaged portion 14 . Next, when the mask 12 is removed and etching is performed in an aqueous solution containing HCl, the damaged portion 14 can be selectively dissolved as shown in FIG. . At that time, insoluble residue is generated on the etched surface, but
Easily removed by rinsing with aqueous H 2 O 2 solution. The depth of the damaged area 14 is determined by ion irradiation conditions such as the ion type, energy, and irradiation dose of the ions to be irradiated, but since all of these can be measured and controlled electrically, conventional etching methods that use many uncertain factors are not possible. Machining accuracy can be significantly improved by this method.
以下、具体的な実施例に従つて詳細に説明す
る。 Hereinafter, a detailed explanation will be given according to specific examples.
第３図はGaAsにマスクを用いて部分的に
100keVのAr+イオンを１×1015／cm2照射し、40℃
及び50℃に加熱した12モルHCl溶液でエツチング
した時に形成される段差の大きさを示したもので
ある。この場合、イオン照射時にマスクされてい
た部分は全く溶解されない。従来のエツチング法
とは異なり、耐エツチング性のマスクを用いない
でも、第３図のように適当な時間エツチングする
と液温やエツチング時間にあまり依存せずに一定
の大きさの段差が得られ、得られた表面の平滑性
も良好である。 Figure 3 shows a partial section of GaAs using a mask.
Irradiated with 100keV Ar + ions at 1×10 15 /cm 2 and heated at 40℃.
This figure shows the size of the step formed when etching is performed with a 12 molar HCl solution heated to 50°C. In this case, the portion that was masked during ion irradiation is not dissolved at all. Unlike conventional etching methods, even if an etching-resistant mask is not used, if etching is performed for an appropriate time as shown in Figure 3, a step of a constant size can be obtained without depending much on the solution temperature or etching time. The smoothness of the obtained surface is also good.
上記の方法でGaAsの形成される段差の大きさ
をイオン照射条件によつて制御できることを示し
たのが、第４図及び第５図である。 FIGS. 4 and 5 show that the size of the step formed in GaAs can be controlled by the ion irradiation conditions using the above method.
第４図のように照射するAr+イオンの量を１×
1015／cm2に固定しても、エネルギーを50keVから
200keVに変化させることによつて得られる段差
の大きさを0.08μｍから0.26μｍの範囲に設定する
ことができる。 As shown in Figure 4, the amount of Ar + ions to be irradiated is 1×
Even if it is fixed at 10 15 /cm 2 , the energy is reduced from 50 keV.
By changing the voltage to 200 keV, the size of the step difference obtained can be set in the range of 0.08 μm to 0.26 μm.
また、第５図のように照射エネルギー100keV
の条件下においても、照射量を１×1014／cm2から
５×1015／cm2に変化させると0.11μｍから0.18μｍ
の大きさの段差が得られる。 Also, as shown in Figure 5, the irradiation energy is 100keV.
Even under the conditions of
A step of the size is obtained.
なお、上記実施例では照射イオンとしてAr+イ
オンを用いた場合について説明したが、この発明
はこれに限らず酸素イオン、ネオンイオン等を用
いても同様の表面形状加工が可能である。また、
この発明の方法はGaAs以外の−族化合物半
導体にも適用することができる。 In the above embodiment, the case where Ar + ions were used as the irradiation ions was explained, but the present invention is not limited to this, and similar surface shape processing can be performed using oxygen ions, neon ions, etc. Also,
The method of this invention can also be applied to - group compound semiconductors other than GaAs.
以上詳細に説明したように、この発明はGaAs
よりなる−族化合物半導体にイオンを照射し
て所望の形状の損傷部分を発生させ、それをHCl
水溶液中で選択的に溶解させるようにしたので表
面形状の精密な加工を行うことができる。したが
つて、この発明は、集積回路の作製等、電子工業
への広範な応用が期待される。 As explained in detail above, this invention is based on GaAs
Ions are irradiated on a - group compound semiconductor to generate a damaged part of the desired shape, and then the damaged part is treated with HCl.
Since it is selectively dissolved in an aqueous solution, it is possible to precisely process the surface shape. Therefore, this invention is expected to find wide application in the electronic industry, such as in the production of integrated circuits.
第１図は従来の方法の工程図、第２図はこの発
明の一実施例の工程図、第３図、第４図、第５図
はこの発明の具体的な実施例を示す図である。
図中、１１は−族化合物半導体の基板、１
２はマスク、１３はイオン、１４は損傷部分であ
る。
Fig. 1 is a process diagram of a conventional method, Fig. 2 is a process diagram of an embodiment of the present invention, and Figs. 3, 4, and 5 are diagrams showing a specific embodiment of the present invention. . In the figure, 11 is a - group compound semiconductor substrate, 1
2 is a mask, 13 is an ion, and 14 is a damaged portion.
Claims (1)
の表面にイオン照射を施し、HClを含む水溶液中
で、イオン照射により発生した損傷部分を選択的
に溶解せしめることを特徴とする−族化合物
半導体の表面形状加工方法。 ２ イオン照射時に表面にマスキングを施し、発
生する損傷部分の形状を制御することを特徴とす
る特許請求の範囲第１項記載の−族化合物半
導体の表面形状加工方法。[Claims] 1. A - group compound semiconductor comprising ion irradiation on the surface of a - group compound semiconductor made of gallium arsenide, and selectively dissolving damaged parts caused by the ion irradiation in an aqueous solution containing HCl. A method for processing the surface shape of compound semiconductors. 2. A method for processing the surface shape of a - group compound semiconductor according to claim 1, characterized in that the shape of a damaged portion that occurs is controlled by masking the surface during ion irradiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5345079A JPS55145344A (en) | 1979-05-02 | 1979-05-02 | Mthod for surface profile processing of 3-5 group compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5345079A JPS55145344A (en) | 1979-05-02 | 1979-05-02 | Mthod for surface profile processing of 3-5 group compound semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55145344A JPS55145344A (en) | 1980-11-12 |
| JPS648465B2 true JPS648465B2 (en) | 1989-02-14 |
Family
ID=12943183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5345079A Granted JPS55145344A (en) | 1979-05-02 | 1979-05-02 | Mthod for surface profile processing of 3-5 group compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55145344A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59213135A (en) * | 1983-05-19 | 1984-12-03 | Agency Of Ind Science & Technol | Fine processing for semiconductor |
| JP2011243657A (en) * | 2010-05-14 | 2011-12-01 | Mitsumi Electric Co Ltd | Semiconductor device manufacturing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4915114A (en) * | 1972-06-02 | 1974-02-09 | ||
| JPS50110284A (en) * | 1974-02-06 | 1975-08-30 | ||
| JPS513782A (en) * | 1974-06-28 | 1976-01-13 | Hitachi Ltd | HANDOTA ISHORIHO |
| JPS5122372A (en) * | 1974-08-19 | 1976-02-23 | Matsushita Electric Ind Co Ltd | Gaaallas no fushokuhoho |
-
1979
- 1979-05-02 JP JP5345079A patent/JPS55145344A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55145344A (en) | 1980-11-12 |
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