JPS59213135A - Fine processing for semiconductor - Google Patents

Fine processing for semiconductor

Info

Publication number
JPS59213135A
JPS59213135A JP8665683A JP8665683A JPS59213135A JP S59213135 A JPS59213135 A JP S59213135A JP 8665683 A JP8665683 A JP 8665683A JP 8665683 A JP8665683 A JP 8665683A JP S59213135 A JPS59213135 A JP S59213135A
Authority
JP
Japan
Prior art keywords
crystal growth
substrate
growth layer
region
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8665683A
Other languages
Japanese (ja)
Other versions
JPH0155574B2 (en
Inventor
Yasuo Baba
馬場 靖男
Eizo Miyauchi
宮内 栄三
Hiroshi Arimoto
宏 有本
Akira Takamori
高森 晃
Toshio Hashimoto
橋本 寿夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP8665683A priority Critical patent/JPS59213135A/en
Publication of JPS59213135A publication Critical patent/JPS59213135A/en
Publication of JPH0155574B2 publication Critical patent/JPH0155574B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To realize a fine processing method for semiconductors, which effects a superior processing precision and facilitates the control of processing form, by a method wherein an ion implantation with a concentration, which is formed by an amorphous substance, is performed in regions in the surface of a substrate and then only crystal growth regions just above the ion-implanted regions in the substrate are selectively removed by performing an etching treatment on an crystal growth layer formed on the surface of the substrate. CONSTITUTION:Ions 3 are previously implanted in regions 2, where oppose to positions to be performed a processing on a crystal growth layer 6 on the surface of a substrate 1, whereon the crystal growth layer 6 is to be formed, and after the prescribed amount of ion-implantation was completed, the crystal growth layer 6 is formed on the surface of the substrate 1 by a molecular beam crystal growth method. After the crystal growth layer 6 of a prescribed thickness was formed by the molecular beam crystal growth method, the crystal growth layer 6 is performed an etching treatment by using a selective etching solution. By appropriately selecting the etching solution, the treating time, etc., only the crystal growth regions just above the ion-implanted regions in the substrate 1 are preferentially etched, removed and apertures 8 are formed.

Description

【発明の詳細な説明】 この発明は半導体の微細加工方法に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor microfabrication method.

光通信や光情報処理技術の発展に伴い従来の光素子、電
子素子単体の代りに各種光素子群、電子素子群を同一基
板に千ノリシックに集積化した光−電子集積回路の実現
が嘱望されている。
With the development of optical communication and optical information processing technology, there are hopes for the realization of opto-electronic integrated circuits in which groups of various optical elements and electronic elements are integrated on the same substrate in thousands of ways, instead of the conventional single optical elements and electronic elements. ing.

この光−電子集積回路の実現に当り、各党、電子微細素
子間のアイツレ―シロン、レーザの共振器ミラー作成、
光の分岐・分波路作成において、半導体微細加工技術が
不可欠であり、製造プロセスの能率化、各素子の性能、
信頼性については微細加工技術は大きな影響を及ぼすこ
とになる。
In realizing this opto-electronic integrated circuit, various parties, collaboration between electronic micro elements, laser resonator mirror creation,
Semiconductor microfabrication technology is indispensable in the creation of optical branches and branching channels, streamlining the manufacturing process, improving the performance of each element,
Microfabrication technology will have a major impact on reliability.

これまでの半導体の微細加工技術としてはりソグラフイ
で形成したパターンを用いたウェット成るいはドライエ
ツチング法が知られているが、エツチングの深さを制御
するのが容易でなく、側方にもエツチングが進行して微
細パターンの精確な形成が困難であった。またドライエ
ツチング法式るいは集束イオンビームを用いた半導体基
板への直接エツチング加工ではプラズマ成るいはイオン
照射により加工面が損傷され、損傷部の除失成るいはア
ニール処理を必要とする。
Wet or dry etching methods using patterns formed by beam lithography have been known as semiconductor microfabrication techniques to date, but it is difficult to control the depth of etching, and etching also occurs on the sides. This progressed, making it difficult to form fine patterns accurately. Furthermore, when a semiconductor substrate is directly etched using a dry etching method or a focused ion beam, the processed surface is damaged by plasma or ion irradiation, and the damaged portion must be removed or annealed.

この発明の目的は加工精度が優れ、加工形状の制御が容
易な半導体微細加工方法を提供することにある。
An object of the present invention is to provide a semiconductor microfabrication method with excellent processing accuracy and easy control of the processed shape.

このため、本発明に依る半導体の微細加工方法は結晶成
長層を形成する基板表面上の結晶成長層の加工すべき位
置に対応する基板表面領域に非晶質が形成する濃度のイ
オン注入を行い、次いで該基板表面上に鞭−晶戒長層を
形成し、形成した結晶成長層をエツチング処理をして基
板のイオン注入領域直上の結晶成長領域のみを選択的に
除去することを特徴とする。
Therefore, in the semiconductor microfabrication method according to the present invention, ions are implanted at a concentration that forms an amorphous material in a substrate surface area corresponding to the position where the crystal growth layer is to be processed on the substrate surface where the crystal growth layer is to be formed. Next, a whip-crystal growth layer is formed on the surface of the substrate, and the formed crystal growth layer is etched to selectively remove only the crystal growth region directly above the ion implantation region of the substrate. .

このように、基板のイオン注入領域直上の結晶成長領域
は多結晶であるため、単結晶に較べてエツチング速度は
著しく早く、従って、基板のイオン注入領域まで正確に
且つ迅速にエツチング処理を行うことができる。またエ
ツチングの横の拡がりは結晶成長層の単結晶領域により
抑制されるため微細なパターンについても正確に千ツチ
ングを行うことができ、イオン照射による基板の損傷部
も併せて除去することができる。
In this way, since the crystal growth region directly above the ion implantation region of the substrate is polycrystalline, the etching speed is significantly faster than that of a single crystal, and therefore, the etching process can be performed accurately and quickly to the ion implantation region of the substrate. Can be done. Furthermore, since the lateral spread of etching is suppressed by the single crystal region of the crystal growth layer, fine patterns can be precisely etched, and parts of the substrate damaged by ion irradiation can also be removed.

次にこの発明を第1図により説明すると、予じめ結晶成
長層6を形成すべき基板7表面上の、結晶成長層に加工
すべき位置に対応する領域−へイオン3を注入する。基
板lとしては半絶縁性のGaAsの如き基板結晶のみな
らず、基板結晶上に形成した成長層をも含む。上述のイ
オン注入は公知のイオン注入法を用いることができ、注
入すべきイオン濃度はイオン注入領域に大量のイオン照
射損傷が形成され、少くとも高密度に非晶質(アモルフ
ァス・クラスター)が出来る程度とし、具体的にはI 
X 1016♂程度以上を必要とする。使用するイオン
種はBgイオン、hイオン、均イオンなどが挙げられる
が、質量数の大きいイオン種の方が効果的である。また
加速エネルギーも通常のイオン注入法で用いる数10 
KgVから数100 KgVの範囲で好適に利用でき、
I MgVを超えても良い。また10KgV程度でも有
効であるが、加速エネルギーが低くなるに従って入射イ
オンによるスパッタリング効果が顕著となって、効果が
減少する。
Next, the present invention will be explained with reference to FIG. 1. Ions 3 are implanted in advance into a region on the surface of the substrate 7 where the crystal growth layer 6 is to be formed, corresponding to a position to be processed into the crystal growth layer. The substrate 1 includes not only a semi-insulating substrate crystal such as GaAs but also a growth layer formed on the substrate crystal. A known ion implantation method can be used for the above-mentioned ion implantation, and the ion concentration to be implanted is such that a large amount of ion irradiation damage is formed in the ion implantation region, and at least amorphous clusters are formed at a high density. degree, specifically I
Requires approximately 1016♂ or more. The ion species used include Bg ions, h ions, and uniform ions, but ion species with a large mass number are more effective. In addition, the acceleration energy is a number of 10, which is used in normal ion implantation.
It can be suitably used in the range of KgV to several 100 KgV,
It may exceed I MgV. Although it is effective at about 10 KgV, as the acceleration energy decreases, the sputtering effect due to incident ions becomes more pronounced and the effect decreases.

イオンを注入する方法としては第1図に示したようにサ
ブミクロンのオーダで集束されたイオンビーム3を直接
基板/の所定領域−に照射するマスクレスイオン注入方
法、成るいは、第2図に示すように8401薄膜などの
注入マスクダを基板lに被着し、レジスト薄膜により所
定のパターン5を描画して、イオンビーム3を照射して
基板/の所定領域コにイオン3を注入するようにしても
良い。
The ion implantation method is a maskless ion implantation method in which a predetermined region of the substrate is directly irradiated with an ion beam 3 focused on the order of submicrons as shown in FIG. 1, or a maskless ion implantation method as shown in FIG. As shown in the figure, an implantation mask such as 8401 thin film is applied to the substrate l, a predetermined pattern 5 is drawn with the resist thin film, and the ion beam 3 is irradiated to implant the ions 3 into a predetermined area of the substrate. You can also do it.

上述の如くして、基板/上に形成する結晶成長層の加工
すべき位置に対応する基板領域に所定量のイオン注入が
完了したら、この基板面上に結晶成長層6を分子線結晶
成長法で形成する(第3図)。結晶成長温度は通常用い
られている500℃〜750℃で良いが、余り高いと基
板はアニール処理を施されたような効果が生じるので、
比較的低い温度の方が良好な結果を得る。
As described above, when a predetermined amount of ions have been implanted into the substrate region corresponding to the position where the crystal growth layer to be formed on the substrate is to be processed, the crystal growth layer 6 is formed on the substrate surface by molecular beam crystal growth. (Figure 3). The crystal growth temperature may be the commonly used 500°C to 750°C, but if it is too high, the substrate will have the effect of being annealed.
Relatively low temperatures give better results.

このようにして基板上に結晶成長層を形成させると、基
板のイオン注入領域λは単結晶でなく、イオンの多量照
射による損傷によって、高密度の非晶質が形成している
ことに基いて結晶成長時に高密度欠陥が残留しているた
め、イオン注入領域直上に成長する結晶成長領域7は単
結晶でなく、多結晶が形成される。
When a crystal growth layer is formed on the substrate in this way, the ion-implanted region λ of the substrate is not a single crystal, but a high-density amorphous layer formed due to damage caused by a large amount of ion irradiation. Since high-density defects remain during crystal growth, the crystal growth region 7 that grows directly above the ion implantation region is not a single crystal but a polycrystal.

分子線結晶成長法にて所定の厚さの結晶成長層6が形成
したら、次に選択性のあるエツチング溶液を用いて結晶
成長層6をエツチング処理する。このエツチング処理は
公知の方法を採用することができ、エツチング溶液、処
理時間などを適当に選択することにより基板/のイオン
注入領域λ直上の結晶成長領域7のみがエツチング除去
され、イオン注入をしない領域上に形成した結晶成長領
域は殆んどエツチングによる減少は見られない。これは
イオン注入領域直上の結晶成長領域は前述の如く多結晶
であるためエツチング速度が単結晶と比べてはるかに大
きく、その結果、イオン注入領域直上の結晶成長領域の
みが優先的にエツチングされ、取り除かれ開口部ざが形
成するのである(第4図)。このとき、エツチングの横
の拡がりも当然に単結晶領域により阻止され、所定の領
域のみを正確に基板までエツチングを行うことになる。
After the crystal growth layer 6 of a predetermined thickness is formed by the molecular beam crystal growth method, the crystal growth layer 6 is then etched using a selective etching solution. This etching process can be carried out by a known method, and by appropriately selecting the etching solution, processing time, etc., only the crystal growth region 7 directly above the ion implantation region λ of the substrate is etched away, without ion implantation. The crystal growth region formed on the region shows almost no reduction due to etching. This is because the crystal growth region directly above the ion implantation region is polycrystalline as described above, so the etching rate is much higher than that for single crystal, and as a result, only the crystal growth region directly above the ion implantation region is etched preferentially. It is removed to form an opening (Fig. 4). At this time, the lateral spread of the etching is naturally prevented by the single crystal region, so that only a predetermined region is precisely etched to the substrate.

勿論エツチング条件を制御することによって基板/上の
イオン注入領、域までエツチング処理を行い、イオン注
入による損傷領域を除去することもできる。
Of course, by controlling the etching conditions, it is also possible to perform the etching process to the ion implanted region on the substrate and remove the damaged region caused by the ion implantation.

上記において、ウェットエツチング法を用いて基板のイ
オン注入領域直上に形成した結晶成長領域を取り除く方
法を説明したが、イオン注入領域上に形成された成長領
域は多結晶であるため、エツチングの方法は厳しく限定
されず、居スパッタリングや0at4ガスなどの反応ガ
スを用いたドライエツチング法を用いることもできる。
In the above, we explained how to remove the crystal growth region formed directly above the ion implantation region of the substrate using the wet etching method, but since the growth region formed on the ion implantation region is polycrystalline, the etching method is The method is not strictly limited, and dry etching methods using a reactive gas such as organic sputtering or Oat4 gas can also be used.

この発明は上記の説明で明らがなように、成長層の形成
する前に基板の成長層の加工部分に相当する領域に著量
のイオンを注入して非晶質とした上で結晶成長するため
上記領域上に形成した成長領域は多結晶となって、エツ
チングを行うと選択的に除去することができ、エツチン
グの深さは結晶成長層の膜厚により決まるため制御が容
易で、エツチング領域はイオン注入領域直上部分にのみ
限定され、横方向へのエツチングは抑制されるため正確
なエツチングが行われる。特にサブミクロンのオーダの
微細なエツチングを行うような場合、サブミクロンに集
束されたイオンビームを用いて直接に基板にパターンを
描写すれば良く、他に転写、位置合せなどの工程を必要
としないため極めて簡単、且つ正確に結晶成長層にエツ
チングを行うことができる。従って、結晶成長温度が比
較的低い温度で成長する半導体の微細加工について良好
な結果を得ることができる。更に基板上にGaAs /
AAGαA8  ヘテロ・エピタキシャル層を形成した
ときのエツチングにもこの発明を利用することができ、
光−電子集積回路などの半導体微細加工に大いに貢献す
ることになる。
As is clear from the above description, in this invention, before the growth layer is formed, a significant amount of ions are implanted into the region of the substrate corresponding to the processed portion of the growth layer to make it amorphous, and then crystal growth is performed. Therefore, the growth region formed on the above region becomes polycrystalline and can be selectively removed by etching, and the depth of etching is determined by the thickness of the crystal growth layer, making it easy to control. The region is limited to just above the ion implantation region, and lateral etching is suppressed, so that accurate etching can be performed. Particularly when performing fine etching on the order of submicrons, it is sufficient to draw the pattern directly on the substrate using an ion beam focused on submicrons, without the need for other processes such as transfer and alignment. Therefore, the crystal growth layer can be etched extremely easily and accurately. Therefore, good results can be obtained in microfabrication of semiconductors grown at relatively low crystal growth temperatures. Furthermore, GaAs/
This invention can also be used for etching when forming an AAGαA8 heteroepitaxial layer.
This will greatly contribute to the microfabrication of semiconductors such as opto-electronic integrated circuits.

次にこの発明の実施例を述べる。Next, embodiments of this invention will be described.

Orドープの半絶縁性GaAs結晶の上に結晶成長した
GaAs層を基板として用い、その表面の所定の領域に
直径0.1μmに集束したBeイオンビームを用いて5
 X 10”cy++−”の濃度で室温にて160 K
gVの加速エネルギーで注入した後に、このGaAs結
晶成長層基板上に更にGaAa結晶成長層を分子線成長
法にて2.5μmの厚さ形成した。結晶成長温度は60
0℃とした。次にこのGaAa結晶成長層をHF : 
H2O,: I(,0が1 : 1 : 10の混合比
のエツチング溶液を用いてエツチング処理をした。エツ
チング時間は30秒であって、基板のイオン注入直上の
GaA3結晶成長領域は全てエツチング除去され、イオ
ン注入領域直上以外のGaA8結晶成長領域はエツチン
グによる減少は殆ど示しておらず、イオン注入領域幅の
エツチングが形成していた。
Using a GaAs layer crystal-grown on an Or-doped semi-insulating GaAs crystal as a substrate, a Be ion beam focused to a diameter of 0.1 μm was applied to a predetermined area on the surface of the GaAs layer.
160 K at room temperature with a concentration of X 10"cy++-"
After implantation with acceleration energy of gV, a GaAa crystal growth layer with a thickness of 2.5 μm was further formed on the GaAs crystal growth layer substrate by molecular beam growth. Crystal growth temperature is 60
The temperature was 0°C. Next, this GaAa crystal growth layer is heated with HF:
Etching was performed using an etching solution with a mixing ratio of H2O,:I(,0) of 1:1:10.The etching time was 30 seconds, and the GaA3 crystal growth region immediately above the ion implantation of the substrate was completely etched away. The GaA8 crystal growth region other than directly above the ion implantation region showed almost no reduction due to etching, and the etching was formed by etching the width of the ion implantation region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の方法を実施するための一実施例を示す
斜視図、第2図は本発明の方法を実施するための他の実
施例を示す斜視図、第3図は本発明の方法により基板上
に結晶成長層を形成した状態を示す断面図、第4図は本
発明によるエツチング処理した状態の半導体の断面図で
ある。 l・・・基板結晶、コ・・・イオン注入領域、3・・・
イオン、6・・・結晶成長層、7・・・多結晶領域、ざ
・・・開口部。
FIG. 1 is a perspective view showing one embodiment for implementing the method of the present invention, FIG. 2 is a perspective view showing another embodiment for implementing the method of the present invention, and FIG. 3 is a perspective view showing another embodiment for implementing the method of the present invention. FIG. 4 is a cross-sectional view showing a state in which a crystal growth layer is formed on a substrate by the method, and FIG. 4 is a cross-sectional view of a semiconductor after being etched according to the present invention. l...substrate crystal, co...ion implantation region, 3...
ion, 6... crystal growth layer, 7... polycrystalline region, za... opening.

Claims (1)

【特許請求の範囲】[Claims] 結晶成長層を形成する基板表面上の結晶成長層の加工す
べき位置に対応する基板表面領域に非晶質が形成する濃
度のイオン注入を行い、次いで該基板表面上に結晶成長
層を形成し、形成した結晶成長層をエツチング処理をし
て基板のイオン注入領域直上の結晶成長領域のみを選択
的に除去することを特徴とする半導体微細加工方法。
Ion implantation is performed at a concentration that forms an amorphous substance in a region of the substrate surface corresponding to a position where the crystal growth layer is to be processed on the substrate surface where the crystal growth layer is to be formed, and then a crystal growth layer is formed on the substrate surface. A semiconductor microfabrication method characterized in that the formed crystal growth layer is etched to selectively remove only the crystal growth region immediately above the ion implantation region of the substrate.
JP8665683A 1983-05-19 1983-05-19 Fine processing for semiconductor Granted JPS59213135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8665683A JPS59213135A (en) 1983-05-19 1983-05-19 Fine processing for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8665683A JPS59213135A (en) 1983-05-19 1983-05-19 Fine processing for semiconductor

Publications (2)

Publication Number Publication Date
JPS59213135A true JPS59213135A (en) 1984-12-03
JPH0155574B2 JPH0155574B2 (en) 1989-11-27

Family

ID=13893071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8665683A Granted JPS59213135A (en) 1983-05-19 1983-05-19 Fine processing for semiconductor

Country Status (1)

Country Link
JP (1) JPS59213135A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256301A (en) * 1985-05-10 1986-11-13 Hitachi Ltd Production of semiconductor structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53104156A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Manufacture for semiconductor device
JPS55145344A (en) * 1979-05-02 1980-11-12 Agency Of Ind Science & Technol Mthod for surface profile processing of 3-5 group compound semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53104156A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Manufacture for semiconductor device
JPS55145344A (en) * 1979-05-02 1980-11-12 Agency Of Ind Science & Technol Mthod for surface profile processing of 3-5 group compound semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256301A (en) * 1985-05-10 1986-11-13 Hitachi Ltd Production of semiconductor structure

Also Published As

Publication number Publication date
JPH0155574B2 (en) 1989-11-27

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