JPS6484375A - Method for computing sum of products - Google Patents
Method for computing sum of productsInfo
- Publication number
- JPS6484375A JPS6484375A JP24061887A JP24061887A JPS6484375A JP S6484375 A JPS6484375 A JP S6484375A JP 24061887 A JP24061887 A JP 24061887A JP 24061887 A JP24061887 A JP 24061887A JP S6484375 A JPS6484375 A JP S6484375A
- Authority
- JP
- Japan
- Prior art keywords
- data
- product
- products
- sums
- low order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To speed up an operation processing time by dividing all the multiplicands and multipliers of respective product operations to high order and low order digit data by a data dividing means, matching the digit position of partial sums of products and adding them. CONSTITUTION:A processor 101 controls the operation of a storage device 102, a computing element 103 for the sum of products and a data converter 104 by control signals 112-114. In case of dividing double length data, the most significant bit(MSB) of low order digit data is added to the least signifi cant bit(LSB) of high order digit data. The product of high order side data, the product of the high and low order side data and the product of the low order side data out of the divided single length data are respectively applied to the computing element 103 to find out the sums of products, the obtained sums of products are matched at their digit position and then added to each other to execute product sum operation. Since correction due to the division of double length data can be executed by simple addition and respective partial product sums are previously calculated, the merits of the product sum computing elements for single length data can be effectively utilized. Consequently, the product sum operation of double length data can be rapidly executed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24061887A JPS6484375A (en) | 1987-09-28 | 1987-09-28 | Method for computing sum of products |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24061887A JPS6484375A (en) | 1987-09-28 | 1987-09-28 | Method for computing sum of products |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6484375A true JPS6484375A (en) | 1989-03-29 |
Family
ID=17062175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24061887A Pending JPS6484375A (en) | 1987-09-28 | 1987-09-28 | Method for computing sum of products |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6484375A (en) |
-
1987
- 1987-09-28 JP JP24061887A patent/JPS6484375A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0212571A3 (en) | Method and circuit for performing discrete transforms | |
EP0351242A3 (en) | Floating point arithmetic units | |
CA2008774A1 (en) | Modular multiplication method and the system for processing data | |
JPS5776635A (en) | Floating multiplying circuit | |
EP0380100A3 (en) | Multiplier | |
JPS6470827A (en) | Apparatus and method for performing shift operation within multipler array circuit | |
CA2119283A1 (en) | Multiplier Circuit and Division Circuit | |
EP0278529A3 (en) | Multiplication circuit capable of operating at a high speed with a small amount of hardware | |
EP0221425A3 (en) | Circuit for performing square root functions | |
JPS6484375A (en) | Method for computing sum of products | |
EP0326182A3 (en) | High speed digital signal processor for signed digit numbers | |
EP0314968A3 (en) | Overlapped multiple-bit scanning multiplication system with banded partial product matrix | |
JPS5330241A (en) | Arithmetic unit | |
JPS57113144A (en) | Stored program computer | |
JPS5663649A (en) | Parallel multiplication apparatus | |
EP0208238A3 (en) | High speed residue calculating apparatus | |
GB1395991A (en) | Electornic arrangement for the multiplication of a binary- coded number in a system having an even-numbered radix greater than 2 with a factor equal to half the radix of siad system of numbers | |
SU868751A1 (en) | Multiplier | |
JPS54159833A (en) | Decimal multiplier | |
JPS6484332A (en) | Arithmetic unit | |
SU1674162A1 (en) | Analog computing device | |
JPS57211643A (en) | Power calculating device | |
BARASHENKOV et al. | Method of acceleration of arithmetic calculations | |
JPS6488831A (en) | Parallel data multiplying circuit with sign processing function | |
JPS6429133A (en) | Norm calculation device |