JPS6482271A - Digital image processing circuit - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of each fundamental arithmetic circuit by not arranging respective arithmetic circuits independently of an image data bus but arranging them in series in the order of a multiplying circuit, an ALU, a bit shift circuit, and an LUT. CONSTITUTION:A multiplying circuit 301 outputs the product between a first image data input X to be processed and an input Y selectable by a selector 305. A constant in a constant register 306 or second image data to be processed is inputted as the input Y. An ALU 302 generates the result of addition, subtraction, or logic operation between an input A and an input B in an output F. The input B can be selected by a selector 307, and a constant in a constant register 308 or second image data to be processed is inputted as the input B. A bit shift circuit 303 generates the output which is (1/2)<n> or 2<n>-fold as large as the input by n-stage right shift or left shift [(n) is a positive integer]. A LUT 304 is a table memory for conversion from input data to arbitrary output data, and the input is outputted as it is if (input data)=(output data) is set.