JPS6481211A - Formation of semiconductor thin film - Google Patents

Formation of semiconductor thin film

Info

Publication number
JPS6481211A
JPS6481211A JP23832987A JP23832987A JPS6481211A JP S6481211 A JPS6481211 A JP S6481211A JP 23832987 A JP23832987 A JP 23832987A JP 23832987 A JP23832987 A JP 23832987A JP S6481211 A JPS6481211 A JP S6481211A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline
amorphous
crystallinity
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23832987A
Other languages
Japanese (ja)
Inventor
Satoshi Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23832987A priority Critical patent/JPS6481211A/en
Publication of JPS6481211A publication Critical patent/JPS6481211A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a silicon thin film good in its crystallinity by a simple method, by sequentially depositing a polycrystalline semiconductor layer as a lower layer and an amorphous semiconductor layer as an upper layer respectively on an insulated substrate and thereafter by performing heat treatment. CONSTITUTION:A CVD method of 650 deg.C or more in a growth temperature is used to deposit a polycrystalline Si layer 1-2 on an insulated substrate 1-1. Since the layer on this state is very small in its grain diameter and so irregular in its crystal orientation resulting in a variety in orientations, only the growth temperature is lowered to be 650 deg.C or below without interrupting the formation of the film. Thereupon an amorphous Si layer 1-4 is serially deposited on said polycrystalline Si layer 1-2, so that the polycrystalline Si layer as a lower layer and the amorphous Si layer as an upper layer are formed by one step of the CVD method. Next crystal growth of the amorphous Si layer 1-4 is performed by heat treatment to form an Si layer 1-5 good in its crystallinity. Since crystal growth of the amorphous Si layer begins with the polycrystalline Si layer serving as a seed crystal and the heat treatment is performed for long hours, only the crystal grains with a single crystalline bearing grow much and so a polycrystalline Si film large in its grain diameter can be obtained uniform in its orientation and good in its crystallinity.
JP23832987A 1987-09-22 1987-09-22 Formation of semiconductor thin film Pending JPS6481211A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23832987A JPS6481211A (en) 1987-09-22 1987-09-22 Formation of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23832987A JPS6481211A (en) 1987-09-22 1987-09-22 Formation of semiconductor thin film

Publications (1)

Publication Number Publication Date
JPS6481211A true JPS6481211A (en) 1989-03-27

Family

ID=17028590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23832987A Pending JPS6481211A (en) 1987-09-22 1987-09-22 Formation of semiconductor thin film

Country Status (1)

Country Link
JP (1) JPS6481211A (en)

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