JPS6481033A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS6481033A
JPS6481033A JP23724087A JP23724087A JPS6481033A JP S6481033 A JPS6481033 A JP S6481033A JP 23724087 A JP23724087 A JP 23724087A JP 23724087 A JP23724087 A JP 23724087A JP S6481033 A JPS6481033 A JP S6481033A
Authority
JP
Japan
Prior art keywords
instruction
field
value
decision
carried out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23724087A
Other languages
Japanese (ja)
Inventor
Takeshi Sakamura
Takuichirou Nakazawa
Ikuya Kawasaki
Atsushi Hasegawa
Kazuhiko Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP23724087A priority Critical patent/JPS6481033A/en
Publication of JPS6481033A publication Critical patent/JPS6481033A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To omit the calculation required for decision of the boundary crossing and also to shorten an instruction executing time, by using a limited bit field instruction that inhibits the decision of the boundary crossing carried out based on the offset value and the field value. CONSTITUTION:An instruction which handles a field covering >=2 word areas in a memory is prepared together with an instruction which handles a field included in a word. The latter instruction is equal to a limited bit field instruction where the offset value is received as the immediate value. This bit field instruction functions to prepare the decision for the boundary crossing to be carried out in the preceding and next steps, i.e., to designate the direction and the value of the bit shift processing carried out by a barrel shifter. Then an instruction error is decided and an instruction is issued to have a jump to an exception processing routine when it is decided that a bit field is crossing a boundary.
JP23724087A 1987-09-24 1987-09-24 Data processing system Pending JPS6481033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23724087A JPS6481033A (en) 1987-09-24 1987-09-24 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23724087A JPS6481033A (en) 1987-09-24 1987-09-24 Data processing system

Publications (1)

Publication Number Publication Date
JPS6481033A true JPS6481033A (en) 1989-03-27

Family

ID=17012466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23724087A Pending JPS6481033A (en) 1987-09-24 1987-09-24 Data processing system

Country Status (1)

Country Link
JP (1) JPS6481033A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5853177B2 (en) * 2011-04-08 2016-02-09 パナソニックＩｐマネジメント株式会社 Data processing apparatus and data processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5853177B2 (en) * 2011-04-08 2016-02-09 パナソニックＩｐマネジメント株式会社 Data processing apparatus and data processing method

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