JPS647733A - Multiplex demodulating circuit - Google Patents

Multiplex demodulating circuit

Info

Publication number
JPS647733A
JPS647733A JP16261187A JP16261187A JPS647733A JP S647733 A JPS647733 A JP S647733A JP 16261187 A JP16261187 A JP 16261187A JP 16261187 A JP16261187 A JP 16261187A JP S647733 A JPS647733 A JP S647733A
Authority
JP
Japan
Prior art keywords
signal
circuit
pilot signal
composite signal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16261187A
Other languages
Japanese (ja)
Inventor
Jun Kanda
Shujiro Azuma
Kaoru Yamamoto
Hiroshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP16261187A priority Critical patent/JPS647733A/en
Publication of JPS647733A publication Critical patent/JPS647733A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To digitally demodulate a composite signal with a simple constitution by separating a pilot signal from a digitally composite signal, delaying one side of both signals to other side, mutually making it into a negative phase, adding it and cancelling a pilot signal component. CONSTITUTION:A composite signal including a pilot signal is inputted to a filter 1, the noise component of the 1/12, 3/12, 5/12 and 6/12 of a sampling frequency fs is removed by adder circuits 11-13 and delaying circuits 14-16, controlled to a signal at a prescribed level with a multiplying circuit 2 and the pilot signal is separated by a BPF 3. The phase of the pilot signal is changed by 180 deg., an adder circuit 6 adds it with a composite signal delayed from a delay circuit 4 and the pilot signal is cancelled. On the other hand, the output of a BPF is inputted to a generating circuit 7 and a rectangular wave and an approximate sine wave are outputted from exclusive OR circuits 75 and 77. These signals are multiplied with the output of the circuit 6 by a multiplying circuit 8, a sub-voice signal is outputted, synthesized with a main voice signal by a matrix circuit 10 and a composite signal is demodulated.
JP16261187A 1987-06-30 1987-06-30 Multiplex demodulating circuit Pending JPS647733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16261187A JPS647733A (en) 1987-06-30 1987-06-30 Multiplex demodulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16261187A JPS647733A (en) 1987-06-30 1987-06-30 Multiplex demodulating circuit

Publications (1)

Publication Number Publication Date
JPS647733A true JPS647733A (en) 1989-01-11

Family

ID=15757889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16261187A Pending JPS647733A (en) 1987-06-30 1987-06-30 Multiplex demodulating circuit

Country Status (1)

Country Link
JP (1) JPS647733A (en)

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