JPS6476599A - Semiconductor memory inspecting system - Google Patents

Semiconductor memory inspecting system

Info

Publication number
JPS6476599A
JPS6476599A JP62233843A JP23384387A JPS6476599A JP S6476599 A JPS6476599 A JP S6476599A JP 62233843 A JP62233843 A JP 62233843A JP 23384387 A JP23384387 A JP 23384387A JP S6476599 A JPS6476599 A JP S6476599A
Authority
JP
Japan
Prior art keywords
memory cell
true
input signal
coincidence detecting
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62233843A
Other languages
Japanese (ja)
Inventor
Toshio Takeshima
Tadahide Takada
Masaaki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62233843A priority Critical patent/JPS6476599A/en
Publication of JPS6476599A publication Critical patent/JPS6476599A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain the parallel test of a memory cell to consider badness to fix the outputs of respective blocks in the same value and the influence of interference between bits by dividing into two memory cell block groups and parallel-testing each of them by using different data. CONSTITUTION:A true and a false data b1 and b2 are prepared by a writing circuit 1 and respectively written into every three memory cell blocks among, for example, six memory cell blocks 21-26. After that, read out data c1-c6 are checked by a comparing circuit 3, when they are in a true-false relation, the memory cell is decided to be good and when they are not in the true-false relation, it is decided to be bad. The comparing circuits 3 consists of a 2 input signal coincidence detecting circuits 31 and 32, 3 input signal coincidence detecting circuit 33 and 34 and 4 input signal coincidence detecting circuit 35. Thus, the test to consider the badness to fix the outputs of the respective blocks in the same value and the influence of the interference between the bits can be attained.
JP62233843A 1987-09-18 1987-09-18 Semiconductor memory inspecting system Pending JPS6476599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233843A JPS6476599A (en) 1987-09-18 1987-09-18 Semiconductor memory inspecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233843A JPS6476599A (en) 1987-09-18 1987-09-18 Semiconductor memory inspecting system

Publications (1)

Publication Number Publication Date
JPS6476599A true JPS6476599A (en) 1989-03-22

Family

ID=16961437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233843A Pending JPS6476599A (en) 1987-09-18 1987-09-18 Semiconductor memory inspecting system

Country Status (1)

Country Link
JP (1) JPS6476599A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161200A (en) * 1993-12-07 1995-06-23 Nec Corp Semiconductor memory and inspecting method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161200A (en) * 1993-12-07 1995-06-23 Nec Corp Semiconductor memory and inspecting method therefor

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