JPS6475954A - Electronic measuring device - Google Patents

Electronic measuring device

Info

Publication number
JPS6475954A
JPS6475954A JP23434787A JP23434787A JPS6475954A JP S6475954 A JPS6475954 A JP S6475954A JP 23434787 A JP23434787 A JP 23434787A JP 23434787 A JP23434787 A JP 23434787A JP S6475954 A JPS6475954 A JP S6475954A
Authority
JP
Japan
Prior art keywords
state
brought
inverter
potential
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23434787A
Other languages
Japanese (ja)
Inventor
Kazunari Naya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP23434787A priority Critical patent/JPS6475954A/en
Publication of JPS6475954A publication Critical patent/JPS6475954A/en
Pending legal-status Critical Current

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Landscapes

  • Measuring Temperature Or Quantity Of Heat (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

PURPOSE:To prevent an once-through current from flowing to an inverter, by providing a potential control means for fixing the potential of the input terminal of the inverter to an earth point or power supply voltage when all of switching means are brought to an OFF-state. CONSTITUTION:When both of try state buffers TSB1, TSB2 are brought to an output high impedance state by control signals CNT1, CNT2, the feedback circuit of an inverter INV is blocked and oscillation can be stopped. Moreover, when both of the control signals CNT1, CNT2 are brought to a low level and the outputs of two try state buffers TSB1, TSB2 are brought to a high impedance state, the output of an NOR gate G1 is changed to a high level. By this mechanism, the output of a try state buffer TSB3 becomes a low level and the input potential of the inverter INV is fixed to 0V. Therefore, the input terminal of the inverter INV becomes a floating state to prevent the flow of an once-through current.
JP23434787A 1987-09-18 1987-09-18 Electronic measuring device Pending JPS6475954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23434787A JPS6475954A (en) 1987-09-18 1987-09-18 Electronic measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23434787A JPS6475954A (en) 1987-09-18 1987-09-18 Electronic measuring device

Publications (1)

Publication Number Publication Date
JPS6475954A true JPS6475954A (en) 1989-03-22

Family

ID=16969574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23434787A Pending JPS6475954A (en) 1987-09-18 1987-09-18 Electronic measuring device

Country Status (1)

Country Link
JP (1) JPS6475954A (en)

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