JPS647536U - - Google Patents

Info

Publication number
JPS647536U
JPS647536U JP10147187U JP10147187U JPS647536U JP S647536 U JPS647536 U JP S647536U JP 10147187 U JP10147187 U JP 10147187U JP 10147187 U JP10147187 U JP 10147187U JP S647536 U JPS647536 U JP S647536U
Authority
JP
Japan
Prior art keywords
printing
image
line
stores
print head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10147187U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10147187U priority Critical patent/JPS647536U/ja
Publication of JPS647536U publication Critical patent/JPS647536U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Dot-Matrix Printers And Others (AREA)
JP10147187U 1987-06-30 1987-06-30 Pending JPS647536U (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10147187U JPS647536U (en:Method) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10147187U JPS647536U (en:Method) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS647536U true JPS647536U (en:Method) 1989-01-17

Family

ID=31330497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10147187U Pending JPS647536U (en:Method) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS647536U (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7521761B2 (en) * 2004-03-30 2009-04-21 Fujitsu Limited Variable layout structure for producing CMOS circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216029A (ja) * 1986-03-18 1987-09-22 Fujitsu Ltd 図形印刷制御方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216029A (ja) * 1986-03-18 1987-09-22 Fujitsu Ltd 図形印刷制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7521761B2 (en) * 2004-03-30 2009-04-21 Fujitsu Limited Variable layout structure for producing CMOS circuit

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