JPS647536U - - Google Patents

Info

Publication number
JPS647536U
JPS647536U JP10147187U JP10147187U JPS647536U JP S647536 U JPS647536 U JP S647536U JP 10147187 U JP10147187 U JP 10147187U JP 10147187 U JP10147187 U JP 10147187U JP S647536 U JPS647536 U JP S647536U
Authority
JP
Japan
Prior art keywords
printing
image
line
stores
print head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10147187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10147187U priority Critical patent/JPS647536U/ja
Publication of JPS647536U publication Critical patent/JPS647536U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を実施した描画像通信装置の構
成を示す図、第2図は第1図の画像メモリの読出
す区切りを示す模式図、第3図は第1図の動作状
態を示すフローチヤート、第4図、第5図は画像
メモリの記憶状態の一部を示す模式図、第6図は
画像メモリとの関係で印字方法を示す説明図、第
7図は従来例の画像メモリの読出す区切りを示す
模式図である。 1……入力装置、3……制御回路、5……画像
メモリ、7……表示装置、8……印字装置、9…
…データメモリ。
FIG. 1 is a diagram showing the configuration of an image communication device embodying the present invention, FIG. 2 is a schematic diagram showing the reading division of the image memory in FIG. 1, and FIG. 3 is a diagram showing the operating state of FIG. 1. Flowchart, Figures 4 and 5 are schematic diagrams showing part of the storage state of the image memory, Figure 6 is an explanatory diagram showing the printing method in relation to the image memory, and Figure 7 is a conventional image memory FIG. 1... Input device, 3... Control circuit, 5... Image memory, 7... Display device, 8... Printing device, 9...
...data memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 縦一列に配列された複数の印字素子を有した印
字ヘツドを左右方向へ移動して印字を行なうと共
に、無印字で紙送りを行なうラインスキツプ機能
を備えた印字手段と、画像データを記憶する画像
メモリと、画像メモリより印字ヘツドの印字素子
数の整数分の1に対応した単位で読出された画像
データを少なくとも1行分蓄積する印字バツフア
メモリと、画像メモリより読出したデータに基づ
き、ラインスツキプ或いは印字を行なうよう前記
印字手段を制御する制御手段で構成したことを特
徴とする画像印字装置。
Printing means equipped with a line skip function that prints by moving a print head having a plurality of printing elements arranged in a vertical line in the horizontal direction and also feeds paper without printing, and an image memory that stores image data. a print buffer memory that stores at least one line of image data read out from the image memory in units corresponding to an integer fraction of the number of printing elements of the print head; An image printing apparatus characterized by comprising a control means for controlling the printing means to perform the printing.
JP10147187U 1987-06-30 1987-06-30 Pending JPS647536U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10147187U JPS647536U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10147187U JPS647536U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS647536U true JPS647536U (en) 1989-01-17

Family

ID=31330497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10147187U Pending JPS647536U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS647536U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7521761B2 (en) * 2004-03-30 2009-04-21 Fujitsu Limited Variable layout structure for producing CMOS circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216029A (en) * 1986-03-18 1987-09-22 Fujitsu Ltd Graphic print control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216029A (en) * 1986-03-18 1987-09-22 Fujitsu Ltd Graphic print control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7521761B2 (en) * 2004-03-30 2009-04-21 Fujitsu Limited Variable layout structure for producing CMOS circuit

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