JPS647491B2 - - Google Patents
Info
- Publication number
- JPS647491B2 JPS647491B2 JP9155279A JP9155279A JPS647491B2 JP S647491 B2 JPS647491 B2 JP S647491B2 JP 9155279 A JP9155279 A JP 9155279A JP 9155279 A JP9155279 A JP 9155279A JP S647491 B2 JPS647491 B2 JP S647491B2
- Authority
- JP
- Japan
- Prior art keywords
- section
- etching
- wafer
- processing
- inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 claims description 38
- 235000012431 wafers Nutrition 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 32
- 238000007689 inspection Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 16
- 238000005259 measurement Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000012546 transfer Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 3
- 230000032258 transport Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007781 pre-processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Description
【発明の詳細な説明】
この発明はウエハ１枚処理エツチング・プロセ
スの使用に好適な処理装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing apparatus suitable for use in a single wafer etching process.
半導体装置の製造においては、半導体ウエハの
段階でウエハ表面に形成した各種物質の被膜を選
択的にエツチするエツチ処理が不可欠である。こ
のエツチ処理の形態は、例えばポリSiゲート形成
の場合第１図を参照し、下記のように行われる。
(a)Si結晶基板１上にポリSiあるいはSiO2，Si3N4
等の被処理膜２を形成する。(b)被処理膜とにフオ
トレジスト（感光性耐蝕膜３を塗布する、(c)感
光、現像等の写真処理を行いゲートに対応するレ
ジストマスク３ａを完成する。(d)レジスト・マス
クのパターン寸法ｌを測定する。(e)レジスト・マ
スクを通して被処理膜のエツチング（ドライエツ
チ又はウエツトエツチ）を行う。(f)レジストを除
去する（ウエツトプロセスの場合洗浄を伴う）。
(g)エツチされた被処理層（ゲート）２ａのパター
ン寸法l′を測定する。 In the manufacture of semiconductor devices, an etch process is essential for selectively etching coatings of various substances formed on the wafer surface at the semiconductor wafer stage. For example, in the case of forming a poly-Si gate, the etching process is performed as follows with reference to FIG.
(a) Poly-Si or SiO 2 , Si 3 N 4 on Si crystal substrate 1
A to-be-treated film 2 such as the following is formed. (b) Coat a photoresist (photosensitive corrosion-resistant film 3) on the film to be processed. (c) Perform photo processing such as exposure and development to complete a resist mask 3a corresponding to the gate. (d) Coat the resist mask 3a. Measure the pattern dimension l. (e) Etch the film to be processed (dry etching or wet etching) through the resist mask. (f) Remove the resist (cleaning is required in the case of a wet process).
(g) Measure the pattern dimension l' of the etched layer (gate) 2a.
このようなエツチ処理とそれに伴う各プロセス
は自動化の傾向にあるが、一般に各プロセス毎に
それぞれ自動機を使用して個別に処理が行われて
いる。例えば第２図に示すように寸法測定ａ，ｄ
には光学系を見えた半自動式検査機Ａが使われ、
エツチングｂにはエツチ・水洗自動機Ｂ、レジス
ト除去ｃには除去水洗自動機Ｃ等がそれぞれ使用
されている。各自動機Ａ，Ｂ，Ｃ…間は例えばウ
エハ25枚入りのカートリツジを手作業で移し換え
る等のため人手を要し非能率である。又前記した
ようなゲート形成の場合にエツチ後に線幅精度を
上げるためにレジストパターン寸法を測定し、そ
の結果に基づいてエツチ量を作業者が設定する
が、全数チエツクすると膨大な工数がかかり、一
方、抜取り検査するためには微細パターンでは問
題が多く充分に検査の結果が生かされない。 Although there is a trend toward automation of such etching processing and the processes associated with it, generally each process is individually performed using an automatic machine. For example, as shown in Figure 2, dimension measurements a, d
A semi-automatic inspection machine A that allows the optical system to be seen is used.
An automatic etching/washing machine B is used for etching b, and an automatic water washing machine C is used for resist removal c. For example, cartridges containing 25 wafers must be manually transferred between the automatic machines A, B, C, etc., which requires manpower and is inefficient. In addition, in the case of gate formation as described above, the resist pattern dimensions are measured after etching in order to improve the line width accuracy, and the operator sets the etching amount based on the results, but checking all the resist patterns requires a huge amount of man-hours. On the other hand, there are many problems with fine patterns for sampling inspection, and the inspection results cannot be fully utilized.
本発明は上記した従来技術の問題点を解消する
べくなされたものである。よつてこの発明の目的
は高精度のエツチングなどの処理が可能であり、
しかも作業人員を低減できる処理装置を提供する
ことにある。 The present invention has been made to solve the problems of the prior art described above. Therefore, the purpose of this invention is to enable processing such as high precision etching,
Moreover, it is an object of the present invention to provide a processing device that can reduce the number of workers.
上記発明の目的を達成するためこの発明の最も
シンプルな形態は、例えば第３図を参照し、ウエ
ハを１枚ごとに転送するためのローダ・アンロー
ダ部Ｆと、ウエハ上のレジストパターン及びエツ
チパターンの寸法を測定するための寸法外観検査
部Ａと、レジストをマスクとしてウエハ表面を選
択的にエツチするエツチング部Ｂと、エツチされ
たウエハ表面のレジストを取除くレジスト除去部
Ｃと、これら各部にわたつてウエハを搬送する搬
送手段Ｇ及びエツチング前後のパターン寸法測定
情報に基づいてエツチング量を制御するエツチン
グ量制御部Ｈとを具備し、また図示しないがウエ
ハのロツト管理、プロセス条件等を制御するもの
及び全体のシーケンスを制御する電気制御部を備
えてなる処理装置であることを特徴とする。この
第３図で示した処理装置は各処理部を一列に配置
した場合の例であつて、ローダ・アンローダ部Ｆ
及び寸法外観検査部Ａはそれぞれ２個あつて両端
に配置される。なお、エツチング量制御部Ｈは他
の処理部例えば検査部等に内蔵される。 In order to achieve the above object of the invention, the simplest form of the invention, as shown in FIG. A dimensional appearance inspection section A for measuring the dimensions of the wafer, an etching section B for selectively etching the wafer surface using a resist as a mask, and a resist removal section C for removing the resist from the etched wafer surface. It is equipped with a transport means G that transports the wafer across, and an etching amount control section H that controls the etching amount based on pattern dimension measurement information before and after etching, and also controls wafer lot management, process conditions, etc. (not shown). The processing device is characterized by being equipped with an electric control unit that controls the processing and the entire sequence. The processing apparatus shown in FIG. 3 is an example in which each processing section is arranged in a row, and the loader/unloader section F
There are two dimensional and visual inspection sections A, and they are arranged at both ends. Note that the etching amount control section H is built in another processing section, such as an inspection section.
第４図及び第５図は本発明をポリSiエツチ工程
一貫処理装置に適用した一実施例を示し、Ｆはロ
ーダ・アンローダ部、Ａはバイパスを有する寸法
外観検査部、Ｂはプラズマ・エツチ部、Ｉはサブ
ローダ・アンローダ部を有するＵ字形搬送部、Ｃ
はプラズマによるレジスト除去部、Ｄは必要に応
じて設けられる洗浄処理部であり、これら各処理
部間にはベルトコンベア又はエアベアリング等の
搬送手段Ｇを有し、ウエハを１枚ごとに移送する
ようになつている。以下各処理部について詳述す
る。 4 and 5 show an embodiment in which the present invention is applied to a poly-Si etch process integrated processing apparatus, where F is a loader/unloader section, A is a dimensional appearance inspection section with a bypass, and B is a plasma etching section. , I is a U-shaped conveyor section having a subloader/unloader section, C
is a resist removal section using plasma, and D is a cleaning processing section provided as necessary. A conveying means G such as a belt conveyor or air bearing is provided between these processing sections to transfer wafers one by one. It's becoming like that. Each processing section will be explained in detail below.
ローダ・アンローダ部Ｆは矢印INよりカート
リツジごと未処理をセツトしてウエハ１枚ごとに
供給する間欠回転により転送する円板式ローダ４
と、処理されたウエハをOUTより取出す円板式
アンローダ５とを１つのユニツトにセツトしたも
のである。 The loader/unloader section F is a disc-type loader 4 that loads the unprocessed cartridges from the arrow IN and transfers them by intermittent rotation to feed each wafer one by one.
and a disk-type unloader 5 for taking out the processed wafer from the OUT are set in one unit.
寸法外観検査部（以下検査部と称す）Ａは第６
Ａ図、第６Ｂ図に示すように対物レンズを具えた
寸法外観検査機構６、ウエハを選択的に移送する
ためのゲート９を有するバイパス７、サブローダ
部８ａ、サブアンローダ部８ｂからなる。ロー
ダ・アンローダ部Ｆから送られた処理前のウエハ
群のうち、例えば25枚中の２〜３枚は抜き取られ
て第６Ａ図の実線の矢印にそつて進み検査機構６
の中に位置決めセツトされてレジストパターン寸
法を測定され、その測定結果は記憶されエツチ量
制御部Ｈに送られる。他の23枚はローダ部Ｆによ
つて同図の破線の矢印で示すバイパス７ａ，７
ｂ，７ｃにそつて進み、検査されたウエハと共通
の出口１０から次のエツチ部のユニツトＢへ転送
される。 Dimension and appearance inspection department (hereinafter referred to as inspection department) A is the 6th
As shown in FIGS. A and 6B, it consists of a dimensional appearance inspection mechanism 6 equipped with an objective lens, a bypass 7 having a gate 9 for selectively transferring wafers, a sub-loader section 8a, and a sub-unloader section 8b. Among the group of unprocessed wafers sent from the loader/unloader section F, for example, 2 to 3 out of 25 wafers are extracted and advanced along the solid line arrow in FIG. 6A to the inspection mechanism 6.
The resist pattern dimension is measured, and the measurement results are stored and sent to the etching amount control section H. The other 23 sheets are bypassed by the loader section F and bypasses 7a and 7 indicated by the broken line arrows in the same figure.
b, 7c, and is transferred to unit B of the next etching section through an exit 10 common to the inspected wafer.
エツチ処理された後のウエハ群は第６Ｂ図の実
線の矢印にそつてバイパス７ｄを通り、このうち
抜き取られた２〜３枚はパイパス７ａを前記の経
路と逆行して検査部６に入つてエツチ後のパター
ン寸法が測定され、バイパス７ｃを経てバイパス
７ｄで地の23枚の進行に合流し、ローダ・アンロ
ーダ部Ｆのアンローダ部５に転送される。 The group of etched wafers passes through the bypass 7d along the solid arrow in FIG. 6B, and the two or three extracted wafers go through the bypass 7a in the opposite direction to the above-mentioned path and enter the inspection section 6. The pattern size after etching is measured, passes through the bypass 7c, merges with the advancing 23 sheets at the bypass 7d, and is transferred to the unloader section 5 of the loader/unloader section F.
プラズマエツチ部Ｂは前処理部１１と本処理部
１２とから成り、本処理部で送入されたウエハに
対しCF4ガス、O2ガス中でプラズマ放電によりレ
ジストから露出するポリSiをエツチしてポリSiゲ
ートを形成する。 The plasma etching section B consists of a pre-processing section 11 and a main processing section 12, and the main processing section etches the poly-Si exposed from the resist by plasma discharge in CF 4 gas and O 2 gas on the wafer sent in. to form a poly-Si gate.
Ｕ字形搬送部Ｉはこれによつて諸処理ユニツト
の配列を２列に構成し、同一端（ローダ・アンロ
ーダ部）でウエハの出し入れを行うとともに、エ
ツチ処理前と後とでの寸法外観検査を一つの検査
機構で検査を可能とした。サブローダ・アンロー
ダ部１３はエツチ後に選択酸化膜形成前のストツ
パ用不純物イオン打込み等の他の工程を必要とす
る場合にウエハを取出し、取入れるために用いる
ためのものである。 The U-shaped transfer section I has various processing units arranged in two rows, and wafers are loaded and unloaded at the same end (loader/unloader section), and the dimensional appearance can be inspected before and after etching processing. Inspection is now possible with a single inspection mechanism. The subloader/unloader section 13 is used to take out and take in the wafer when other steps such as implantation of impurity ions for a stopper before forming a selective oxide film are required after etching.
レジスト除去部Ｃは、エツチされたウエハにお
いて不要となつたレジストをO2ガス中でプラズ
マ放電により除去するためのものである。 The resist removal section C is for removing unnecessary resist from the etched wafer by plasma discharge in O 2 gas.
洗浄処理部Ｄはプラズマエツチによるレジスト
除去の際に被処理物中に残留するレジスト中の不
純物イオンを酸処理より除去するためのものであ
る。この洗浄処理部は必ずしもこの一貫処理装置
の中に含ませなくともよく後段の処理装置で前洗
浄部として設置しても良い。 The cleaning processing section D is for removing impurity ions in the resist remaining in the object to be processed when the resist is removed by plasma etching by acid treatment. This cleaning processing section does not necessarily need to be included in this integrated processing device, and may be installed as a pre-cleaning section in a subsequent processing device.
エツチ量制御部Ｈは検査部又はプラズマエツチ
部に内蔵され、エツチング前後のパターン寸法測
定により得られた情報に基づいてエツチ量制御系
数を補正しプラズマエツチ部におけるエツチ処理
の制御動作を指令するためのものである。 The etch amount control section H is built in the inspection section or the plasma etch section, and is used to correct the etch amount control system based on information obtained by measuring pattern dimensions before and after etching, and to command the control operation of the etch process in the plasma etch section. belongs to.
上記構成の一貫処理装置によつて(1)ローダ・ア
ンローダ部のローダ部にセツトされたカートリツ
ジから出たウエハは自動的に検査部（一部技取
り）、プラズマエツチ部、レジスト除去部、洗浄
部、検査部（一部技取り）を経てアンローダのア
ートリツジに入り(2)エツチ前後の検査によつて適
正なエツチ量制御をなす諸動作を自動的に行う。
エツチング後の寸法公差は従来のものに比較して
高精度が可能となつた。 With the integrated processing equipment configured as described above, (1) Wafers taken out from the cartridge set in the loader section of the loader/unloader section are automatically transferred to the inspection section (some techniques are required), the plasma etch section, the resist removal section, and the cleaning section. It enters the art storage of the unloader through the inspection section and inspection section (partially technical), and (2) automatically performs various operations to control the appropriate amount of etching through inspection before and after etching.
The dimensional tolerance after etching has become more accurate than that of conventional etching.
第７図は第４図の一貫処理装置を各処理部Ｆ，
Ａ，Ｂ，…ごとにユニツト（ブロツク）化した場
合の実施例を示す、各ユニツトにおいてはウエハ
の出入搬路にそれぞれストツカ乃至転送部１４を
設け、この転送部を介して各ユニツトを連結でき
るようにする。このようなブロツク化により、各
種のユニツトを必要に応じて交換し、附加しある
いは省略することができる。 Figure 7 shows the integrated processing device in Figure 4 with each processing section F,
An example is shown in which wafers A, B, ... are formed into units (blocks). Each unit is provided with a stocker or transfer section 14 on the wafer loading/unloading path, and each unit can be connected via this transfer section. Do it like this. By forming blocks in this manner, various units can be replaced, added, or omitted as necessary.
以上、実施例で述べた本発明によれば(1)一貫処
理化により人員が低減できる、(2)検査の自動化に
より高精度のエツチングが可能となる、(3)各処理
部の配列、ユニツト化により、設置スペースを小
さくできる等の効果を奏する。 As described above, according to the present invention described in the examples, (1) the number of personnel can be reduced by integrated processing, (2) highly accurate etching is possible by automating inspection, and (3) the arrangement of each processing section and unit can be improved. This has the effect of reducing the installation space.
本発明は前記実施例に限定されず、これ以外の
種々の変形例を有する。実施例ではプラズマ装置
を利用したドライエツチ法を示したが、ウエツト
エツチ法の場合にも同様に本発明を適用できる。 The present invention is not limited to the above-mentioned embodiments, and has various other modifications. In the embodiment, a dry etching method using a plasma apparatus is shown, but the present invention can be similarly applied to a wet etching method.
ローダ・アンローダ等の各処理部間の転送手段
としては電磁ソレノイドを使用した直動型、シー
ソー方式、回転方式その他を任意に採用すること
ができる。 As the transfer means between each processing unit such as a loader/unloader, a direct-acting type using an electromagnetic solenoid, a seesaw type, a rotation type, or the like can be arbitrarily adopted.
本発明はポリSi，SiO2，Si3N4等の被膜、Al
膜、PSG（リン・シリケート・ガラス）膜等、ウ
エハ上に形成する各種の被膜のエツチ処理を対象
とする。 The present invention is applicable to coatings such as poly-Si, SiO 2 , Si 3 N 4 , etc.
The target is the etching process of various films formed on wafers, such as films and PSG (phosphorus silicate glass) films.
第１図ａ〜ｇは本発明の対象となるポリSiエツ
チ工程の各断面図、第２図ａ〜ｄはエツチ工程と
従来の処理装置を対応させたブロツク線図であ
る。第３図は本発明による処理装置の一実施例の
概略平面図、第４図は本発明による処理装置の他
の実施例の概略平面図、第５図は同じく他の実施
例の斜面図、第６Ａ図及び第６Ｂ図は同じく他の
実施例の検査部におけるウエハの動きを示す一部
平面図、第７図は本発明による処理装置をユニツ
ト化した実施例の概略平面図である。
１……検査部、Ｂ……エツチ部、Ｃ……レジス
ト除去部、Ｄ……エツチ洗浄部、Ｅ……検査部、
Ｆ……ローダ・アンローダ部、Ｇ……搬送手段、
Ｈ……エツチング量制御部、Ｉ……Ｕ字形搬送
部、１……Si結晶基板、２……被処理膜（Si）、
２ａ……Siゲート、３……フオトレジスト、３ａ
……レジストマスク、４……ローダ、５……アン
ローダ、６……寸法外観検査機構、７，７ａ，７
ｂ……バイパス、８ａ……ローダ部、８ｂ……サ
ブローダ部、９……ゲート、１０……出口、１１
……前処理部、１２……本処理部、１３……サブ
ローダ・アンローダ部、１４……転送部。
1A to 1G are cross-sectional views of the poly-Si etch process to which the present invention is applied, and FIGS. 2A to 2D are block diagrams showing the correspondence between the etch process and conventional processing equipment. FIG. 3 is a schematic plan view of one embodiment of the processing apparatus according to the present invention, FIG. 4 is a schematic plan view of another embodiment of the processing apparatus according to the present invention, and FIG. 5 is a perspective view of another embodiment. 6A and 6B are partial plan views showing the movement of a wafer in the inspection section of another embodiment, and FIG. 7 is a schematic plan view of an embodiment in which the processing apparatus according to the present invention is integrated into a unit. 1...Inspection section, B...Etch section, C...Resist removal section, D...Etch cleaning section, E...Inspection section,
F...Loader/unloader section, G...Transportation means,
H... Etching amount control unit, I... U-shaped transport unit, 1... Si crystal substrate, 2... Film to be processed (Si),
2a...Si gate, 3...Photoresist, 3a
...Resist mask, 4...Loader, 5...Unloader, 6...Dimension and appearance inspection mechanism, 7, 7a, 7
b...Bypass, 8a...Loader section, 8b...Subloader section, 9...Gate, 10...Exit, 11
. . . Preprocessing section, 12 . . . Main processing section, 13 . . . Subloader/unloader section, 14 . . . Transfer section.
Claims (1)
アンローダ部と、ウエハ上のパターン寸法を測定
する検査部と、ウエハ表面の被処理物を選択的に
エツチするエツチ部と、ウエハ表面の選択エツチ
用レジストを除去するレジスト除去部と、上記各
処理部間にわたつてウエハを搬送する搬送手段及
び、検査部において測定したパターン寸法測定結
果に基づいて所望のパターン寸法が得られるよう
にエツチング量を制御するエツチング量制御部と
を具備し、ウエハを連続して処理することを特徴
とする処理装置。 ２ ウエハの搬送路の平面形状をＵ字状に形成
し、一つの検査部によつてエツチ前とエツチ後の
パターン寸法測定を行うようにした特許請求の範
囲第１項記載の処理装置。 ３ 各処理部にウエハ搬送路を連設させたユニツ
トとし、各ユニツト間を相互に連結乃至分離でき
るようにした特許請求の範囲第１項又は第２項記
載の処理装置。[Claims] 1. A loader that delivers or stores wafers one by one.
An unloader section, an inspection section that measures pattern dimensions on the wafer, an etch section that selectively etch the object to be processed on the wafer surface, a resist removal section that removes resist for selective etching on the wafer surface, and each of the above processes. The wafer is equipped with a transport means for transporting the wafer between sections, and an etching amount control section for controlling the etching amount so that a desired pattern dimension is obtained based on the pattern dimension measurement results measured in the inspection section. A processing device characterized by continuous processing. 2. The processing apparatus according to claim 1, wherein the planar shape of the wafer transport path is formed into a U-shape, and pattern dimensions are measured before and after etching by one inspection section. 3. The processing apparatus according to claim 1 or 2, which is a unit in which each processing section is connected to a wafer transport path, and each unit can be interconnected or separated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9155279A JPS5617022A (en) | 1979-07-20 | 1979-07-20 | Treating apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9155279A JPS5617022A (en) | 1979-07-20 | 1979-07-20 | Treating apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5617022A JPS5617022A (en) | 1981-02-18 |
| JPS647491B2 true JPS647491B2 (en) | 1989-02-09 |
Family
ID=14029655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9155279A Granted JPS5617022A (en) | 1979-07-20 | 1979-07-20 | Treating apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5617022A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249328A (en) * | 1984-05-25 | 1985-12-10 | Kokusai Electric Co Ltd | Apparatus for dry-etching and chemical vapor-phase growth of semiconductor wafer |
| JPH0736400B2 (en) * | 1985-12-23 | 1995-04-19 | 東洋設備工業株式会社 | Wafer etching equipment |
| KR100675316B1 (en) * | 1999-12-22 | 2007-01-26 | 엘지.필립스 엘시디 주식회사 | Unification Type Cleaning and Etch/ Strip Apparatus |
| JP3686866B2 (en) * | 2001-12-18 | 2005-08-24 | 株式会社日立製作所 | Semiconductor manufacturing apparatus and manufacturing method |
-
1979
- 1979-07-20 JP JP9155279A patent/JPS5617022A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5617022A (en) | 1981-02-18 |
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