JPS6470794A - Display device - Google Patents

Display device

Info

Publication number
JPS6470794A
JPS6470794A JP62226891A JP22689187A JPS6470794A JP S6470794 A JPS6470794 A JP S6470794A JP 62226891 A JP62226891 A JP 62226891A JP 22689187 A JP22689187 A JP 22689187A JP S6470794 A JPS6470794 A JP S6470794A
Authority
JP
Japan
Prior art keywords
bit
register
attribute code
attribute
displayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62226891A
Other languages
Japanese (ja)
Inventor
Hiroshi Uruga
Toshiyuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62226891A priority Critical patent/JPS6470794A/en
Publication of JPS6470794A publication Critical patent/JPS6470794A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To reduce storage capacity of an attribute code storage device by providing a register for the attribute code specifying a display condition, switching the register information and thereby enabling a plurality of bits of attribute information to be specified. CONSTITUTION: With a switching register 22 added for an attribute code storage device, the bit 4 of the attribute code is shared by a vertical line VL and a brief graphic BG. At no time are VL and BG specified simultaneously. The register 22 is 8 bit structured; with contents '0' in the bit 4 of the register 22, the bit 4 of the attribute code comparable to 1,000 characters all specifies VL; if the bit 4 of the attribute code is '0', ordinary characters are displayed, and if '1', VL is displayed. With contents '1' in the bit 4 of the register 22, the bit 4 of the attribute code comparable to 1,000 characters specifies BG; if the bit 4 of the code is '0', ordinary characters are displayed, and if '1', BG is displayed. With this structure, the specification of the attribute information can be reduced from 9 bit to 8 bit, requiring 1,000 byte memory, a half of the conventional capacity.
JP62226891A 1987-09-10 1987-09-10 Display device Pending JPS6470794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62226891A JPS6470794A (en) 1987-09-10 1987-09-10 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226891A JPS6470794A (en) 1987-09-10 1987-09-10 Display device

Publications (1)

Publication Number Publication Date
JPS6470794A true JPS6470794A (en) 1989-03-16

Family

ID=16852203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226891A Pending JPS6470794A (en) 1987-09-10 1987-09-10 Display device

Country Status (1)

Country Link
JP (1) JPS6470794A (en)

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