JPS6469041A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS6469041A
JPS6469041A JP22685687A JP22685687A JPS6469041A JP S6469041 A JPS6469041 A JP S6469041A JP 22685687 A JP22685687 A JP 22685687A JP 22685687 A JP22685687 A JP 22685687A JP S6469041 A JPS6469041 A JP S6469041A
Authority
JP
Japan
Prior art keywords
leads
die pad
inner leads
lead frame
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22685687A
Other languages
Japanese (ja)
Other versions
JPH0834281B2 (en
Inventor
Koji Nose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP62226856A priority Critical patent/JPH0834281B2/en
Publication of JPS6469041A publication Critical patent/JPS6469041A/en
Publication of JPH0834281B2 publication Critical patent/JPH0834281B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the drawing strength of leads by intruding an inner lead pattern to a die pad section and positioning the base of the die pad where upper than the top face of the inner lead pattern. CONSTITUTION:One parts of a die pad 3, on which a semiconductor chip 2 is loaded, in a lead frame 1 are cut off conformed to the shape of inner leads 4. The lead frame 1 is arranged so that one parts 6 of leads constituting the inner leads 4 are intruded to the cut-off sections 5. The working of depressing bending sections 8 is executed to hanging leads 7 hanging the die pad 3. The inner leads 4 are bent so that the base of the die pad 3 is made higher than the inner leads 4 in order to prevent the contacts of semiconductor chips 4 and the inner leads 4 on assembly. Plating regions 9 plated with gold or silver are shaped at the nose sections of each of the die pad 3 and the inner leads 4 for the lead frame 1. Accordingly, the lowering of moisture resistance and the drawing strength of the leads can be reduced by the shape of the inner leads disposed and extended to one parts of the die pad when semiconductor package structure is formed.
JP62226856A 1987-09-10 1987-09-10 Semiconductor device Expired - Lifetime JPH0834281B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62226856A JPH0834281B2 (en) 1987-09-10 1987-09-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226856A JPH0834281B2 (en) 1987-09-10 1987-09-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6469041A true JPS6469041A (en) 1989-03-15
JPH0834281B2 JPH0834281B2 (en) 1996-03-29

Family

ID=16851641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226856A Expired - Lifetime JPH0834281B2 (en) 1987-09-10 1987-09-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0834281B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198883A (en) * 1988-08-06 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor device having an improved lead arrangement and method for manufacturing the same
DE4318727A1 (en) * 1992-06-05 1993-12-09 Mitsubishi Electric Corp Semiconductor device with lead-on-chip-structure - has brazing solder material with no moisture absorption, formed on surface of semiconductor component and fixed to support plate
US5519576A (en) * 1994-07-19 1996-05-21 Analog Devices, Inc. Thermally enhanced leadframe
DE4345305C2 (en) * 1992-06-05 1998-04-09 Mitsubishi Electric Corp Semiconductor device with lead-on-chip-structure
JP2010283394A (en) * 2010-09-21 2010-12-16 Renesas Electronics Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154764A (en) * 1985-12-27 1987-07-09 Hitachi Ltd Resin sealed semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154764A (en) * 1985-12-27 1987-07-09 Hitachi Ltd Resin sealed semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198883A (en) * 1988-08-06 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor device having an improved lead arrangement and method for manufacturing the same
DE4318727A1 (en) * 1992-06-05 1993-12-09 Mitsubishi Electric Corp Semiconductor device with lead-on-chip-structure - has brazing solder material with no moisture absorption, formed on surface of semiconductor component and fixed to support plate
US5724726A (en) * 1992-06-05 1998-03-10 Mitsubishi Denki Kabushiki Kaisha Method of making leadframe for lead-on-chip (LOC) semiconductor device
DE4318727C2 (en) * 1992-06-05 1998-03-12 Mitsubishi Electric Corp Process for the production of a semiconductor device with LOC structure and associated leadframe
DE4345305C2 (en) * 1992-06-05 1998-04-09 Mitsubishi Electric Corp Semiconductor device with lead-on-chip-structure
US5900582A (en) * 1992-06-05 1999-05-04 Mitsubishi Denki Kabushiki Kaisha Lead frame including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the lead frame
DE4345301C2 (en) * 1992-06-05 2003-11-20 Mitsubishi Electric Corp Lead wire frames for use in manufacturing a LOC structure semiconductor device and method of manufacturing a LOC structure semiconductor device
DE4345303C2 (en) * 1992-06-05 2003-12-04 Mitsubishi Electric Corp Lead wire frames for use in manufacturing a LOC structure semiconductor device and method for manufacturing a LOC structure semiconductor device
DE4345302C2 (en) * 1992-06-05 2003-12-11 Mitsubishi Electric Corp A method of manufacturing a LOC structure semiconductor device and lead wire frames for use in manufacturing a LOC structure semiconductor device
US5519576A (en) * 1994-07-19 1996-05-21 Analog Devices, Inc. Thermally enhanced leadframe
JP2010283394A (en) * 2010-09-21 2010-12-16 Renesas Electronics Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0834281B2 (en) 1996-03-29

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