JPS6466726A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS6466726A
JPS6466726A JP22310887A JP22310887A JPS6466726A JP S6466726 A JPS6466726 A JP S6466726A JP 22310887 A JP22310887 A JP 22310887A JP 22310887 A JP22310887 A JP 22310887A JP S6466726 A JPS6466726 A JP S6466726A
Authority
JP
Japan
Prior art keywords
signal
analog
conversion
circuit
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22310887A
Other languages
Japanese (ja)
Inventor
Hideo Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22310887A priority Critical patent/JPS6466726A/en
Publication of JPS6466726A publication Critical patent/JPS6466726A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the processing efficiency of a data processor and to perform the digital processing of data at a high speed, by applying the A/D conversion to the analog signal based on a start signal and taking out the hold digital signal after a prescribed time. CONSTITUTION:An S/H amplifier 21 samples and holds the analog signals applied to an input terminal 1 at the prescribed time intervals based on the sampling/holding signal S10 received from an A/D conversion control circuit 27. Then the held analog signal is applied to an A/D converting circuit 23. The circuit 23 receives the analog held by the amplifier 21 and starts the A/D conversion when a conversion start signal 11 is given from the circuit 27 to convert the analog signal into the 8-bit digital signals ADO-AD7. Thus a microcomputer 31 interrupts its processing under execution and reads the digital signal out of a register 29 to process an arithmetic operation, etc.
JP22310887A 1987-09-08 1987-09-08 Analog/digital converter Pending JPS6466726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22310887A JPS6466726A (en) 1987-09-08 1987-09-08 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22310887A JPS6466726A (en) 1987-09-08 1987-09-08 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS6466726A true JPS6466726A (en) 1989-03-13

Family

ID=16792950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22310887A Pending JPS6466726A (en) 1987-09-08 1987-09-08 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6466726A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer
JPWO2020137656A1 (en) * 2018-12-25 2021-12-23 京セラ株式会社 Analog / digital converters, wireless communication devices, and analog / digital converters

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer
JPWO2020137656A1 (en) * 2018-12-25 2021-12-23 京セラ株式会社 Analog / digital converters, wireless communication devices, and analog / digital converters

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