JPS6460017A - Flip flop - Google Patents

Flip flop

Info

Publication number
JPS6460017A
JPS6460017A JP62214189A JP21418987A JPS6460017A JP S6460017 A JPS6460017 A JP S6460017A JP 62214189 A JP62214189 A JP 62214189A JP 21418987 A JP21418987 A JP 21418987A JP S6460017 A JPS6460017 A JP S6460017A
Authority
JP
Japan
Prior art keywords
signal
latch circuit
propagation
sent
direct current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62214189A
Other languages
Japanese (ja)
Other versions
JP2681938B2 (en
Inventor
Tomihiro Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62214189A priority Critical patent/JP2681938B2/en
Priority to EP19880114042 priority patent/EP0305941B1/en
Priority to DE19883875878 priority patent/DE3875878T2/en
Publication of JPS6460017A publication Critical patent/JPS6460017A/en
Application granted granted Critical
Publication of JP2681938B2 publication Critical patent/JP2681938B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the increase of a propagation delay time due to a saturation condition and to attain a faster action, by shifting a propagation signal, which is sent from a first latch circuit to a second latch circuit, to the signal with a smaller logical amplitude and with a lower direct current level than that of an input/output signal with the outside of the circuit, and operating the propagation signal. CONSTITUTION:Only a propagation signal DM sent from a first latch circuit 95 to a second latch circuit 96 is shifted to the signal with a smaller logical amplitude and with a lower direct current level than those of the input/output signals D1, D2, S1, S2 and Dout, and operated. Thus, the collector potential of a transistor 7 does not become lower until it is saturated compared with the base potential, and as this result, the delay of the propagation delay time of the slave latch circuit 96 can be prevented, and the faster action is attained.
JP62214189A 1987-08-29 1987-08-29 Flip flop Expired - Lifetime JP2681938B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62214189A JP2681938B2 (en) 1987-08-29 1987-08-29 Flip flop
EP19880114042 EP0305941B1 (en) 1987-08-29 1988-08-29 Flipflop which is operable at high speed and adapted to implementation as an integrated circuit
DE19883875878 DE3875878T2 (en) 1987-08-29 1988-08-29 HIGH-SPEED OPERATIONAL FLIPFLOP SUITABLE FOR IMPLEMENTATION AS AN INTEGRATED CIRCUIT.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214189A JP2681938B2 (en) 1987-08-29 1987-08-29 Flip flop

Publications (2)

Publication Number Publication Date
JPS6460017A true JPS6460017A (en) 1989-03-07
JP2681938B2 JP2681938B2 (en) 1997-11-26

Family

ID=16651713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214189A Expired - Lifetime JP2681938B2 (en) 1987-08-29 1987-08-29 Flip flop

Country Status (1)

Country Link
JP (1) JP2681938B2 (en)

Also Published As

Publication number Publication date
JP2681938B2 (en) 1997-11-26

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