JPS6459941A - Method of forming conductive stud - Google Patents
Method of forming conductive studInfo
- Publication number
- JPS6459941A JPS6459941A JP63148460A JP14846088A JPS6459941A JP S6459941 A JPS6459941 A JP S6459941A JP 63148460 A JP63148460 A JP 63148460A JP 14846088 A JP14846088 A JP 14846088A JP S6459941 A JPS6459941 A JP S6459941A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- substrate
- exposed
- metal
- positive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/945—Special, e.g. metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/959—Mechanical polishing of wafer
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86120 | 1987-08-17 | ||
US07/086,120 US4758306A (en) | 1987-08-17 | 1987-08-17 | Stud formation method optimizing insulator gap-fill and metal hole-fill |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6459941A true JPS6459941A (en) | 1989-03-07 |
JPH0682759B2 JPH0682759B2 (ja) | 1994-10-19 |
Family
ID=22196409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63148460A Expired - Lifetime JPH0682759B2 (ja) | 1987-08-17 | 1988-06-17 | 導電性スタツドの形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4758306A (ja) |
EP (1) | EP0303823B1 (ja) |
JP (1) | JPH0682759B2 (ja) |
DE (1) | DE3868178D1 (ja) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63104425A (ja) * | 1986-10-09 | 1988-05-09 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | バイアの形成方法 |
US5307903A (en) * | 1988-01-29 | 1994-05-03 | Hitachi, Ltd. | Method and system of controlling elevators and method and apparatus of inputting requests to the control system |
US4952274A (en) * | 1988-05-27 | 1990-08-28 | Northern Telecom Limited | Method for planarizing an insulating layer |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5217566A (en) * | 1991-06-06 | 1993-06-08 | Lsi Logic Corporation | Densifying and polishing glass layers |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5169802A (en) * | 1991-06-17 | 1992-12-08 | Hewlett-Packard Company | Internal bridging contact |
US5514616A (en) * | 1991-08-26 | 1996-05-07 | Lsi Logic Corporation | Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures |
US5258328A (en) * | 1992-03-16 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of forming multilayered wiring structure of semiconductor device |
US5422289A (en) * | 1992-04-27 | 1995-06-06 | National Semiconductor Corporation | Method of manufacturing a fully planarized MOSFET and resulting structure |
US5302551A (en) * | 1992-05-11 | 1994-04-12 | National Semiconductor Corporation | Method for planarizing the surface of an integrated circuit over a metal interconnect layer |
US5278103A (en) * | 1993-02-26 | 1994-01-11 | Lsi Logic Corporation | Method for the controlled formation of voids in doped glass dielectric films |
US5604158A (en) * | 1993-03-31 | 1997-02-18 | Intel Corporation | Integrated tungsten/tungsten silicide plug process |
US5397433A (en) * | 1993-08-20 | 1995-03-14 | Vlsi Technology, Inc. | Method and apparatus for patterning a metal layer |
JP3349001B2 (ja) * | 1994-12-29 | 2002-11-20 | ソニー株式会社 | 金属膜の形成方法 |
AU4866496A (en) * | 1995-02-24 | 1996-09-18 | Intel Corporation | Polysilicon polish for patterning improvement |
US5827780A (en) * | 1996-04-01 | 1998-10-27 | Hsia; Liang Choo | Additive metalization using photosensitive polymer as RIE mask and part of composite insulator |
US6331481B1 (en) | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
US6503827B1 (en) | 2000-06-28 | 2003-01-07 | International Business Machines Corporation | Method of reducing planarization defects |
US9496217B2 (en) * | 2009-06-04 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a via |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60102756A (ja) * | 1983-11-09 | 1985-06-06 | Toshiba Corp | 半導体装置の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4070501A (en) * | 1976-10-28 | 1978-01-24 | Ibm Corporation | Forming self-aligned via holes in thin film interconnection systems |
US4307179A (en) * | 1980-07-03 | 1981-12-22 | International Business Machines Corporation | Planar metal interconnection system and process |
US4572765A (en) * | 1983-05-02 | 1986-02-25 | Fairchild Camera & Instrument Corporation | Method of fabricating integrated circuit structures using replica patterning |
CA1260754A (en) * | 1983-12-26 | 1989-09-26 | Teiji Majima | Method for forming patterns and apparatus used for carrying out the same |
US4575402A (en) * | 1985-02-13 | 1986-03-11 | Hewlett-Packard Company | Method for fabricating conductors in integrated circuits |
US4595452A (en) * | 1985-03-11 | 1986-06-17 | Oerlikon-Buhrle U.S.A. Inc. | Method and apparatus for plasma etching |
US4621045A (en) * | 1985-06-03 | 1986-11-04 | Motorola, Inc. | Pillar via process |
-
1987
- 1987-08-17 US US07/086,120 patent/US4758306A/en not_active Expired - Fee Related
-
1988
- 1988-06-17 JP JP63148460A patent/JPH0682759B2/ja not_active Expired - Lifetime
- 1988-07-12 DE DE8888111161T patent/DE3868178D1/de not_active Expired - Fee Related
- 1988-07-12 EP EP88111161A patent/EP0303823B1/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60102756A (ja) * | 1983-11-09 | 1985-06-06 | Toshiba Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US4758306A (en) | 1988-07-19 |
EP0303823B1 (en) | 1992-01-29 |
JPH0682759B2 (ja) | 1994-10-19 |
EP0303823A1 (en) | 1989-02-22 |
DE3868178D1 (de) | 1992-03-12 |
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