JPS6459572A - Data collecting device - Google Patents

Data collecting device

Info

Publication number
JPS6459572A
JPS6459572A JP21705987A JP21705987A JPS6459572A JP S6459572 A JPS6459572 A JP S6459572A JP 21705987 A JP21705987 A JP 21705987A JP 21705987 A JP21705987 A JP 21705987A JP S6459572 A JPS6459572 A JP S6459572A
Authority
JP
Japan
Prior art keywords
data
transfer
cpu
setting
bubble memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21705987A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP21705987A priority Critical patent/JPS6459572A/en
Publication of JPS6459572A publication Critical patent/JPS6459572A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the wasteful time to send unnecessary data to a bubble memory system by throwing away the data unnecessary to preserve and transferring the data necessary to preserve to a bubble memory based on the setting of a transfer judging switch. CONSTITUTION:For a buffer amplifier part 1, only the maximum number of analog input signals is prepared, the buffer amplifier part 1 is connected to a (ch) setting selecting part 2 and an analog input signal is selected by a CPU part 4 as needed. when the writing to a memory part 5 of the data is completed, a control instruction is issued from the CPU part 4 and the data accumulated at the memory part 5 are transferred to a bubble memory system part 6. Then, by inputting to the CPU 4 whether or not transfer is executed by a transfer judging switch 7, for example, when the transfer judging switch 7 is the setting not to transfer the data, the data transfer is omitted prepared fro a next analog data input and the time necessary to the data transfer is omitted.
JP21705987A 1987-08-31 1987-08-31 Data collecting device Pending JPS6459572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21705987A JPS6459572A (en) 1987-08-31 1987-08-31 Data collecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21705987A JPS6459572A (en) 1987-08-31 1987-08-31 Data collecting device

Publications (1)

Publication Number Publication Date
JPS6459572A true JPS6459572A (en) 1989-03-07

Family

ID=16698186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21705987A Pending JPS6459572A (en) 1987-08-31 1987-08-31 Data collecting device

Country Status (1)

Country Link
JP (1) JPS6459572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120944A (en) * 1984-07-10 1986-01-29 Fuji Photo Film Co Ltd Formation of color image

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120944A (en) * 1984-07-10 1986-01-29 Fuji Photo Film Co Ltd Formation of color image

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