JPS645786B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission control system in a loop transmission system, and more particularly to a data transmission control system that performs transmission control to prevent contention.

In a method in which a single loop transmission path shared by multiple data transmission devices is multiplexed and transmitted message by message in a time-division manner, messages transmitted from each transmission device must be prevented from colliding on the loop transmission path. Therefore, control is performed such that at most one data transmission device transmits a message on the transmission path at a certain time.

In this control, a specific master control device is connected to the loop transmission path, and this master control device selects the next data transmission device to be permitted to transmit, and instructs it to transmit. This system requires the installation of a master control device, and if it fails, the entire loop transmission line will be brought down, so duplication of the master control device or installation of a backup system is required.

Another drawback is that control is always temporarily transferred to the master control device between transmissions, resulting in overhead.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission control method that eliminates the need for a specific master control device in a message multiplexing loop transmission system.

Another object of the present invention is to provide a data transmission control system that eliminates the need for a specific master control device and eliminates the overhead of temporarily returning the transmission right to the master control device when a certain transmission is completed.

The system of the present invention includes a data transmission path, and a plurality of frames each connected to the data transmission path and transmitting frame information each having an address information field for securing transmission rights for data transmission via the loop transmission path. and a data transmission device,
In a data transmission control method in a loop transmission system in which only one data transmission device transmits a message on the loop transmission path at a certain time in order to prevent transmission messages from colliding on the loop transmission path, the plurality of Each of the data transmission devices includes a timer that is reset to an initial value each time the frame information passes, and the data transmission device when the clocked value of the timer exceeds a certain value sends specific frame information to the loop transmission path. The present invention is characterized in that the transmission right is acquired when the data transmission device receives the frame information.

Next, the present invention will be explained in detail with reference to the drawings.

In general, a loop transmission system is comprised of a loop transmission path 1 and a plurality of data transmission devices 2-1, 2-2, . . . , 2-n connected thereto, as shown in FIG.

In the present invention, when each data transmission device has not acquired the transmission right, it performs a relay operation, and when it has acquired the transmission right, it transmits a message on the transmission path 1 as shown in FIG.
It can be sent with a frame structure as shown in .

The transmission right information is transmitted on the transmission line 1 in a frame structure as shown in FIG. 2a, and the data transmission device that has captured this transmission right frame acquires the transmission right.

In FIG. 2, F is a flag for identifying the beginning and end of a frame, and in the embodiment, '
It is indicated by a bit pattern of 01111110'. DA is the destination address and the address of the data transmission device that receives the frame. SA is a transmission address, which is the address of the data transmission device that sent the frame. Note that each data transmission device is assigned a unique address within the system. TKN is a specific bit pattern to indicate that this frame is a transmission right frame. (hereinafter referred to as TKN). I is a specific bit pattern to indicate that this frame is a message frame. FCS is a check bit to determine whether the frame has been transmitted normally.

If there is no transmission request in any data transmission device, the transmission right frame is circulating on the transmission path.
At this time, the DA field of the transmission right frame is a specific address (called a global address) that is determined so that all data transmission devices can receive it.
In the example, the bit pattern is '11111111').

Assume that a transmission request is generated in an existing data transmission device. Then, when the transmission right frame reaches its location, the data transmission device receives the frame and acquires the transmission right. At this time, the transmission right frame is invalidated in the downstream direction of the transmission path.

Next, the frame of the transmitted message is sent out onto the transmission path. When the transmission of the transmission message frame is completed, the transmission right frame is sent out onto the transmission path, and the transmission right is returned to the transmission path.

Since the transmission right frame must be controlled so that at most one frame exists on the transmission path, in a system where there is no master control device and all data transmission devices are equal, it is necessary to devise a method for generating it. be.

In the system of the present invention, each data transmission device has a timer that continues to measure time while a transmission request is occurring.
This timer is set to the initial value each time a transmission right frame is detected. Different initial values are set in advance for each data transmission device. This timer times out immediately after the system is powered on or when the transmission right frame disappears for some reason. Then, the data transmission device temporarily obtains the transmission right and sends a specific frame to the transmission path. In the example, this particular frame is DA=SA
= TKN frame of own address. If the specific frame goes around the transmission path and is detected on the receiving side, it means that no other data transmission device has acquired the right to transmit, so it must formally acquire the right to transmit and send the message. Start sending.

If the receiving side does not detect the specific frame within a certain period of time, there is a possibility that some other data transmission device has temporarily or officially acquired the transmission right, so the temporarily acquired transmission right is abandoned and the timer starts counting. Start over.

FIG. 3 shows an embodiment of the present invention.

In FIG. 3, the data transmission device 2 has a transmission line 1.
A signal is supplied from -IN, and the signal is output to transmission line 1-OUT. The signal from the transmission line 1-IN is demodulated by the demodulation circuit 20, and the data is transferred to the signal line 101.
Then, a clock is output to the signal line 102, respectively. The signal line 101 is connected to a zero removal circuit 21, which removes the bit '0' inserted on the transmitting side after five consecutive bits '1' to ensure transparency of information within the frame. 103. The technology for inserting/removing bit '0' to ensure transparency of information in frames is described in the "High-level data link control procedure" for communication lines.
It is known as part of. The signal on the signal line 104 becomes a logic ``1'' only when ``0'' is removed from the output line of the zero removal circuit 21, and is applied to the AND circuit 3, where it outputs the clock signal from the clock signal line 102 to the signal line 105. Control output. The signal on signal line 105 is supplied to counter 24 . The data on the signal line 101 is also given to the flag detection circuit 25 and the aport detection circuit 26, and when the flag and the aport pattern, which is a pattern of consecutive logic '1's of 7 bits or more and less than 15 bits, are detected, the data on the signal line 101 is sent to the flag detection circuit 25 and the aport detection circuit 26. Logic '1' is output to and 107, respectively. Detection of flags and aport patterns is known as part of the above-mentioned "high-level data link control procedure."
This is a counter that outputs logic '1' when a number of bits or more and less than 15 bits is given. signal line 10
The data of No. 1 is further supplied to a selector 40 for relaying frames destined for other data transmission devices. The counter 24 counts the number of clocks on the signal line 105 after being set to an initial state by a flag detection signal applied via the signal line 106.
When each value of multiples of 8, 9, 17 and 25 is counted, a logic '1' signal is output to signal lines 108, 109, 110 and 111. Signal line 1 after '0' removal
The data of 03 is supplied to the shift register 22 and held in the 8-bit hold register 25 via the signal line 112 every 8 bits (1 octet) from the bit at the time of flag detection.

The contents held in the hold register 25 are compared to the data transmission device's own address, global address and TKN by comparison circuits 26, 27 and 28.
and the comparison results are sent to the signal lines 114 and 114, respectively.
115 and 116. These results are ANDed by AND circuits 29, 30, 31, and 32, and output to signal lines 117, 118, 119, and 120 to obtain the contents of 8 bits (first octet) counting from the bit at the time of flag detection. ) is the same as its own address, flip-flop 3
3, the flip-flop 35 if the first octet is a global address, and the second octet (contents of the next 8 bits after the first octet).
If it is the same as its own address, the flip-flop 34 is set, and if the third octet (contents of the next 8 bits after the second octet) is TKN, the flip-flop 36 is set. Output lines 121, 122, 123 and 124 from flip-flops 33, 34, 35 and 36 are connected to a control circuit 50, respectively, and a reset signal line 1 is connected to these flip-flops 33-36.
25 is connected to a control circuit 50.

The contents sent out from shift register 22 via output line 126 are supplied to check circuit 37 and AND circuit 38. Signal line 121 is logic'
If it is 1', the frame is addressed to the data transmission device, so the contents of the signal line 126 are stored in the reception buffer 39.

The selector 40 is a circuit that selects any one of relay, data (user data or transmission right data) transmission, flag transmission, or abort transmission signals, and the contents of the output line 128 are transmitted through the modulation circuit 41. and output to transmission line 1-OUT.

The selector 42 is a circuit that selects either transmission data or check bits, and the data on its output line 130 is applied to the selector 40 via a zero insertion circuit 44. Zero insertion circuit 4
4 uses a known technique in the above-mentioned "high-level data link control procedure".

The selector 43 is a circuit for selecting either user data or transmission right data, and the contents of its output line 131 are applied to the selector 42 and the check bit generating circuit 45.

Control signals to each selector circuit 40, 42 and 43 are supplied from control circuit 50 via control lines 140, 141 and 142.

Next, the detailed configuration of the control circuit 50 will be explained with reference to FIG.

In FIG. 4, when there is user data to be transmitted, flip-flop 501 is set by the program and signal line 201 becomes logic '1'. When a transmission right frame with a global address is received in this state, the signal lines 123 and 124 become logic '1', the output line 202 of the AND circuit 502 becomes logic '1', and the signal is delayed by the delay circuit 503. A logic '1' is output on line 203. Furthermore, the contents of the signal line 202 are supplied to the encoder 550 via the OR circuit 549, and the encoder 550 outputs a code signal to the signal line 140 so that the selector 40 selects abort transmission. As a result, the transmission right frame is invalidated in the downstream direction of the transmission path. The content of the flag detection signal line 106 is checked and the content of the signal line 143 is the AND circuit 504.
A logical AND is performed at , and the result is input to AND circuits 505 , 506 , and 518 via signal line 204 .
The output line 205 of the AND circuit 505 becomes logic '1' when there is a transmission request and the result of checking the transmission right frame is good, and flip-flops 508, 509 and 510 are set via the OR circuit 507.

The set state of flip-flop 510 indicates that the data transmission device is transmitting. During transmission, the set state of flip-flop 508 indicates that a user data frame is being sent, and the reset state indicates that a transmission right frame or abort pattern is being sent.

Flip-flop 509 is flip-flop 5
It is used to create a state delayed by a certain period of time.

The output line 142 of the flip-flop 508 is a control signal line for the selector 530 and the selector 43, and when the logic is '1', the user data count (number of bits) and the user data are transmitted, and when the logic is '0', the transmission right data is transmitted. Select the count (number of bits) and transmission right data, respectively. The values of the user data count and transmission right data count are set by the program.

The signal on output line 207 of OR circuit 511, via OR circuit 537 and its output line 144, sets flip-flop 531 to begin the frame transmission sequence. The signal on signal line 144 further sets counter 539 to an initial state via OR circuit 538. It is also used as an initial setting signal for check bit generation circuit 44 in FIG.

The counter 539 inhibits and counts the clock signal only when the zero insertion circuit (44 in FIG. 3) inserts a '0', and when it counts 8 and 16, the signal lines 233 and 234 are set to logic '1'. ' to.

The state of output line 235 of flip-flop 531 is logic '' during the transmission of the first flag of the frame.
This signal becomes 1' and is used to load the counter 540 and generate the control signal for the selector 40.

When the signal line 233 becomes logic '1', that is, 8
When the clock advances, flip-flop 532 is set via AND circuit 541. At the same time, flip-flop 531 is reset. The output signal of flip-flop 532 is a signal that becomes logic '1' while transmitting user data or transmission right data, and the signal on output line 237 is a signal that becomes logic '1' while transmitting user data or transmission right data.
2 is supplied to an encoder 547 to generate a signal for controlling the signal.

The counter 540 subtracts 1 from the amount of transmission data loaded on the signal line 235 at clock timing, and when the result becomes '0', the counter 540
outputs a logic '1'. The signal on the signal line 238 is supplied to the reset terminal of the flip-flop 501, the AND circuit 542, the set terminal of the flip-flop 533, and the reset terminal of the flip-flop 532, and is also used to clear the counter 539 via the OR circuit 538. Ru.

Output line 240 of flip-flop 533 becomes a logic '1' during check bit transmission (for 16 clocks) and this state is provided to encoder 547 to generate the control signal for selector 42. When the counter 539 counts the value '16', the signal line 234
becomes logic '1' and the output line 24 of the AND circuit 543
A value of 1 sets flip-flop 534, resets flip-flop 533, and outputs OR circuit 5 to clear counter 539.
It becomes an input to 38.

Output line 242 of flip-flop 534 goes to logic '1' during sending out the last flag of the frame (8 clocks) and its state is passed to encoder 550 via OR circuit 548 to generate the control signal for selector 40. Supplied.

When the counter 539 counts 8, the AND circuit 5
Output line 243 of 44 goes to logic '1' and is used to reset flip-flop 534, flip-flops 508 and 509.

The output line 229 of the one-shot circuit 529 becomes logic '1' for a certain period of time from the time when the signal line 243 changes from logic '1' to logic '0'.

The reset operation of flip-flop 509 is delayed by a delay circuit 512 for a certain period of time. The output line 244 of flip-flop 509 is connected to flip-flop 5.
31 and 535.

Immediately after the transmission of the user data is completed, the delay circuit 51
During the delay time of 2, signal line 244 is at logic '1', so flip-flop 531 is set and flip-flop 535 is not set. Therefore, the transmission sequence of the next transmission right frame is started. When the sending of the transmission right data is completed, the signal line 244 is
Since it is logic '0', flip-flop 531 is not set and flip-flop 535 is set. and output line 24 of flip-flop 535.
In order to reset the flip-flop 510 and invalidate the relay data following the transmission right frame, the bit 5 becomes logic '1' for 8 bits after sending the transmission right frame, so that the selector 40 selects abort transmission. is applied to encoder 550.

Next, the transmission right recovery operation will be explained in detail with reference to FIG.

As mentioned above, when a transmission request occurs, signal line 2
01 becomes logic '1'. As a result, the output line 301 of the OR circuit 601 in FIG.
2 is set to logic '1' for a certain period of time, and the initial value A is loaded into the counter 604. The initial value A is a different value for each data transmission device, and is manually set at the time of installation.

In the AND circuit 602, the signal line 201 is logic '1'.
When the signal line 212 indicating that transmission is in progress and the output line 213 of the flip-flop 607 are at logic '0', a clock signal is supplied to the counter 604, and the contents of the counter are decremented by one.

When a transmission right frame is detected, the output line 211 of the AND circuit 518 in FIG. 4 becomes logic '1', and the initial value is loaded into the counter 604 via the OR circuit 601 and one shot circuit 603 in FIG. As long as the right frame exists, the counter 604 will never become '0'.

Immediately after the power is turned on to the system or when the transmission right frame disappears for some reason, the content of the counter 604 becomes '0' and the output line 30
5 becomes logic '1' and generates an interrupt to the program.

The interrupted program transfers the transmission right buffer 52 (third
After rewriting the own address in the DA field in FIG. 4, flip-flop 510 (FIG. 4) and flip-flop 607 (FIG. 5) are set.

When the flip-flop 510 is set, the same operation as that from when the flip-flop 508 described above is reset is performed, and a transmission right frame (specific frame) is sent out on the transmission path.

On the other hand, when the flip-flop 607 is set and the signal line 213 becomes logic '1', the initial value B is loaded into the counter 609 via the one-shot circuit 605 at the rising edge, and the clock signal is supplied to the counter 609 via the AND circuit 606. , its contents are decremented by one. The initial value B is the same value for each data transmission device.

The signal on the signal line 213 is applied to an OR circuit 549 (FIG. 4) so that after sending a specific frame, the selector 40 selects the abort pattern without performing any relay operation until the contents of the counter 609 reach '0'. .

When a particular frame is received, output lines 121 and 1 of flip-flops 33 and 36 in FIG.
24 becomes a logic '1', and as a result, the output line 209 of the AND circuit 506 in FIG. 4 becomes a logic '1' if the check result is good. As a result, AND circuit 51
5 output line 214 becomes logic '1' and OR circuit 50
7, the same operation as when receiving the transmission right frame described above is performed.

On the other hand, in FIG. 5, when the signal line 209 becomes logic '1', the flip-flop 607 is reset and the subtraction of the counters 604 and 609 is stopped.

If a specific frame is not received after a certain period of time, the content of the counter 609 becomes '0', and its output line 306 becomes logic '1', and the one-shot circuit 61
0 to generate a pulse on the signal line 307. As a result, flip-flop 607 is reset, counter 604 is loaded with the initial value A, and the above-described operation is repeated.

Since the above event occurs when a specific frame is sent simultaneously by two or more different data transmission devices (except in the case of a failure), the initial value A should be set to a different value for each data transmission device. If you leave it there,
If this process is repeated several times, any one data transmission device will definitely succeed in receiving the specific frame and can recover the lost transmission right frame.

The present invention has the effect of eliminating the need for countermeasures such as duplicating the master control device because a master control device is not particularly required for data transmission control on a loop transmission path.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the loop transmission system, FIG. 2 is a diagram for explaining the structure of a frame, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram for explaining the structure of a frame. A diagram showing the detailed configuration of the control circuit and FIG. 5 are diagrams showing the transmission right recovery control circuit in detail. In Figures 1 to 4, 1, 1-IN, 1
-OUT...Transmission line, 2, 2-1, 2-2, 2-
3, 2-4,...2-n...data transmission device, 20
... Demodulation circuit, 21 ... 0 detection circuit, 22 ... Shift register, 24 ... Counter, 25 ... Hold register, 26, 28 ... Comparison circuit, 29,
30, 32...AND circuit, 33, 34, 36...
...Flip-flop circuit, 37...Check circuit, 39...Reception buffer, 40, 42, 43...
...Selector, 41...Modulation circuit, 44...0 insertion circuit, 45...Check bit generation circuit, 50...
...Control circuit, 539, 540, 604, 609...
...Counter, 547,550...Encoder, 5
01,508,509,510,531,53
2,533,534,535,607...Flip-flop, 600...Transmission right recovery control circuit, 5
29,603,605...One shot circuit.

Claims (1)

[Scope of Claims] 1. The data transmission device comprising a loop transmission path and a plurality of data transmission devices each connected to the loop transmission path and assigned a unique address, and which has acquired a transmission right frame. In a data transmission control method in a loop transmission system in which only one of the plurality of data transmission devices transmits a message to the loop transmission path, each of the plurality of data transmission devices is provided with a timer that is reset to an initial value every time the transmission right frame passes; The data transmission device whose timer value exceeds a certain value performs a first process of sending a specific frame having the unique address assigned to itself as the destination address to the loop transmission path; a second process of acquiring a transmission right when the specific frame is received within a predetermined time from sending the frame; and not receiving the specific frame within the predetermined time from sending the specific frame. A data transmission control method in a loop transmission system, characterized in that a third process of resetting the timer itself is performed.