JPS6457758A - Eeprom and its manufacture - Google Patents
Eeprom and its manufactureInfo
- Publication number
- JPS6457758A JPS6457758A JP63134266A JP13426688A JPS6457758A JP S6457758 A JPS6457758 A JP S6457758A JP 63134266 A JP63134266 A JP 63134266A JP 13426688 A JP13426688 A JP 13426688A JP S6457758 A JPS6457758 A JP S6457758A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- polysilicon
- substrate
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 4
- 229920005591 polysilicon Polymers 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE: To facilitate manufacturing memory cells and reduce the size by forming a flash EEPROM, using a cell structure having no contact. CONSTITUTION: Word lines 12 are formed with a second layer polysilicon along an Si substrate, and bit lines 13 are formed at a lower part of a thick thermosetting Si layer 14 in the surface of the Si substrate 11, thereby forming source regions 15 and drain regions 16 of memory cells 10. Floating gates 17 are formed with a first layer polysilicon layer across the adjacent two bit lines. Erasing windows 18 are formed near the source regions 15 of the cells, and inner silicon oxide layer 19 is thinner than a gate oxide film 20 at other parts of the channel regions. This improves the coupling between a word line 12 forming layer and floating gate 17 forming layer and minimizes the possibility of interferences on read. The memory cells 10 have no need for contacts between the polysilicon layer and substrate or between the polysilicon layers, in a cell array.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5619687A | 1987-06-01 | 1987-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457758A true JPS6457758A (en) | 1989-03-06 |
Family
ID=22002818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63134266A Pending JPS6457758A (en) | 1987-06-01 | 1988-05-31 | Eeprom and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457758A (en) |
-
1988
- 1988-05-31 JP JP63134266A patent/JPS6457758A/en active Pending
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