JPS645762B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a horizontal synchronization extraction circuit, and more particularly, a horizontal synchronization extraction circuit that can reliably extract any horizontal synchronization period by digital processing from a composite video signal whose polarity is randomly inverted in units of horizontal synchronization periods. Regarding.

Conventionally, only the horizontal synchronization signal was separated from the composite video signal of television, or specific information (VIR reference signal for specific improvement of transmission) was inserted into a specific horizontal synchronization period within the vertical retrace period and transmitted. When separating and extracting multiplexed signals for still images, teletext, etc.), in order to correctly extract a specific horizontal synchronization period in each even and odd numbered field that is interlaced, the first Japanese Patent Publication No. 57-45510 discloses a method of detecting a horizontal synchronizing signal and determining the oil release period using this as a reference. This method separates only the horizontal synchronization signal from the video signal and the composite synchronization signal separated by using the difference in the pulse width of the horizontal synchronization signal, vertical synchronization signal, and equalization pulse. As in the ``Video Signal Transmission System'' (Patent Application No. 58-90940) filed on May 24, 1958, the video signal including the horizontal synchronization signal is transmitted in units of horizontal scanning periods for the purpose of averaging and concealing the transmission spectrum. It cannot be applied to a transmission method in which the polarity is randomly inverted and the white level of the inverted video signal exceeds the pedestal level of the uninverted horizontal synchronizing signal. Furthermore, as a method for detecting vertical synchronization signals that is resistant to cracking or missing pulses that occur when there is a weak electric field or a lot of noise, a method using digital processing instead of the conventional analog processing was developed.
-29108, but as will be explained later, this method also has the disadvantage of generating erroneous detection signals when used in the above-mentioned video signal transmission method, and cannot be used as a standard for horizontal synchronization extraction. Can not.

An object of the present invention is to provide a horizontal synchronization extraction circuit that solves the above-mentioned problems, detects a vertical synchronization signal from a composite video signal transmitted with randomly reversed polarity, and can extract a horizontal synchronization signal or a horizontal synchronization period without error. The goal is to provide the following.

The horizontal synchronization extraction circuit of the present invention includes a vertical synchronization signal detection circuit that separates and detects a vertical synchronization signal from a composite synchronization signal by digital processing using clock pulses with a high repetition frequency that is an integral multiple of the horizontal synchronization frequency; a start pulse detection circuit that detects the first horizontal synchronization signal pulse that is subsequently sent; a frequency division counter that is activated by the output of the start pulse detection circuit and counts the clock pulses to generate pulses at the horizontal synchronization frequency; at least one pulse counter that counts the output of the frequency division counter by a predetermined number and generates an output pulse; and a control circuit that controls the frequency division counter using the pulse counter or the output of the start pulse detection circuit. The vertical synchronization signal detection circuit includes a clock pulse generation circuit that generates the clock pulses, and a clock pulse generation circuit that is reset by the composite synchronization signal and counts the clock pulses to generate a horizontal return longer than the interval between the vertical synchronization pulses in the composite synchronization signal. a clock pulse counter that generates a detection output when counting a predetermined number of pulses corresponding to a period shorter than the line period; and a clock pulse counter that generates a detection output when counting a predetermined number of pulses corresponding to a period shorter than the line period; The device is constructed by comprising a flip-flop that generates a pulse for which the flip-flop is determined, and a pulse width detection circuit that detects the pulse width of the output pulse of the flip-flop and generates a vertical synchronization signal detection output.

Next, the present invention will be explained in detail with reference to the drawings.
First, the vertical synchronization signal detection circuit that serves as a reference for horizontal synchronization extraction will be explained. Figure 1 shows the special public service issued in 1983.
FIG. 2 is a block diagram of a conventional example of a vertical synchronization signal detection circuit using digital processing described in Publication No. 29108, and FIG. 2 is a time chart illustrating its operation. Second
Figure 2b separated from the composite video signal shown in Figure a.
A composite synchronization signal is applied from input 100 of FIG. 1 to clock pulse counter 1 to reset it. Clock pulse counter 1 receives the 204K signal applied to input 101 when the composite synchronization signal is removed.
Hz clock pulses are started counting, and the interval L between equalization pulses is longer than the interval L between vertical sync pulses.
A pulse is generated at output 102 when a predetermined number of pulses corresponding to a shorter time period (four pulses in the example circuit of FIG. 1) are counted. This output pulse is applied to the reset terminal of RS flip-flop 2, the leading edge of the pulse is determined by the composite synchronization signal branched from input 100 and applied to the set terminal, and the trailing edge is determined by the output of clock pulse counter 1. The output pulse shown in FIG. 2c is generated.
This output pulse is generated 4 times after clock pulse counter 1 starts counting for each synchronizing signal pulse.
The width of the pulse increases by the time τ until counting the second pulse, and since L>τ>l is selected, one continuous wide pulse A is generated for the vertical synchronization signal period. can get. The pulse width detection circuit 3 has a pulse output 103 of Fig. 2c and 31.5KHz.
Count the AND output with the clock pulse 104,
When four consecutive pulses are counted, a vertical synchronization signal detection pulse shown in FIG. 2d is sent to the output 105. Since this circuit is configured to be reset by the inverted output of pulse input 103,
The vertical synchronization signal can be detected by generating detection pulses only for wide pulses. However, for the signal shown in Figure 2e whose polarity is randomly inverted using the horizontal synchronization period described above, the synchronization separation circuit cannot separate only the synchronization signal, and the composite synchronization signal contains an inverted image. Some of the signals are mixed in, and the interval between the video signals, that is, the horizontal blanking period T, is smaller than the counting period τ of the clock pulse counter 1, so the output of the flip-flop 2 becomes as shown in FIG. A wide pulse B is generated. That is, if two or more inversion sections continue, there is a possibility that an erroneous vertical synchronization signal detection pulse may be generated depending on the level of the video signal.
In addition, in the case of the horizontal synchronization extraction circuit described in Japanese Patent Publication No. 57-45510, vertical synchronization is detected by passing the composite synchronization signal separated by the synchronization separation circuit through a low-pass filter, but the image signal level in the inversion section is When the image signal level is high, an output similar to that of the vertical synchronizing signal is generated, and when the image signal level is low, the horizontal synchronizing signal is not received either, both of which cause malfunctions. One way to prevent malfunctions caused by such inverted image signals is to use the vertical synchronization signal detection circuit shown in FIG.
Measures must be taken to prevent the horizontal retrace period T from becoming continuous pulses B for the composite video signal shown in FIG. 2e.

FIG. 3 is a block diagram of an embodiment of the present invention using a vertical synchronization signal detection circuit with the above-mentioned measures, and a clock pulse generation circuit with a repetition frequency (8.056MHz) that is ²⁹ times the horizontal synchronization frequency of 15.734KHz. 4
a vertical synchronization signal detection circuit 5 that digitally detects a vertical synchronization signal from a composite synchronization signal input 106, and a vertical synchronization signal detection circuit 5 that is connected to this output and counts equalization pulses sent following the vertical synchronization signal to detect the first horizontal synchronization signal. A start pulse detection circuit 6 that generates a start pulse output 107 with a signal pulse, and a frequency division counter 7 that starts counting 8.056 MHz clock pulses 108 with this start pulse and generates a pulse output 109 with a horizontal synchronous frequency synchronized with the start pulse. , an end pulse counter 8 which counts these pulses and generates an end pulse 110 that matches the last horizontal synchronizing signal pulse, and a frequency division counter 7 which is composed of a flip-flop and an AND circuit and controls the frequency division counter 7 with a start pulse output 107 and an end pulse 109. It is composed of a control circuit 9. FIG. 4 is a block diagram of one embodiment of the vertical synchronization signal detection circuit 5 in FIG.
1, a clock pulse counter 11 consisting of two hexadecimal counters and an AND circuit, a flip-flop 2 and a pulse width detection circuit 3, which are the same as in FIG. The operations shown in FIGS. 3 and 4 will be explained below using the time chart shown in FIG. 5. The composite video signal of FIG. 5a (same as FIG. 2e) whose polarity has been randomly inverted is separated by a synchronization separation circuit,
A signal mixed with the image signal shown in FIG. 5b is applied as the composite synchronization signal input 106 of FIGS. 3 and 4. Clock pulse counter 11 in Fig. 4
When the composite synchronization signal input 106 becomes zero, it starts counting 8.056 MHz clock pulses 108 as shown in FIG. 5c, and when the 48th pulse is counted, an output pulse is sent to the AND circuit output. As in the case of FIG. 1, the Q output 111 of the flip-flop 2 provides an output whose pulse width is expanded by the pulse count time τ' as shown in FIG. 5d. The time τ' required to count 48 8.056MHz clock pulses has a relationship of l'<τ'<T' with respect to the color TV signal waveform standard shown in Figure 6. For the vertical synchronization signal, it becomes a continuous output pulse like B', and for the vertical synchronization signal, it becomes a continuous output pulse like A'.
The vertical synchronizing signal detection pulse shown in FIG. 5e is reliably outputted to the output 112 of the pulse width detection circuit 3 without being disturbed by the inverted video signal. The start pulse detection circuit 6 in FIG. 3 counts the equalization pulse C following the A' pulse in FIG. 5d, and detects the start pulse in FIG. Occur. This output is applied to the set terminal of the flip-flop in control circuit 9, opening the AND gate and sending clock pulse 108 to frequency divider counter 7. The frequency division counter 7 divides the frequency by ^1/29 and sends the pulse shown in FIG. 5g synchronized with the horizontal synchronization signal to the output 109. The end pulse counter 8 counts this pulse and generates the end pulse shown in FIG. 5h, which corresponds to the last horizontal synchronizing signal pulse. This end pulse output 110
is applied to the reset terminal of the flip-flop of control circuit 9 to close the AND gate and stop the operation of frequency division counter 7. FIG. 5i shows the control voltage waveform of the AND gate. As described above in detail, the second and subsequent horizontal synchronization signals of each field are reproduced at the output 109 regardless of the number of corners or odd numbers. If a crystal controlled oscillator is used in the 8.056MHz clock pulse generation circuit 4, a high frequency can be ensured, and the horizontal synchronization frequency on the input signal side is also normally strictly regulated, so the horizontal synchronization signal of the input signal and the reproduced horizontal synchronization The time difference with the signal is small and does not pose a problem. That is, if the difference between the input signal horizontal synchronization frequency and the frequency obtained by dividing the clock pulse is, for example, 1×10 ^-5 , then the range of variation in the phase of the first horizontal synchronization signal pulse generated by frequency division is 8.056. It is less than the cycle of MHz clock pulse 1 and less than 0.002H with respect to the horizontal synchronization period H,
0.0025H is added to this for the final horizontal synchronization signal pulse (253rd or 254th) of each field.
It will be 0.0045H or less. For example, if we consider that the polarity of the video signal is inverted at the front porch section of the horizontal synchronizing signal shown in Figure 6 or at the back porch section after color burst, this value is determined by the time width of that section.
It is sufficiently small compared to 0.02H and can be used as a reference signal for polarity reversal without any problems.

In the embodiment described above, the clock pulse counter 11 counts the 48th pulse and sends out an output, and the counting time τ' is set shorter than the horizontal retrace period T' before the color burst. Therefore, it operates even if the inversion reference level for polarity inversion is the pedestal level. However, if the inversion reference level is set to the image signal side of the pedestal level, for example, to an intermediate value between the peak value of the synchronization signal and the video white level, the color burst is set to the pulse height of the synchronization signal as shown in Figure 6. Since it is determined to be approximately half of S, it is sufficient if τ'<T. In addition, in the embodiment, the frequency of the clock pulse is selected to be ²⁹ times the horizontal synchronization frequency, but it goes without saying that other values may also be used. The decision should be made by taking these into consideration. In the embodiment shown in FIG. 3, the start pulse detection circuit 6 counts the equalization pulse C (cf. 111) shown in FIG. 5 d following the vertical synchronization signal detection pulse (cf. 112) shown in FIG. 5 e. It is configured to detect the first horizontal synchronizing signal pulse at It may also be possible to detect the
A configuration in which the first pulse that arrives after a certain period of time from the vertical synchronization signal detection pulse is detected is also possible. Furthermore, it goes without saying that the pulse width detection circuit 3 shown in the embodiment shown in FIG. 4 can use other methods described in the same publication as well as the conventional example shown in FIG. 1 described in Japanese Patent Publication No. 57-29108. . Although the embodiment shown in FIG. 3 is configured to output the second and subsequent reproduction horizontal synchronizing signals, it is easy to output the first pulse at the same time, and the end pulse counter 8 is not necessarily It is clear that it is not necessary to use the final horizontal synchronization pulse, and that any horizontal synchronization period can be easily extracted using two pulse counters.

As described in detail above, according to the horizontal synchronization extraction circuit of the present invention, the polarity of the video signal and the horizontal synchronization signal is randomly inverted in units of horizontal synchronization periods, and the inverted video signal level is changed to a synchronization signal that is not inverted. Even if the video signal exceeds the pedestal level and mixes into the composite synchronization signal separated by the separation circuit, the horizontal synchronization signal of each field can be extracted without error, and the inverted control signal can be generated or generated using this as a reference. This has the advantage of being able to extract signals from arbitrary horizontal synchronization sections.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional vertical synchronization signal detection circuit using digital processing, FIG. 2 is a time chart explaining its operation, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 5 is a block diagram of an embodiment of the vertical synchronization signal detection circuit shown in FIG. 5. FIG. 5 is a time chart explaining the operation of FIGS.
FIG. 6 is a reference waveform diagram of a synchronization signal of a color television signal. 1, 11...Clock pulse counter, 2...
Flip-flop, 3...Pulse width detection circuit,
4, 10... Clock pulse generation circuit, 5... Vertical synchronization signal detection circuit, 6... Start pulse detection circuit, 7... Frequency division counter, 8... End pulse counter, 9... Control circuit.

Claims (1)

[Claims] 1. A vertical synchronization signal detection circuit that separates and detects a vertical synchronization signal from a composite synchronization signal by digital processing using a clock pulse with a high repetition frequency that is an integral multiple of the horizontal synchronization frequency, and a vertical synchronization signal detection circuit that separates and detects a vertical synchronization signal from a composite synchronization signal using a clock pulse with a high repetition frequency that is an integral multiple of the horizontal synchronization frequency, and a start pulse detection circuit for detecting signal pulses; a frequency division counter that is activated by the output of the start pulse detection circuit and counts the clock pulses to generate pulses at the horizontal synchronization frequency; and the output of the frequency division counter is predetermined. the vertical synchronization signal detection circuit, the vertical synchronization signal detection circuit comprising: at least one pulse counter that counts the number of pulses and generates an output pulse; and a control circuit that controls the frequency division counter using the pulse counter or the output of the start pulse detection circuit; includes a clock pulse generation circuit that generates the clock pulses, and a clock pulse generation circuit that is reset by the composite synchronization signal and counts the clock pulses to a period that is longer than the interval between vertical synchronization pulses in the composite synchronization signal and shorter than the horizontal retrace interval. a clock pulse counter that generates a detection output when counting a corresponding predetermined number of pulses; and a flip-flop that generates a pulse whose leading and trailing edges are determined by the composite synchronization signal and the detection output of the clock pulse counter. and a pulse width detection circuit that detects the pulse width of the output pulse of the flip-flop and generates a vertical synchronization signal detection output.