JPS6457487A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6457487A
JPS6457487A JP62214716A JP21471687A JPS6457487A JP S6457487 A JPS6457487 A JP S6457487A JP 62214716 A JP62214716 A JP 62214716A JP 21471687 A JP21471687 A JP 21471687A JP S6457487 A JPS6457487 A JP S6457487A
Authority
JP
Japan
Prior art keywords
sram
output signal
common data
information
multibit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62214716A
Other languages
Japanese (ja)
Inventor
Masaaki Kubodera
Kimiko Nishizawa
Masahiro Shioya
Katsuro Sasaki
Takao Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62214716A priority Critical patent/JPS6457487A/en
Priority to KR1019880010509A priority patent/KR890004327A/en
Publication of JPS6457487A publication Critical patent/JPS6457487A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the generation of a noise and to prevent the malfunction of a SRAM, by changing an arrangement length at every common data line or every output signal line in the SRAM of a multibit system. CONSTITUTION:In the SRAM (of multibit system) for outputting plural information by one information reading operation, a wiring length is changed at every common data line I/O or output signal line DBus. Accordingly, the load capacity and the load resistance of the individual common data lines I/O or the individual output signal lines DBus are different and the timing of the output of the information is different. Thereby, the noise generated in a reference potential VSS or a power source potential VCC can be dispersed to prevent the malfunction in the input step circuit of the SRAM.
JP62214716A 1987-08-28 1987-08-28 Semiconductor integrated circuit device Pending JPS6457487A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62214716A JPS6457487A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device
KR1019880010509A KR890004327A (en) 1987-08-28 1988-08-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214716A JPS6457487A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6457487A true JPS6457487A (en) 1989-03-03

Family

ID=16660438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214716A Pending JPS6457487A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6457487A (en)

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