JPS6455936A - Frame detection circuit - Google Patents

Frame detection circuit

Info

Publication number
JPS6455936A
JPS6455936A JP62213317A JP21331787A JPS6455936A JP S6455936 A JPS6455936 A JP S6455936A JP 62213317 A JP62213317 A JP 62213317A JP 21331787 A JP21331787 A JP 21331787A JP S6455936 A JPS6455936 A JP S6455936A
Authority
JP
Japan
Prior art keywords
pattern
detection
rom
frame
dissidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62213317A
Other languages
Japanese (ja)
Inventor
Masashi Oba
Kunio Takada
Shinzo Tsurumaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62213317A priority Critical patent/JPS6455936A/en
Publication of JPS6455936A publication Critical patent/JPS6455936A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To decrease the circuit scale by providing a function required for frame detection such as operation as a shift register in a built-in table and detection of coincidence/dissidence between detected pattern and frame pattern to a ROM. CONSTITUTION:In giving 0000000 and 1 from a FF 72 as data to a ROM 71, a flag representing odd/even number and a flag representing whether or not the pattern is coincident with a 7-bit pattern are inserted to a specific bit and 10000000 is read as a generated pattern and fed to the FF 72 via a gate 73, and the processing similar to above is executed repetitively. In discriminating it that a synchronization protection circuit 8 detects a multi-frame pattern, a table switching signal is sent. The ROM 71 has a 2nd table having a pattern and flag required for the operation after the said detection in addition to the said table. The 2nd table continues detecting coincidence/dissidence of the input data with self-running and the circuit 8 checks it and sends a table switching signal in the set state and the pattern detection is switched.
JP62213317A 1987-08-27 1987-08-27 Frame detection circuit Pending JPS6455936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213317A JPS6455936A (en) 1987-08-27 1987-08-27 Frame detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213317A JPS6455936A (en) 1987-08-27 1987-08-27 Frame detection circuit

Publications (1)

Publication Number Publication Date
JPS6455936A true JPS6455936A (en) 1989-03-02

Family

ID=16637145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213317A Pending JPS6455936A (en) 1987-08-27 1987-08-27 Frame detection circuit

Country Status (1)

Country Link
JP (1) JPS6455936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512750U (en) * 1991-07-29 1993-02-19 日本精工株式会社 Self-propelled linear guide device
EP3424638A1 (en) 2017-07-04 2019-01-09 Akira Sugiyama Flexible multi-table device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512750U (en) * 1991-07-29 1993-02-19 日本精工株式会社 Self-propelled linear guide device
EP3424638A1 (en) 2017-07-04 2019-01-09 Akira Sugiyama Flexible multi-table device

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