JPS6455665A - Data bus mutual conversion system - Google Patents

Data bus mutual conversion system

Info

Publication number
JPS6455665A
JPS6455665A JP21326587A JP21326587A JPS6455665A JP S6455665 A JPS6455665 A JP S6455665A JP 21326587 A JP21326587 A JP 21326587A JP 21326587 A JP21326587 A JP 21326587A JP S6455665 A JPS6455665 A JP S6455665A
Authority
JP
Japan
Prior art keywords
bit
timing
signal
data
separating means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21326587A
Other languages
Japanese (ja)
Inventor
Masashi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP21326587A priority Critical patent/JPS6455665A/en
Publication of JPS6455665A publication Critical patent/JPS6455665A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To enable even a 16-bit CPU to access an option board connected to an 8-bit CPU by providing a timing indicating means which indicates the timing when an address signal and a data signal are separated from each other by a separating means. CONSTITUTION:This data bus compatible system where CPUs different in bit constitution like an 8-bit arithmetic processing unit CPU and a 16-bit are used together is provided with a separating means which separates the multiplexed signal of the address signal and the data signal into the address signal and the data signal and a timing indicating means 7 which indicates the timing of this separation in the separating means 2. For example, multiplexed address signal and data signal outputted from the 16-bit CPU are separated in parallel by the separating means at the timing indicated by the timing indicating means, and therefore, data can be sent to the 8-bit device.
JP21326587A 1987-08-27 1987-08-27 Data bus mutual conversion system Pending JPS6455665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21326587A JPS6455665A (en) 1987-08-27 1987-08-27 Data bus mutual conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21326587A JPS6455665A (en) 1987-08-27 1987-08-27 Data bus mutual conversion system

Publications (1)

Publication Number Publication Date
JPS6455665A true JPS6455665A (en) 1989-03-02

Family

ID=16636235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21326587A Pending JPS6455665A (en) 1987-08-27 1987-08-27 Data bus mutual conversion system

Country Status (1)

Country Link
JP (1) JPS6455665A (en)

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